JPH04206901A - Laminated thermistor - Google Patents
Laminated thermistorInfo
- Publication number
- JPH04206901A JPH04206901A JP33904390A JP33904390A JPH04206901A JP H04206901 A JPH04206901 A JP H04206901A JP 33904390 A JP33904390 A JP 33904390A JP 33904390 A JP33904390 A JP 33904390A JP H04206901 A JPH04206901 A JP H04206901A
- Authority
- JP
- Japan
- Prior art keywords
- thermistor
- constant
- temperature
- resistance
- range
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010030 laminating Methods 0.000 abstract description 3
- 238000003475 lamination Methods 0.000 abstract 1
- 239000002003 electrode paste Substances 0.000 description 8
- 239000000758 substrate Substances 0.000 description 7
- 239000003990 capacitor Substances 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002265 prevention Effects 0.000 description 2
- 239000002002 slurry Substances 0.000 description 2
- 229910018648 Mn—N Inorganic materials 0.000 description 1
- 229910018651 Mn—Ni Inorganic materials 0.000 description 1
- 101100489867 Mus musculus Got2 gene Proteins 0.000 description 1
- 229910017709 Ni Co Inorganic materials 0.000 description 1
- 229910003267 Ni-Co Inorganic materials 0.000 description 1
- 229910003262 Ni‐Co Inorganic materials 0.000 description 1
- 229910018106 Ni—C Inorganic materials 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000007606 doctor blade method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000004014 plasticizer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野］
この発明は積層サーミスタに関し、特にたとえば突入電
流防止用積層サーミスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a laminated thermistor, and particularly to a laminated thermistor for preventing rush current.
スイッチング電源では、交流入力を直接ダイオードによ
って整流し、それを電解コンデンサで平滑化する。その
ため、スイッチング時に電解コンデンサにサージ電流が
流れ、これを突入電流という。この突入電流はたとえば
百数十アンペアという大電流であり、スイッチ接点やダ
イオードの劣化を早めてしまう。この突入電流を抑制す
る方法の１つとして、従来より、ザーミスタの動特性を
利用するものがある。ずなわぢ、ザーミスタは常温で数
Ω〜数十Ωの抵抗値を有し、スイッチがオンされたとき
この抵抗値によって突入電流を抑制する。また、ザーミ
スタはスイッチング電源の安定状態では自己発熱し、そ
の抵抗値は常温の１／１０程度になるので、電力ロスな
どの支障は生じない。In a switching power supply, AC input is directly rectified by a diode and smoothed by an electrolytic capacitor. Therefore, a surge current flows through the electrolytic capacitor during switching, and this is called an inrush current. This rush current is a large current of, for example, hundreds of amperes, and accelerates the deterioration of switch contacts and diodes. One of the conventional methods for suppressing this rush current is to utilize the dynamic characteristics of the thermistor. The thermistor has a resistance value of several ohms to several tens of ohms at room temperature, and this resistance value suppresses inrush current when the switch is turned on. Further, the thermistor self-heats when the switching power supply is in a stable state, and its resistance value is about 1/10 of that at room temperature, so problems such as power loss do not occur.
このような突入電流防止用サーミスタとして、常温付近
で使用できるものとしては、Ｍｎ−Ｎ系、Ｍ−Ｎｉ−Ｃ
ｏ系またはＭｎ−Ｎｉ ＝Ｃｏ系などの酸化物があり、
また、８００℃前後で使用できるものとしてはＺｒ−Ｙ
系酸化物などがある。As such inrush current prevention thermistors, Mn-N type and M-Ni-C are usable at room temperature.
There are oxides such as o-based or Mn-Ni = Co-based,
In addition, Zr-Y can be used at around 800℃.
There are various types of oxides.
これらのザーミスタは温度係数が大きい上、形状や抵抗
値の自由度が大きく、また安価である等の利点を有して
いる。These thermistors have advantages such as a large temperature coefficient, a large degree of freedom in shape and resistance value, and low cost.
［発明が解決しようとする課題］
ごのような半導体特性を利用するサーミスタの抵抗温度
特性は以下の式で表される。[Problems to be Solved by the Invention] The resistance-temperature characteristics of a thermistor that utilizes the semiconductor characteristics described above are expressed by the following equation.
Ｒ，＝Ｒ２ｅｘｐ （（１／Ｔ＋ −１／Ｔｚ ）Ｂ
ＩＴ、、Ｔ２ ： 温度（ｋ）
Ｒ，、Ｒ２： 温度Ｔ、、Ｔ２における抵抗値Ｂ（ｋ
） ： ・す゛−ミスタ定数この式からよく分か
るように、従来のサーミスタでは、抵抗温度特性が直線
的でないため、特に低温側での抵抗値が危、激に増大し
てしまう。したがって、従来のサーミスタを突入電流防
止用として用いるには、低温側での抵抗値を低く安定化
させる必要がある。そのため、従来では、数種類の負特
性サーミスタと数種類の定抵抗体とを組み合わせたり、
または、サーミスタ定数Ｂに制約を設けて用いなければ
ならない等、実用性に問題があった・
それゆえに、この発明の主たる目的は、低温側において
も抵抗温度特性が安定な、積層サーミスタを提供するご
とである。R,=R2exp ((1/T+ -1/Tz)B
IT,,T2: Temperature (k) R,,R2: Resistance value B(k) at temperature T,,T2
) : ・Su-mister constant As can be clearly seen from this equation, in conventional thermistors, the resistance temperature characteristic is not linear, so the resistance value increases dangerously and dramatically, especially at low temperatures. Therefore, in order to use a conventional thermistor for inrush current prevention, it is necessary to stabilize the resistance value at a low temperature side. Therefore, in the past, several types of negative characteristic thermistors and several types of constant resistance elements were combined,
Alternatively, the thermistor constant B must be used with restrictions, which poses problems in practicality. Therefore, the main purpose of the present invention is to provide a laminated thermistor with stable resistance-temperature characteristics even at low temperatures. This is true.
この発明は、簡単にいえば、それぞれのサーミスタ定数
Ｂが５０≦Ｂ＜６０００の範囲で示されかつ抵抗温度特
性の異なる抵抗体層を２種類以−１−積層してなり、合
成した抵抗温度特性を、温度Ｔの範囲５０℃≦Ｔ≦７０
℃で２０００≦Ｂ≦５０００でありかつ一層 Ｏ’Ｃ≦
Ｔ〈５０℃の範囲で５０≦Ｂ≦２５００に設定した、積
層サーミスタである。To put it simply, this invention consists of laminating two or more types of resistor layers each having a thermistor constant B in the range of 50≦B<6000 and having different resistance-temperature characteristics. Characteristics, temperature T range 50℃≦T≦70
℃ 2000≦B≦5000 and even more O'C≦
This is a laminated thermistor in which T is set to 50≦B≦2500 in the range of 50°C.
〔作用］
たとえばサーミスタ定数Ｂの大きい抵抗体層とサーミス
タ定数Ｂの小さい抵抗体層とを積層すると、合成抵抗温
度特性が必要な温度範囲でほぼ直線となる。[Function] For example, when a resistor layer with a large thermistor constant B and a resistor layer with a small thermistor constant B are laminated, the combined resistance-temperature characteristic becomes almost a straight line in the required temperature range.
この発明によれば、抵抗温度特性がほぼ直線になり安定
するので、とりわけ低温側における抵抗温度特性が安定
化され、１つの積層サーミスタだけで広い温度範囲にお
いて安定して突入電流を防止でき、従来のような固定抵
抗との組み合わせ等の使用」−の煩雑さが解消する。According to this invention, the resistance-temperature characteristic is almost linear and stable, so the resistance-temperature characteristic is stabilized, especially on the low temperature side, and inrush current can be stably prevented over a wide temperature range with just one laminated thermistor. This eliminates the complexity of using a combination with a fixed resistor such as
この発明の上述の目的、その他の目的、特徴および利点
は、図面を参照して行う以下の実施例の詳細な説明から
一層明らかとなろう。The above objects, other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
Ｃ実施例〕
第１図を参照して、この実施例の突入電流防止用の積層
サーミスタ１０はサーミスタチップ１２を含む。サーミ
スタチップ１２は、サーミスタ定数Ｂの小さい抵抗体層
１４およびその上に積層されたサーミスタ定数Ｂの大き
い抵抗体層１６を含む。Embodiment C] Referring to FIG. 1, a multilayer thermistor 10 for preventing rush current according to this embodiment includes a thermistor chip 12. The thermistor chip 12 includes a resistor layer 14 with a small thermistor constant B and a resistor layer 16 with a large thermistor constant B laminated thereon.
低サーミスタ定数の抵抗体層１４は、その−力士面上に
内部電極１８が形成された複数のサーミスタ基板２０を
含み、第１図図示のように内部電極１８が互い違いにな
るように、サーミスタ基板２０を積層することによって
形成される。The low thermistor constant resistor layer 14 includes a plurality of thermistor substrates 20 having internal electrodes 18 formed on their - sumo surfaces, and the thermistor substrates 20 are arranged such that the internal electrodes 18 are alternated as shown in FIG. It is formed by laminating 20 layers.
同じように、低サーミスタ定数の抵抗体層１４の上に積
層された高サーミスタ定数の抵抗体層１６は、その−力
士面上に内部電極１８が形成された複数のサーミスタ基
板２２を含む。そして、内部電極１８が互い違いに配置
されるように、サーミスタ基板２２を積層して、抵抗体
層１Ｇが形成される。Similarly, the high thermistor constant resistor layer 16 laminated on the low thermistor constant resistor layer 14 includes a plurality of thermistor substrates 22 on which internal electrodes 18 are formed on the - sumo wrestler surface. Then, the thermistor substrates 22 are stacked so that the internal electrodes 18 are arranged alternately to form the resistor layer 1G.
なお、抵抗体層１４および１６のサーミスタ定数Ｂはと
もに５０≦Ｂ＜６０００の範囲に設定される。Note that the thermistor constants B of the resistor layers 14 and 16 are both set in the range of 50≦B<6000.
このようにして得られるサーミスタチップ１２には、内
部電極１８が露出する２側面から上下主面の一部にかけ
て、それぞれ断面コ字状の外部電極２４が形成される。In the thermistor chip 12 obtained in this manner, external electrodes 24 each having a U-shaped cross section are formed from the two side surfaces where the internal electrodes 18 are exposed to part of the upper and lower main surfaces.
この外部電極２４にまって抵抗体層１４および２０が並
列接続される。Resistor layers 14 and 20 are connected in parallel across this external electrode 24.
このように、サーミスタ定数Ｂの小さい抵抗体層］４と
サーミスタ定数の大きい抵抗体層１６とを並列接続する
ことによって、その合成抵抗温度係数は一定の温度範囲
でほぼ直線となる。したがって、特に低温側での抵抗温
度特性が安定し、突入電流防止用として有用な積層サー
ミスタが得られる。In this way, by connecting the resistor layer 4 with a small thermistor constant B and the resistor layer 16 with a large thermistor constant in parallel, the combined temperature coefficient of resistance becomes approximately a straight line within a certain temperature range. Therefore, a multilayer thermistor with stable resistance-temperature characteristics particularly on the low temperature side and useful for preventing rush current can be obtained.
実ル１
まず、Ｃａ ／ Ｍ ｎ系酸化物からなる低サーミスタ
定数の抵抗材料に、Ｃａ Ｃ０３、Ｍ ｎ ＣＣＬ＋を
所定量秤量混合した後、９００℃で２時間仮焼して、そ
の仮焼物にバインダ、可塑剤および純水を加えて十分に
混練してスラリを作成した。ドクタブレード法を用いて
スラリをテープキャスティングし、厚さ０．３ｍｍの低
ザーミスタ定数のグリーンテープを作成した。ごのグリ
ーンテープの一方主面上に所定間隔毎に長方形の所定面
積を有する内部電極ペースト層１８′を塗布した。なお
、この内部電極ペースＩ・とじては、ｐｔペーストを用
いた。そして、その一方端面に内部電極ペースト層１８
′が露出しかつそれぞれ同じ大きさとなるように、グリ
ーンテープを切断して、複数のグリーンテープユニット
２０′を作成した。そして、グリーンテープユニット２
０′を、第２図図示のように内部電極ペースト層１８′
が互い違いになるよ・うに所定枚数積層した。Example 1: First, a predetermined amount of Ca C03 and M n CCL+ was mixed into a resistance material with a low thermistor constant made of Ca/M n-based oxide, and then calcined at 900°C for 2 hours to form the calcined product. A binder, plasticizer, and pure water were added and sufficiently kneaded to create a slurry. The slurry was tape cast using a doctor blade method to produce a 0.3 mm thick green tape with a low thermistor constant. An internal electrode paste layer 18' having a rectangular predetermined area was applied at predetermined intervals on one main surface of each green tape. Note that PT paste was used for this internal electrode paste I. Then, an internal electrode paste layer 18 is formed on one end surface of the internal electrode paste layer 18.
A plurality of green tape units 20' were produced by cutting the green tape so that the green tape units 20' were exposed and each had the same size. And green tape unit 2
0' to the internal electrode paste layer 18' as shown in FIG.
A predetermined number of sheets were laminated so that the sheets were alternated.
ついで、Ｍｎ−Ｎｉ系酸化物からなる高サーミスタ定数
の抵抗材料に、ＭｎＣ０ａ 、Ｎ１ＣＯａ、Ｃｏｃｏ：
＋およびＡｌＣＯ３を所定量秤量混合し、先と同様の方
法によって、厚さ０．０３ｍｍのグリーンテープを作成
し、その−力士面」―に所定間隔で所定面積の内部電極
ペースト層１８′を形成した。そして、その一方端面に
内部電極ペースト層１８′が露出しかつそれぞれ同じ大
きさとなるように、グリーンテープを切断して、複数の
グリーンテーブユニツｌ−２２’を作成した。そして、
グリーンテープユニット２２′を、第２図図示のように
内部電極ペースト層１８′が互い違いになるように所定
枚数積層した。Next, MnC0a, N1COa, Coco:
Weigh and mix predetermined amounts of + and AlCO3, create a green tape with a thickness of 0.03 mm in the same manner as above, and form internal electrode paste layers 18' of a predetermined area at predetermined intervals on the - sumo wrestler surface. did. Then, the green tape was cut so that the internal electrode paste layer 18' was exposed on one end face and each had the same size to create a plurality of green tape units 1-22'. and,
A predetermined number of green tape units 22' were laminated so that the internal electrode paste layers 18' were alternated as shown in FIG.
このようにして準備した抵抗体グリーンユニットを高サ
ーミスタ定数のものが低ザーミスク定数のものの」二に
なるように積層して、熱圧着して、グリーンユニット１
２′を得た。このグリーンテープｌ−１２′を１２００
℃で２時間一体焼成し、第１図図示のザーミスタチップ
１２を得た。The resistor green units prepared in this way are stacked so that the one with a high thermistor constant is twice that of the one with a low thermistor constant, and the green unit 1 is bonded with heat.
I got 2'. This green tape l-12' is 1200
The product was integrally fired at .degree. C. for 2 hours to obtain the thermistor chip 12 shown in FIG.
その後、ザーミスタチップ１２の両端面にＡｇペースト
を５００℃で焼き付けることによって外部電極２４を形
成した。Thereafter, external electrodes 24 were formed on both end surfaces of the thermistor chip 12 by baking Ag paste at 500°C.
なお、−船釣に、積層ザーミスタ１０の抵抗温度特性を
平滑化するには、抵抗体層１４および１６の抵抗値を、
平滑化を行う温度範囲付近で同程度の大きさにする必要
がある。しかし、この実施例の抵抗体層１４および１６
としてそれぞれ使用されたＣ ａ ／ Ｍ ｎ系酸化物
とＭｎ−Ｎｉ−Ｃｏ系酸化物との抵抗値は、常温付近で
２桁程度の差がある。したがって、この差を解消するた
めに、抵抗体層１４の各サーミスタ基板２０（第１図）
の厚さを抵抗体層１６の各サーミスタ基板２２の厚さよ
り１０倍以上厚くしている。In addition, in order to smooth the resistance-temperature characteristics of the laminated thermistor 10 for boat fishing, the resistance values of the resistor layers 14 and 16 are
It is necessary to have a similar size around the temperature range in which smoothing is performed. However, in this embodiment, resistor layers 14 and 16
The resistance values of the Ca/Mn-based oxides and the Mn-Ni-Co-based oxides, which were respectively used as oxides, have a difference of about two orders of magnitude at room temperature. Therefore, in order to eliminate this difference, each thermistor substrate 20 (FIG. 1) of the resistor layer 14 is
The thickness of the resistor layer 16 is made ten times or more thicker than the thickness of each thermistor substrate 22 of the resistor layer 16.
また、サーミスタ定数Ｂ＝６０００以上の材料は比抵抗
が１００にΩ・ｃｍ以上となり、規格寸法の自由度が制
限される。このため、サーミスタ定数Ｂとしては、０≦
Ｂ＜６０００の範囲で利用するのが望ましい。Further, a material with a thermistor constant B=6000 or more has a specific resistance of 100 Ω·cm or more, which limits the degree of freedom in standard dimensions. Therefore, the thermistor constant B is 0≦
It is desirable to use it in the range of B<6000.
このようにして得られた積層サーミスタ１０の抵抗温度
特性が第３Ａ図、第３Ｂ［Ｄおよび第３Ｃ図にそれぞれ
示される。The resistance-temperature characteristics of the multilayer thermistor 10 thus obtained are shown in FIGS. 3A, 3B[D, and 3C, respectively.
実験では、低ザーミスタ定数の抵抗体層１４のサーミス
タ定数Ｂを３００にと−・定にし、高サーミスタ定数の
抵抗体層１６のサーミスタ定数Ｂをそれぞれ６０００Ｋ
（第３Ａ図）、５０００Ｋ（第３Ｂ図）および４００
０Ｋ（第３Ｃ図）に設定した。In the experiment, the thermistor constant B of the resistor layer 14 with a low thermistor constant was set to 300, and the thermistor constant B of the resistor layer 16 with a high thermistor constant was set to 6000K.
(Figure 3A), 5000K (Figure 3B) and 400K
It was set to 0K (Figure 3C).
第３Ａ図〜第３Ｃ図のいずれの例においても、積層ザー
ミスタ１０の合成抵抗温度特性は、線へで示すように、
測定温度範囲すなわち−】０℃≦］゛≦７０℃において
ほぼ直線を呈する。因みに、線Ｂばザーミスタチンブを
高サーミスタ定数の抵抗体層１６だけで形成した積層ザ
ーミスタの抵抗温度特性を示し、線Ｃはザーミスタチッ
プを低ザーミスク定数の抵抗体層１４だけで形成した積
層サーミスタの抵抗温度特性を示す。In any of the examples shown in FIGS. 3A to 3C, the composite resistance temperature characteristic of the laminated thermistor 10 is as shown by the line
It exhibits a substantially straight line in the measurement temperature range, that is, -]0°C≦]゛≦70°C. Incidentally, line B shows the resistance-temperature characteristics of a multilayer thermistor in which the thermistor chip is formed only with the resistor layer 16 with a high thermistor constant, and line C shows the resistance temperature characteristics of a multilayer thermistor in which the thermistor chip is formed only with the resistor layer 14 with a low thermistor constant. Shows resistance temperature characteristics.
また、次表に、各サーミスタ定数Ｂを有する抵抗体層を
組み合わせたときの特性を示す。Further, the following table shows the characteristics when resistor layers having each thermistor constant B are combined.
この表および先の第３Ａ図〜第３Ｃ図からよく分かるよ
うに、この発明に従えば、抵抗温度係数特に低温側での
抵抗温度係数が安定している。As can be clearly seen from this table and FIGS. 3A to 3C above, according to the present invention, the temperature coefficient of resistance, especially on the low temperature side, is stable.
（以下余白）
この表において、Ｒ−、ｏ／Ｒ２５ば一１０’Ｃの抵抗
値と２５℃の抵抗値との変化割合を示し、Ｂ ６０−１
゜０は６０“Ｃ〜１００ ’Ｃでのザーミスタ定数の合
成値を示す。(Margins below) In this table, the change ratio between the resistance value at 10'C and the resistance value at 25°C is shown for R-, o/R25, and B 60-1
0 indicates the composite value of the thermistor constant at 60"C to 100'C.
なお、上表には、低温側での抵抗温度特性を比較するた
めに、サーミスタ定数３３９０単体のＲ−ＩＱ／Ｒ２，
のイ直も掲載した。In addition, in the above table, in order to compare the resistance temperature characteristics on the low temperature side, R-IQ/R2 of a single thermistor constant of 3390,
I also posted the i-nao.
第１図はこの発明の一実施例を示す断面図である。
第２図は第１図実施例の製造工程を示す分解斜視図であ
る。
第３Ａ図〜第３Ｃ図は、それぞれ、実施例の積層サーミ
スタの抵抗温度特性を、比較例とともに示すグラフであ
る。
図において、１０は積層サーミスタ、１４．１６は抵抗
体層、１８は内部電極、２０．２２はサーミスタ基板、
２４ば外部電極を示す。
特許出願人 株式会社 村田製作所
代理人 弁理士 山 １） 義 人
−１１＝
第１図
］０
第２図
第３Ａ図
１＾ 凸 １凸 つ凸 つ凸 ｌ凸 Ｑｎ
らｎ ７ｎ第３Ｃ図
温 度 じＣ）
第３Ｂ図
温 度 （０Ｃ）FIG. 1 is a sectional view showing an embodiment of the present invention. FIG. 2 is an exploded perspective view showing the manufacturing process of the embodiment shown in FIG. FIGS. 3A to 3C are graphs showing the resistance-temperature characteristics of the laminated thermistor of the example, together with a comparative example. In the figure, 10 is a laminated thermistor, 14.16 is a resistor layer, 18 is an internal electrode, 20.22 is a thermistor substrate,
24 indicates an external electrode. Patent Applicant Murata Manufacturing Co., Ltd. Agent Patent Attorney Yama 1) Yoshihito-11 = Figure 1] 0 Figure 2 Figure 3A 1^ Convex 1 convex 1 convex 1 convex l convex Qn
7n Figure 3C Temperature DiC) Figure 3B Temperature (0C)
Claims (1)
範囲で示されかつ抵抗温度特性の異なる抵抗体層を２種
類以上積層してなり、合成抵抗温度特性を、温度Ｔの範
囲５０℃≦Ｔ≦７０℃で２０００≦Ｂ≦５０００であり
かつ−１０℃≦Ｔ＜５０℃の範囲で５０≦Ｂ≦２５００
に設定した、積層サーミスタ。Two or more types of resistor layers each having a thermistor constant B in the range of 50≦B<6000 and having different resistance-temperature characteristics are laminated, and the combined resistance-temperature characteristic is within the range of temperature T 50°C≦T≦70. 2000≦B≦5000 at ℃ and 50≦B≦2500 in the range of -10℃≦T<50℃
A multilayer thermistor set to
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2339043A JP3047466B2 (en) | 1990-11-30 | 1990-11-30 | Multi-layer thermistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2339043A JP3047466B2 (en) | 1990-11-30 | 1990-11-30 | Multi-layer thermistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04206901A true JPH04206901A (en) | 1992-07-28 |
| JP3047466B2 JP3047466B2 (en) | 2000-05-29 |
Family
ID=18323728
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2339043A Expired - Lifetime JP3047466B2 (en) | 1990-11-30 | 1990-11-30 | Multi-layer thermistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3047466B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5907271A (en) * | 1995-12-13 | 1999-05-25 | Murata Manufacturing Co., Ltd. | Positive characteristic thermistor device |
| JP2008205388A (en) * | 2007-02-22 | 2008-09-04 | Tdk Corp | Thermistor element |
-
1990
- 1990-11-30 JP JP2339043A patent/JP3047466B2/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5907271A (en) * | 1995-12-13 | 1999-05-25 | Murata Manufacturing Co., Ltd. | Positive characteristic thermistor device |
| JP2008205388A (en) * | 2007-02-22 | 2008-09-04 | Tdk Corp | Thermistor element |
| JP4655053B2 (en) * | 2007-02-22 | 2011-03-23 | Ｔｄｋ株式会社 | Thermistor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3047466B2 (en) | 2000-05-29 |
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