JP3206601B2 - Multi-layer thermistor - Google Patents
Multi-layer thermistorInfo
- Publication number
- JP3206601B2 JP3206601B2 JP27881990A JP27881990A JP3206601B2 JP 3206601 B2 JP3206601 B2 JP 3206601B2 JP 27881990 A JP27881990 A JP 27881990A JP 27881990 A JP27881990 A JP 27881990A JP 3206601 B2 JP3206601 B2 JP 3206601B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor layer
- thermistor
- resistance
- temperature
- constant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Thermistors And Varistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は積層サーミスタに関し、特にたとえば突入
電流防止用積層サーミスタに関する。Description: TECHNICAL FIELD The present invention relates to a laminated thermistor, and more particularly to, for example, a laminated thermistor for preventing inrush current.
〔従来技術〕 スイッチング電源では、交流入力を直接ダイオードに
よって整流し、それを電解コンデンサで平滑化する。そ
のため、スイッチング時に電解コンデンサにサージ電流
が流れ、これを突入電流という。この突入電流はたとえ
ば数十アンペアという大電流であり、スイッチ接点やダ
イオードの劣化を早めてしまう。この突入電流を抑制す
る方法の１つとして、従来より、サーミスタの動特性を
利用するものがある。すなわち、サーミスタは常温で数
Ω〜数十Ωの抵抗値を有し、スイッチがオンされたとき
この抵抗値によって突入電流を抑制する。また、サーミ
スタはスイッチング電源の安定状態では自己発熱し、そ
の抵抗値は常温の1/10程度になるので、電力ロスなどの
支障は生じない。[Prior Art] In a switching power supply, an AC input is directly rectified by a diode and is smoothed by an electrolytic capacitor. Therefore, a surge current flows through the electrolytic capacitor during switching, and this is called an inrush current. This inrush current is a large current of, for example, several tens of amperes, and accelerates deterioration of the switch contacts and the diode. As one of the methods for suppressing the inrush current, there is a method that utilizes the dynamic characteristics of a thermistor. That is, the thermistor has a resistance of several Ω to several tens of Ω at room temperature, and suppresses the rush current by this resistance when the switch is turned on. Further, the thermistor self-heats when the switching power supply is in a stable state, and its resistance value becomes about 1/10 of normal temperature, so that trouble such as power loss does not occur.
このような突入電流防止用サーミスタとして、常温付
近で使用できるものとしては、Mn−Ni系,Mn−Ni−Co系
またはMn−Ni−Co系などの酸化物があり、また、800℃
前後で使用できるものとしてはZr−Ｙ系などの酸化物が
ある。これらのサーミスタは温度係数が大きい上、形状
や抵抗値の自由度が大きく、また安価である等の利点を
有している。As such a thermistor for preventing inrush current, oxides such as Mn-Ni-based, Mn-Ni-Co-based or Mn-Ni-Co-based can be used at around room temperature, and 800 ° C.
As a material which can be used before and after, there is an oxide such as a Zr-Y type. These thermistors have advantages such as a large temperature coefficient, a large degree of freedom in shape and resistance value, and a low cost.
このような半導体特性を利用するサーミスタの抵抗温
度特性は以下の式で表される。The resistance-temperature characteristic of a thermistor utilizing such semiconductor characteristics is expressed by the following equation.
R1＝R2exp｛（1/T1−1/T2）Ｂ｝ T1,T2 ：温度〔ｋ〕 R1,R2 ：温度T1,T2における抵抗値 Ｂ〔ｋ〕：サーミスタ定数 この式からよく分かるように、従来のサーミスタで
は、抵抗温度特性が直線的でないため、特に低温側での
抵抗値が急激に増大してしまう。したがって、従来のサ
ーミスタを突入電流防止用として用いるには、低温側で
の抵抗値を低く安定化させる必要がある。そのため、従
来では、数種類の負特性サーミスタと数種類の固定抵抗
体とを組み合わせたり、または、サーミスタ定数Ｂに制
約を設けて用いなければならない等、実用性に問題があ
った。この問題を解決するために、サーミスタ定数の異
なる２種以上のサーミスタ材料を組み合わせ、シート積
層で同時焼成して得られる突入電流防止用サーミスタが
提案されている。R 1 = R 2 exp {(1 / T 1 -1 / T 2 ) B} T 1 , T 2 : temperature [k] R 1 , R 2 : resistance value at temperature T 1 , T 2 B [k]: Thermistor constant As can be clearly understood from this equation, in the conventional thermistor, the resistance-temperature characteristic is not linear, so that the resistance value particularly on the low temperature side sharply increases. Therefore, in order to use a conventional thermistor for preventing inrush current, it is necessary to stabilize the resistance at a low temperature. Therefore, conventionally, there has been a problem in practicality, for example, it is necessary to combine several kinds of negative characteristic thermistors and several kinds of fixed resistors, or to restrict the thermistor constant B before use. In order to solve this problem, there has been proposed a rush current preventing thermistor obtained by combining two or more types of thermistor materials having different thermistor constants and simultaneously firing the laminated sheets.
しかし、上述のように異なる材料を組み合わせる方法
では、それぞれの材料系の比抵抗値が大きく異なるの
で、チップサイズと目標抵抗値とを合致させる設計に限
界があった。However, in the method of combining different materials as described above, since the specific resistance values of the respective material systems are greatly different, there is a limit in designing to match the chip size with the target resistance value.
それゆえに、この発明の主たる目的は、低温側におい
ても抵抗温度特性が安定であり、しかもチップサイズお
よび抵抗値の設計自由度を大きくできる、積層サーミス
タを提供することである。SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a laminated thermistor that has stable resistance-temperature characteristics even at a low temperature side and can increase the degree of freedom in designing a chip size and a resistance value.
この発明は、サーミスタ定数が相対的に大きく負の抵
抗温度特性を有する抵抗体層と、抵抗体層内に埋設され
るとともに抵抗体層の端面に交互に引き出された内部電
極と、内部電極と導電的に接続されるとともに抵抗体層
の端面に形成された外部電極と、抵抗体層の主面上であ
って外部電極間に跨って配置され、サーミスタ定数が相
対的に小さく負の抵抗温度特性を有する膜状抵抗体層と
からなることを特徴とする、積層サーミスタである。The present invention provides a resistor layer having a relatively large thermistor constant and a negative resistance temperature characteristic, an internal electrode embedded in the resistor layer and alternately drawn out to an end face of the resistor layer, An external electrode which is conductively connected and is formed on the end face of the resistor layer, and which is disposed on the main surface of the resistor layer and straddles between the external electrodes, and has a relatively small thermistor constant and a negative resistance temperature; A laminated thermistor comprising a film-shaped resistor layer having characteristics.
サーミスタ定数の相対的に大きい抵抗体層上にサーミ
スタ定数の相対的に小さい抵抗体層をたとえば厚膜法に
よって形成し、高サーミスタ定数の抵抗体層と並列接続
する。両抵抗体層の抵抗温度特性が合成され、その合成
抵抗温度特性は必要な温度範囲でほぼ直線にすることが
できる。A resistor layer having a relatively small thermistor constant is formed on the resistor layer having a relatively large thermistor constant by, for example, a thick film method, and is connected in parallel with a resistor layer having a high thermistor constant. The resistance-temperature characteristics of the two resistor layers are combined, and the combined resistance-temperature characteristics can be made substantially linear in a required temperature range.
この発明によれば、サーミスタ定数の相対的に小さい
抵抗層をたとえば厚膜法によって膜状に形成するので、
特に低温側における抵抗温度特性が安定化され、したが
って、比較的簡単に、目標チップサイズと目標抵抗値と
を合致させることができ、設計の自由度が大幅に改善さ
れる。したがって、従来のような固定抵抗との組み合わ
せ等の使用上の煩雑さが解消されるだけでなく、より広
範囲にわたって抵抗値の調整が可能となる。According to the present invention, since the resistance layer having a relatively small thermistor constant is formed in a film shape by, for example, a thick film method,
In particular, the resistance-temperature characteristics on the low-temperature side are stabilized, so that the target chip size and the target resistance value can be relatively easily matched, and the degree of freedom in design is greatly improved. Therefore, not only is the complicated use of a conventional combination with a fixed resistor or the like eliminated, but also the resistance value can be adjusted over a wider range.
この発明の上述の目的，その他の目的，特徴および利
点は、図面を参照して行う以下の実施例の詳細な説明か
ら一層明らかとなろう。The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of embodiments with reference to the drawings.
第１図および第２図を参照して、この実施例の突入電
流防止用の積層サーミスタ10は、概略、サーミスタ定数
の相対的に大きい抵抗体層12とサーミスタ定数の相対的
に小さい膜状抵抗体層20とを含む。抵抗体層12は、内部
電極14の一方端面をサーミスタ基板16の一方端面と面一
になるように配置した後、特に第２図からよく分かるよ
うに、内部電極14が互い違いになるようにサーミスタ基
板16を所定枚数積層することによって形成される。した
がって、内部電極14は抵抗体層12内に埋設されるととも
に、抵抗体層12の両端面に交互に引き出されることにな
る。Referring to FIG. 1 and FIG. 2, a laminated thermistor 10 for preventing inrush current according to this embodiment generally includes a resistor layer 12 having a relatively large thermistor constant and a film-like resistor having a relatively small thermistor constant. And a body layer 20. After arranging the resistor layer 12 such that one end face of the internal electrode 14 is flush with one end face of the thermistor substrate 16, the thermistor is so arranged that the internal electrodes 14 are alternately arranged, as can be clearly understood from FIG. It is formed by laminating a predetermined number of substrates 16. Therefore, the internal electrodes 14 are embedded in the resistor layer 12 and are alternately drawn to both end surfaces of the resistor layer 12.
このようにして得られる抵抗体層12には、内部電極14
が交互に露出する両端面から上下主面の一部にかけて、
それぞれ内部電極14と導電的に接続される断面コ字状の
外部電極18が形成される。The resistor layer 12 thus obtained has an internal electrode 14
From both end faces that are alternately exposed to a part of the upper and lower main faces,
External electrodes 18 each having a U-shaped cross section that are conductively connected to the internal electrodes 14 are formed.
そして、抵抗体層12の一方主面上に膜状抵抗体層20が
たとえば印刷法によって形成される。この膜状抵抗体層
20は２つの外部電極18に跨がって配置され、したがっ
て、抵抗体層12と膜状抵抗体層20とは並列接続される。Then, a film-shaped resistor layer 20 is formed on one main surface of the resistor layer 12, for example, by a printing method. This film resistor layer
The reference numeral 20 extends over the two external electrodes 18, so that the resistor layer 12 and the film-shaped resistor layer 20 are connected in parallel.
このように、サーミスタ定数の大きい抵抗体層12とサ
ーミスタ定数の小さい膜状抵抗体層20とを並列接続し、
それぞれの抵抗−温度特性を調整することによって、そ
の合成抵抗温度係数は一定の温度範囲でほぼ直線とな
る。したがって、所望の低温領域にこの温度範囲がくる
ように調整することによって、低温側での抵抗温度特性
が安定する。Thus, the resistor layer 12 having a large thermistor constant and the film-shaped resistor layer 20 having a small thermistor constant are connected in parallel,
By adjusting the respective resistance-temperature characteristics, the combined resistance temperature coefficient becomes substantially linear in a certain temperature range. Therefore, by adjusting the temperature range so as to fall within a desired low-temperature region, the resistance-temperature characteristics on the low-temperature side are stabilized.
すなわち、膜状抵抗体層20の抵抗値Ｒは、Rsをシート
抵抗値（Ω）、ｌを長さ、そしてｗを幅とすると、以下
の式によって求められる。That is, the resistance value R of the film-like resistor layer 20, a R s sheet resistance (Omega), l the length, and when the width w, is determined by the following equation.
Ｒ＝RS×Ｎ ここで、厚みｔを一定にすれば、RS＝ρ/t＝一定とな
り、また、Ｎ＝l/wで与えられる。Where R = R S × N, if the thickness t constant, becomes R S = ρ / t = constant and is given by N = l / w.
したがって、膜状抵抗体層20の抵抗値Ｒは、形状比
（l/w）によって決定されることがわかる。すなわち、
外部電極18と膜状抵抗体層20の形状および大きさ等を調
整することによって、抵抗値Ｒを広範囲に選択すること
が可能となる。Therefore, it is understood that the resistance value R of the film-shaped resistor layer 20 is determined by the shape ratio (l / w). That is,
By adjusting the shape, size, and the like of the external electrode 18 and the film-shaped resistor layer 20, the resistance value R can be selected over a wide range.
実験例 まず、Mn−Ni系酸化物からなる高サーミスタ定数の抵
抗材料に、MnCO3,NiCO3,CoCO3およびAl2O3を所定量秤量
混合した後、900℃で２時間仮焼して、その仮焼物にバ
インダ，可塑剤および純水を加えて十分に混練してスラ
リを作成した。ドクタブレード法を用いてスラリをテー
プキャスティングし、厚さ0.3mmの高サーミスタ定数の
グリーンテープを作成した。このグリーンテープの一方
主面上に所定間隔毎に長方形の所定面積を有する内部電
極ペースト層14′を塗布した。なお、この内部電極ペー
ストとしては、Ptペーストを用いた。そして、その一方
端面に内部電極ペースト層14′が露出しかつそれぞれ同
じ大きさとなるように、グリーンテープを切断して、複
数のグリーンテープユニット16′を作成した。そして、
第３図図示のように、内部電極ペースト層14′が互い違
いになるようにグリーンテープユニット16′を所定枚数
積層し、熱圧着してグリーンユニット12′を得た。この
グリーンユニット12′を1300℃で２時間一体焼成し、第
１図および第２図図示の抵抗体層12を得た。Experimental Example First, a predetermined amount of MnCO 3 , NiCO 3 , CoCO 3 and Al 2 O 3 was weighed and mixed with a high thermistor constant resistance material composed of a Mn-Ni-based oxide, and then calcined at 900 ° C. for 2 hours. Then, a binder, a plasticizer, and pure water were added to the calcined product and sufficiently kneaded to prepare a slurry. The slurry was tape-cast using a doctor blade method to produce a green tape having a high thermistor constant of 0.3 mm in thickness. On one main surface of the green tape, an internal electrode paste layer 14 'having a rectangular predetermined area was applied at predetermined intervals. Note that a Pt paste was used as the internal electrode paste. Then, the green tape was cut so that the internal electrode paste layer 14 'was exposed on one end surface and had the same size, thereby producing a plurality of green tape units 16'. And
As shown in FIG. 3, a predetermined number of green tape units 16 'were laminated so that the internal electrode paste layers 14' were alternately formed, and thermocompression bonded to obtain a green unit 12 '. The green unit 12 ′ was integrally fired at 1300 ° C. for 2 hours to obtain the resistor layer 12 shown in FIGS. 1 and 2.
その後、抵抗体層12の両端面から上下主面の一部にか
けてAg−Pdペーストを焼き付けることによって外部電極
18を形成した。この外部電極18は所望の抵抗値に基づい
てその寸法が設定される。Thereafter, the external electrode is baked by baking Ag-Pd paste from both end surfaces of the resistor layer 12 to a part of the upper and lower main surfaces.
18 formed. The dimensions of the external electrode 18 are set based on a desired resistance value.
そして、抵抗体層12の一方主面上に２つの外部電極18
に跨がるようにして低サーミスタ定数の膜状抵抗体層20
を形成した。膜状抵抗体層20の材料としては、温度変化
率の小さいたとえばCo−Li系酸化物とRuO2ガラスビヒク
ルとを所定量混合し、３本ローラで混練して抵抗ペース
トとした。この抵抗ペーストをスクリーン印刷機によっ
て所望の形状比（l/w）に印刷し、これを乾燥した後850
℃で２時間焼成し、積層サーミスタ10を得た。このよう
にして得られた積層サーミスタ10の抵抗温度特性を次表
に示す。The two external electrodes 18 are provided on one main surface of the resistor layer 12.
Film resistor layer 20 having a low thermistor constant
Was formed. As a material of the film-shaped resistor layer 20, a predetermined amount of, for example, a Co—Li-based oxide having a small rate of change in temperature and a RuO 2 glass vehicle were mixed and kneaded with three rollers to form a resistance paste. This resistance paste is printed to a desired shape ratio (l / w) by a screen printer, and after drying it,
Firing at 2 ° C. for 2 hours to obtain a laminated thermistor 10. The following table shows the resistance temperature characteristics of the multilayer thermistor 10 thus obtained.
この表において、R-10/25は−10℃の抵抗値と25℃の
抵抗値との変化割合を示し、B60〜100は60℃〜100℃で
のサーミスタ定数値の合成値を示す。 In this table, R -10 / 25 indicates the rate of change of the resistance value and the resistance value of 25 ° C. of -10 ℃, B 60 ~ 100 show the synthesis of the thermistor constant value at 60 ° C. to 100 ° C..
この表からサーミスタ定数が3390の単一材料からなる
もののR-10/25の値と比較しても、低温側での抵抗温度
係数が安定していることがわかる。From this table, it can be seen that the temperature coefficient of resistance on the low temperature side is stable even when compared with the value of R -10 / 25 even though the thermistor constant is made of a single material having a 3390 thermistor constant.
【図面の簡単な説明】 第１図はこの発明の一実施例を示す斜視図である。 第２図はこの実施例を示す断面図である。 第３図はこの実施例のグリーンユニットの分解斜視図で
ある。 図において、10は積層サーミスタ、12は抵抗体層、14は
内部電極、16はサーミスタ基板、18は外部電極、20は膜
状抵抗体層を示す。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing an embodiment of the present invention. FIG. 2 is a sectional view showing this embodiment. FIG. 3 is an exploded perspective view of the green unit of this embodiment. In the figure, 10 is a laminated thermistor, 12 is a resistor layer, 14 is an internal electrode, 16 is a thermistor substrate, 18 is an external electrode, and 20 is a film resistor layer.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平１−295403（ＪＰ，Ａ) 特開 昭61−121302（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-295403 (JP, A) JP-A-61-121302 (JP, A)
Claims (1)
温度特性を有する抵抗体層と、前記抵抗体層内に埋設さ
れるとともに前記抵抗体層の端面に交互に引き出された
内部電極と、前記内部電極と導電的に接続されるととも
に前記抵抗体層の端面に形成された外部電極と、前記抵
抗体層の主面上であって前記外部電極間に跨って配置さ
れ、サーミスタ定数が相対的に小さく負の抵抗温度特性
を有する膜状抵抗体層とからなることを特徴とする、積
層サーミスタ。A resistor layer having a relatively large thermistor constant and having a negative resistance temperature characteristic; an internal electrode embedded in the resistor layer and alternately drawn to an end face of the resistor layer; An external electrode, which is conductively connected to the internal electrode and is formed on an end face of the resistor layer, is disposed on the main surface of the resistor layer and between the external electrodes, and has a relative thermistor constant. A laminated thermistor comprising a film-like resistor layer having a relatively small negative resistance-temperature characteristic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27881990A JP3206601B2 (en) | 1990-10-17 | 1990-10-17 | Multi-layer thermistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27881990A JP3206601B2 (en) | 1990-10-17 | 1990-10-17 | Multi-layer thermistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04152601A JPH04152601A (en) | 1992-05-26 |
| JP3206601B2 true JP3206601B2 (en) | 2001-09-10 |
Family
ID=17602594
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27881990A Expired - Lifetime JP3206601B2 (en) | 1990-10-17 | 1990-10-17 | Multi-layer thermistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3206601B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923930B (en) * | 2009-06-12 | 2011-08-24 | 深圳市安培盛科技有限公司 | Intelligent PTC (Positive Temperature Coefficient) overvoltage and overcurrent protector |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002502554A (en) * | 1997-06-04 | 2002-01-22 | タイコ・エレクトロニクス・コーポレイション | Circuit protection device |
| US6362723B1 (en) * | 1999-11-18 | 2002-03-26 | Murata Manufacturing Co., Ltd. | Chip thermistors |
| JP4660922B2 (en) * | 2000-12-19 | 2011-03-30 | 株式会社村田製作所 | Thermistor and manufacturing method thereof |
| JP2002231508A (en) * | 2001-01-31 | 2002-08-16 | Oizumi Seisakusho:Kk | Linearized thermistor |
| KR100732785B1 (en) * | 2006-01-13 | 2007-06-27 | 삼화콘덴서공업주식회사 | Filter array device and method thereof |
-
1990
- 1990-10-17 JP JP27881990A patent/JP3206601B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101923930B (en) * | 2009-06-12 | 2011-08-24 | 深圳市安培盛科技有限公司 | Intelligent PTC (Positive Temperature Coefficient) overvoltage and overcurrent protector |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04152601A (en) | 1992-05-26 |
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