JP2001143904A - Composite laminate thermistor - Google Patents

Composite laminate thermistor

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Publication number
JP2001143904A
JP2001143904A JP32798399A JP32798399A JP2001143904A JP 2001143904 A JP2001143904 A JP 2001143904A JP 32798399 A JP32798399 A JP 32798399A JP 32798399 A JP32798399 A JP 32798399A JP 2001143904 A JP2001143904 A JP 2001143904A
Authority
JP
Japan
Prior art keywords
thermistor
layer
laminated
composite
thermistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP32798399A
Other languages
Japanese (ja)
Inventor
Kenji Nozoe
研治 野添
Tsutomu Kitsui
努 橘井
Tomohisa Okimoto
知久 沖本
Yoshiyuki Sato
義之 佐藤
雅幸 ▲高▼橋
Masayuki Takahashi
Etsuro Habata
悦朗 幅田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP32798399A priority Critical patent/JP2001143904A/en
Publication of JP2001143904A publication Critical patent/JP2001143904A/en
Pending legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To provide a composite laminate thermistor which can contribute to miniaturization of an electronic apparatus using a plurality of thermistors such as a temperature compensation circuit of a crystal resonator. SOLUTION: Outer electrodes 4a, 4b, 4c are formed on the exposed end surfaces of inner electrodes 3a, 3b, 3c, 3d of a laminate, in which a first thermistor layer 1, an inner electrode layer 3a, a first thermistor layer 1, an inner electrode layer 3b, a first thermistor layer 1, a second thermistor layer 2, an inner electrode layer 3c, a second thermistor layer 2, an inner electrode layer 3d, and a second thermistor layer 2, are laminated in this order. Resistivity of the first thermister layer 1 is higher than that of the second thermistor layer 2. The inner electrode layers 3b, 3c are connected with the outer electrode 4a, on the same end surface. The inner electrode 3d is connected with the outer electrode 4b, on the end surface facing the inner electrode layers 3b, 3c. The inner electrode layer 3a is connected with the outer electrode 4c, on one side surface different from both exposed end surfaces of the inner electrode layers 3b, 3c, 3d.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は水晶発振子などの温
度補償に使用する複合積層サーミスタに関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a composite laminated thermistor used for temperature compensation of a crystal oscillator or the like.

【0002】[0002]

【従来の技術】図12に示すような携帯電話に使用され
る水晶発振子の温度補償回路において、サーミスタは二
つ使用されており、一方のサーミスタ100は−40〜
25℃の低温域での温度補償に、他方のサーミスタ10
1は25〜85℃の高温域での温度補償に用いている。
2. Description of the Related Art In a temperature compensation circuit for a crystal oscillator used in a portable telephone as shown in FIG. 12, two thermistors are used.
The other thermistor 10 for temperature compensation in the low temperature range of 25 ° C.
No. 1 is used for temperature compensation in a high temperature range of 25 to 85 ° C.

【0003】これらのサーミスタ100,101は図1
3に示すようにサーミスタ層110と内部電極層111
を交互に接続した積層体の両端面に外部電極112を形
成したものであり、別々に基板に実装されていた。
[0003] These thermistors 100 and 101 are shown in FIG.
As shown in FIG. 3, the thermistor layer 110 and the internal electrode layer 111
The external electrodes 112 are formed on both end surfaces of the laminate in which the electrodes are alternately connected, and are separately mounted on the substrate.

【0004】[0004]

【発明が解決しようとする課題】この構成によると、実
装面積が大きく携帯電話等の電子機器の小型化に寄与で
きないという問題点を有していた。
According to this configuration, there is a problem that the mounting area is large and it is not possible to contribute to miniaturization of electronic equipment such as a portable telephone.

【0005】そこで本発明は、水晶発振子の温度補償回
路など複数のサーミスタを使用する電子機器の小型化に
寄与できる複合積層サーミスタを提供することを目的と
するものである。
Accordingly, an object of the present invention is to provide a composite laminated thermistor which can contribute to miniaturization of electronic equipment using a plurality of thermistors such as a temperature compensation circuit of a crystal oscillator.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明の複合積層サーミスタは、サーミスタ層と内部
電極層とを交互に積層した積層体の表面に外部電極を形
成した積層サーミスタを少なくとも二つ積層した複合積
層サーミスタにおいて、前記各積層サーミスタは比抵抗
の異なるサーミスタ層で形成したものであり、一つの複
合積層サーミスタで少なくとも二つのサーミスタ特性を
有するので、上記目的を達成することができる。
In order to achieve this object, a composite laminated thermistor according to the present invention comprises at least a laminated thermistor having external electrodes formed on the surface of a laminate in which thermistor layers and internal electrode layers are alternately laminated. In the two-layer composite thermistor, each of the laminated thermistors is formed by thermistor layers having different specific resistances, and the composite laminated thermistor has at least two thermistor characteristics with one composite laminated thermistor, so that the above object can be achieved. .

【0007】[0007]

【発明の実施の形態】本発明の請求項1に記載の発明
は、サーミスタ層と内部電極層とを交互に積層した積層
体の表面に外部電極を形成した積層サーミスタを少なく
とも二つ積層した複合積層サーミスタにおいて、前記各
積層サーミスタは比抵抗の異なるサーミスタ層で形成し
た複合積層サーミスタであり、複数のサーミスタ特性を
有するものであり、従来複数個のサーミスタを実装して
いた電子機器においてサーミスタの実装面積を小さくす
ることができる上に部品点数も減らすことができる。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is a composite in which at least two laminated thermistors having external electrodes formed on the surface of a laminate in which thermistor layers and internal electrode layers are alternately laminated. In the multilayer thermistor, each of the multilayer thermistors is a composite multilayer thermistor formed by thermistor layers having different specific resistances, has a plurality of thermistor characteristics, and is mounted in an electronic device in which a plurality of thermistors are conventionally mounted. The area can be reduced and the number of parts can be reduced.

【0008】請求項2に記載の発明は、比抵抗の高い積
層サーミスタの外部電極の一つは比抵抗の低い積層サー
ミスタの外部電極の形成面と異なる面に形成した請求項
1に記載の複合積層サーミスタであり、異なる比抵抗を
有するサーミスタを容易に一体化することができる。
According to a second aspect of the present invention, there is provided the composite according to the first aspect, wherein one of the external electrodes of the multilayer thermistor having a high specific resistance is formed on a surface different from the surface on which the external electrodes of the multilayer thermistor having a low specific resistance are formed. It is a laminated thermistor, and can easily integrate thermistors having different specific resistances.

【0009】請求項3に記載の発明は、積層サーミスタ
間に絶縁体層を設けた請求項1に記載の複合積層サーミ
スタであり、焼成時に二つの積層サーミスタ間の相互拡
散を抑制し、それぞれ所望の特性を有する積層サーミス
タとなるものである。
According to a third aspect of the present invention, there is provided the composite laminated thermistor according to the first aspect, wherein an insulating layer is provided between the laminated thermistors. Is a laminated thermistor having the following characteristics.

【0010】請求項4に記載の発明は、積層サーミスタ
間に隣接する内部電極層と同じ外部電極に接続したシー
ルド電極層を設けた請求項1に記載の複合積層サーミス
タであり、焼成時に二つの積層サーミスタ間の相互拡散
を抑制し、それぞれ所望の特性を有する積層サーミスタ
となるものである。
According to a fourth aspect of the present invention, there is provided the composite laminated thermistor according to the first aspect, wherein a shield electrode layer connected to the same external electrode as the internal electrode layer adjacent between the laminated thermistors is provided. Mutual diffusion between the laminated thermistors is suppressed, and the laminated thermistors each have desired characteristics.

【0011】以下本発明の実施の形態について図面を参
照しながら説明する。
Hereinafter, embodiments of the present invention will be described with reference to the drawings.

【0012】(実施の形態1)図1は本発明の実施の形
態1における複合積層サーミスタの斜視図、図2は図1
のA−B断面図、図3は図1のC−D断面図であり、1
は第1サーミスタ層、2は第2サーミスタ層、3a,3
b,3c,3dは内部電極層、4a,4b,4cは外部
電極である。この第1サーミスタ層1は第2サーミスタ
層2よりも比抵抗を高くした。
(First Embodiment) FIG. 1 is a perspective view of a composite laminated thermistor according to a first embodiment of the present invention, and FIG.
FIG. 3 is a sectional view taken along line AB of FIG. 1, and FIG.
Is a first thermistor layer, 2 is a second thermistor layer, 3a, 3
b, 3c and 3d are internal electrode layers, and 4a, 4b and 4c are external electrodes. The first thermistor layer 1 has a higher specific resistance than the second thermistor layer 2.

【0013】また、図4は図1に示す複合積層サーミス
タの積層体の分解斜視図であり、10は第1グリーンシ
ート、11は第2グリーンシート、12a,12b,1
2c,12dはPdを主成分とする電極ペーストであ
る。
FIG. 4 is an exploded perspective view of the laminated body of the composite laminated thermistor shown in FIG. 1, wherein 10 is a first green sheet, 11 is a second green sheet, and 12a, 12b, 1
2c and 12d are electrode pastes containing Pd as a main component.

【0014】まず第1サーミスタ層1としてMn:C
o:Fe:Al=32.5:50:10:7.5原子%
比となるような原料を用いてドクターブレード法により
厚み30μmの第1グリーンシート10を作製する。
First, as the first thermistor layer 1, Mn: C
o: Fe: Al = 32.5: 50: 10: 7.5 atomic%
The first green sheet 10 having a thickness of 30 μm is prepared by a doctor blade method using a raw material having a ratio.

【0015】また、第2サーミスタ層2としてMn:N
i:Cu=68:23:9の原子%比となるような原料
を用いて同様の第2グリーンシート11を作製する。
The second thermistor layer 2 is formed of Mn: N
A similar second green sheet 11 is manufactured using a raw material having an atomic percentage ratio of i: Cu = 68: 23: 9.

【0016】次に図4に示すように第1グリーンシート
10を複数枚積層圧着した上に内部電極層3aとなるよ
うに電極ペースト12aを印刷する。
Next, as shown in FIG. 4, a plurality of first green sheets 10 are laminated and pressed, and an electrode paste 12a is printed so as to form the internal electrode layer 3a.

【0017】次いでこの電極ペースト12a上に第1グ
リーンシート10を積層圧着し、内部電極層3bとなる
ように電極ペースト12bを印刷する。
Next, the first green sheet 10 is laminated and pressed on the electrode paste 12a, and the electrode paste 12b is printed so as to form the internal electrode layer 3b.

【0018】続いて電極ペースト12b上に第1グリー
ンシート10、第2グリーンシート11の順にそれぞれ
複数枚積層圧着する。
Subsequently, a plurality of first green sheets 10 and a plurality of second green sheets 11 are laminated and pressed on the electrode paste 12b in this order.

【0019】次に第2グリーンシート11上に内部電極
層3cとなる電極ペースト12cを印刷後第2グリーン
シート11を積層圧着する。
Next, after the electrode paste 12c to be the internal electrode layer 3c is printed on the second green sheet 11, the second green sheet 11 is laminated and pressed.

【0020】次いで第2グリーンシート11上に内部電
極層3dとなる電極ペースト12dを印刷した後、第2
グリーンシート11を複数枚積層圧着して積層体グリー
ンブロックを得る。
Next, after an electrode paste 12d to be the internal electrode layer 3d is printed on the second green sheet 11,
A plurality of green sheets 11 are laminated and pressed to obtain a laminated green block.

【0021】その後この積層体グリーンブロックを切断
して多数の積層体を得る。
Thereafter, the laminate green blocks are cut to obtain a large number of laminates.

【0022】この積層体を大気中、1150℃で焼成し
て焼結体を得た後、面取りを行い内部電極層3a,3
b,3c,3dを焼結体の端面に露出させる。
This laminate is fired at 1150 ° C. in the air to obtain a sintered body, which is then chamfered to form the internal electrode layers 3a, 3a.
b, 3c and 3d are exposed on the end face of the sintered body.

【0023】この焼結体において内部電極層3b,3
c,3dは焼結体の相対向する端面に一方の端部が露出
するとともに、第1サーミスタ層1間に形成し、第2サ
ーミスタ層2に最も近い内部電極層3bと、第2サーミ
スタ層2間に形成し、第1サーミスタ層1に最も近い内
部電極層3cとは同じ外部電極4aに接続されるように
同じ端面に露出させる。また内部電極層3dは異なる端
面に露出させる。
In this sintered body, the internal electrode layers 3b, 3
c and 3d are formed between the first thermistor layers 1 with one end exposed at the opposing end faces of the sintered body, and the internal electrode layer 3b closest to the second thermistor layer 2 and the second thermistor layer 2 and is exposed on the same end face so as to be connected to the same external electrode 4a as the internal electrode layer 3c closest to the first thermistor layer 1. The internal electrode layer 3d is exposed at a different end face.

【0024】さらに内部電極層3aは内部電極層3b,
3c,3dの露出した両端面とは異なる焼結体の一方の
側面に露出させる。
Further, the internal electrode layer 3a includes the internal electrode layer 3b,
It is exposed on one side surface of the sintered body different from the exposed both end surfaces of 3c and 3d.

【0025】次に焼結体の内部電極層3aの露出した側
面及び内部電極層3b,3c,3dの露出した端面にA
gを主成分とする電極ペーストを塗布して、800℃で
焼き付けて外部電極4a,4b,4cを形成する。
Next, the exposed side surfaces of the internal electrode layer 3a of the sintered body and the exposed end surfaces of the internal electrode layers 3b, 3c, 3d
The electrode paste containing g as a main component is applied and baked at 800 ° C. to form the external electrodes 4a, 4b, and 4c.

【0026】その後、外部電極4a,4b,4cの上に
電解メッキ法によりニッケル膜(図示せず)、さらにこ
の上に半田膜(図示せず)を形成し、図1に示す複合積
層サーミスタを得た。
Thereafter, a nickel film (not shown) is formed on the external electrodes 4a, 4b, 4c by electrolytic plating, and a solder film (not shown) is further formed thereon, and the composite laminated thermistor shown in FIG. 1 is formed. Obtained.

【0027】この複合積層サーミスタにおいて積層体を
挟んで対向する外部電極4a,4b間で発生する抵抗は
内部電極層3a,3b間で発生する抵抗と、内部電極層
3cと外部電極4b間に発生する抵抗の並列抵抗であ
る。しかしながら第2サーミスタ層2の比抵抗が第1サ
ーミスタ層1の比抵抗よりも小さいため内部電極層3c
と外部電極4b間で発生する抵抗は内部電極層3a,3
b間で発生する抵抗と比較すると非常に大きいものであ
る。したがって、外部電極4a,4b間で発生する抵抗
は内部電極層3a,3b間に発生する抵抗に略等しく、
そのB定数は第1サーミスタ層1のB定数に略等しい。
In this composite laminated thermistor, the resistance generated between the external electrodes 4a and 4b opposed to each other across the multilayer body is the resistance generated between the internal electrode layers 3a and 3b and the resistance generated between the internal electrode layer 3c and the external electrode 4b. This is the parallel resistance of the resistors. However, since the specific resistance of the second thermistor layer 2 is smaller than the specific resistance of the first thermistor layer 1, the internal electrode layer 3c
Between the internal electrode layers 3a and 3b.
This is very large as compared with the resistance generated between b. Therefore, the resistance generated between the external electrodes 4a and 4b is substantially equal to the resistance generated between the internal electrode layers 3a and 3b,
The B constant is substantially equal to the B constant of the first thermistor layer 1.

【0028】また、外部電極4a,4bとは積層体の異
なる面に設けた外部電極4cは第1サーミスタ層1の表
面のみに形成し、第2サーミスタ層2の表面には形成し
ないようにすることにより、外部電極4a,4c間で発
生する抵抗は、内部電極層3c,3d間に発生する抵抗
に等しく、そのB定数は第2サーミスタ層2のB定数に
等しくなる。
The external electrode 4c provided on a different surface of the laminate from the external electrodes 4a and 4b is formed only on the surface of the first thermistor layer 1 and is not formed on the surface of the second thermistor layer 2. Thus, the resistance generated between the external electrodes 4a and 4c is equal to the resistance generated between the internal electrode layers 3c and 3d, and the B constant is equal to the B constant of the second thermistor layer 2.

【0029】ここで比較のために図12に示す従来の積
層サーミスタにおいてサーミスタ層101をMn:C
o:Fe:Al=32.5:50:10:7.5原子%
比となるような原料を用いて形成した第1積層サーミス
タと、サーミスタ層101をMn:Ni:Cu=68:
23:9の原子%比となるような原料を用いて形成した
第2積層サーミスタとを作製した。
For comparison, in the conventional laminated thermistor shown in FIG.
o: Fe: Al = 32.5: 50: 10: 7.5 atomic%
A first laminated thermistor formed by using a material having a ratio and a thermistor layer 101 are formed by Mn: Ni: Cu = 68:
A second laminated thermistor formed using a raw material having an atomic ratio of 23: 9 was manufactured.

【0030】本実施の形態1の複合積層サーミスタと、
二種類の従来の積層サーミスタとを25℃と50℃のオ
イルバスに浸漬して抵抗値を測定した結果を(表1)に
示す。
The composite laminated thermistor according to the first embodiment,
The results obtained by immersing the two types of conventional laminated thermistors in an oil bath at 25 ° C. and 50 ° C. and measuring the resistance values are shown in Table 1.

【0031】[0031]

【表1】 [Table 1]

【0032】この(表1)を見るとわかるように本実施
の形態1の複合積層サーミスタは、外部電極4a,4b
間で従来の抵抗値の高い第1積層サーミスタの機能を有
し、外部電極4a,4c間で従来の抵抗値の低い第2積
層サーミスタの機能を有することがわかる。
As can be seen from Table 1, the composite laminated thermistor according to the first embodiment has the external electrodes 4a, 4b
It can be seen that it has the function of the conventional first laminated thermistor having a high resistance value between the external electrodes 4a and 4c, and has the function of the second laminated thermistor of the conventional low resistance value between the external electrodes 4a and 4c.

【0033】(実施の形態2)図5は本発明の実施の形
態2における複合積層サーミスタの斜視図、図6は図5
のA−B断面図、図7は図5のC−D断面図であり、5
は絶縁体層であり、図1〜図3と同じ構成要素について
は同番号を付して説明を省略する。
(Embodiment 2) FIG. 5 is a perspective view of a composite laminated thermistor according to Embodiment 2 of the present invention, and FIG.
7 is a sectional view taken along the line AB of FIG. 5, and FIG.
Denotes an insulator layer, and the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals and description thereof is omitted.

【0034】本実施の形態2と実施の形態1との相違点
は第1サーミスタ層1と第2サーミスタ層2との境界面
全体に絶縁体層5を設けたことである。
The difference between the second embodiment and the first embodiment is that an insulator layer 5 is provided on the entire boundary surface between the first thermistor layer 1 and the second thermistor layer 2.

【0035】この絶縁体層5は焼成時に第1及び第2サ
ーミスタ層1,2と固溶せずに、第1及び第2サーミス
タ層1,2と略同じ焼結温度で、第1及び第2サーミス
タ層1,2と熱膨張係数が略同等の性質を有するセラミ
ック材料で形成した。
The insulator layer 5 does not form a solid solution with the first and second thermistor layers 1 and 2 at the time of firing, and the sintering temperature of the first and second thermistor layers 1 and 2 is substantially the same. It was formed of a ceramic material having substantially the same thermal expansion coefficient as the second thermistor layers 1 and 2.

【0036】この絶縁体層5を設けることにより、焼成
時に第1サーミスタ層1と第2サーミスタ層2間の相互
拡散を防止し、外部電極4a−4b間及び外部電極4a
−4c間の抵抗値、B定数が所望の値から変動するのを
防止することができる。
By providing the insulator layer 5, mutual diffusion between the first thermistor layer 1 and the second thermistor layer 2 during firing is prevented, and between the external electrodes 4a-4b and the external electrodes 4a
-4c can be prevented from varying from desired values.

【0037】なお、この複合積層サーミスタは実施の形
態1と同様にして作製する。
The composite laminated thermistor is manufactured in the same manner as in the first embodiment.

【0038】(実施の形態3)図8は本発明の実施の形
態3における複合積層サーミスタの斜視図、図9は図8
のA−B断面図、図10は図8のC−D断面図であり、
6はシールド電極層で、図1〜図3と同要素については
同番号を付して説明を省略する。
(Embodiment 3) FIG. 8 is a perspective view of a composite laminated thermistor according to Embodiment 3 of the present invention, and FIG.
AB sectional view of FIG. 10, FIG. 10 is a CD sectional view of FIG.
Reference numeral 6 denotes a shield electrode layer, and the same elements as those in FIGS.

【0039】本実施の形態3の複合積層サーミスタも実
施の形態2と同様に第1サーミスタ層1と第2サーミス
タ層2とが焼成時に相互拡散しないようにしたものであ
り、実施の形態2における絶縁体層5の代わりにシール
ド電極層6を第1サーミスタ層1と第2サーミスタ層2
との境界面に設けたものである。
In the composite laminated thermistor of the third embodiment, the first thermistor layer 1 and the second thermistor layer 2 are prevented from interdiffusion at the time of firing similarly to the second embodiment. The shield electrode layer 6 is replaced with the first thermistor layer 1 and the second thermistor layer 2 instead of the insulator layer 5.
Is provided at the boundary surface with

【0040】このシールド電極層6は、第1サーミスタ
層1間に挟まれるとともに第2サーミスタ層2に最も近
い内部電極層3bと、第2サーミスタ層2間に挟まれる
とともに第1サーミスタ層1に最も近い内部電極層3c
と同じ外部電極4aに一方の端部を接続しており同電位
としている。他方の端部は外部電極4bに非接続でかつ
ショート不良とならない程度にできるだけ外部電極4b
に近づけて形成している。また焼結体の側面側の端部も
できるだけ第1及び第2サーミスタ層1,2間の接着性
を確保しつつできるだけ側面端部に近づけて形成してい
る。即ち第1サーミスタ層1と第2サーミスタ層2間の
焼成時の相互拡散を防止するためにできるだけ大きく形
成することが望ましいのである。
The shield electrode layer 6 is sandwiched between the first thermistor layer 1 and the inner electrode layer 3b closest to the second thermistor layer 2, and between the second thermistor layer 2 and the first thermistor layer 1. Nearest internal electrode layer 3c
One end is connected to the same external electrode 4a as that of the above, and the potential is the same. The other end is not connected to the external electrode 4b and the external electrode 4b
It is formed close to. Also, the side end of the sintered body is formed as close as possible to the side end while ensuring the adhesiveness between the first and second thermistor layers 1 and 2 as much as possible. That is, it is desirable to form the first thermistor layer 1 and the second thermistor layer 2 as large as possible in order to prevent mutual diffusion during firing.

【0041】また、複合積層サーミスタの特性に及ぼす
影響をできるだけ小さくするために、シールド電極層6
と外部電極4b間で発生する抵抗が内部電極3c,3d
間で発生する抵抗と比べて無視できるほど大きくなるよ
う、シールド電極層6と外部電極4bの距離をできるだ
け近づける必要がある。
In order to minimize the influence on the characteristics of the composite laminated thermistor, the shield electrode layer 6
Between the internal electrodes 3c and 3d
It is necessary to make the distance between the shield electrode layer 6 and the external electrode 4b as short as possible so that the resistance is negligibly large as compared with the resistance generated between them.

【0042】上記実施の形態3ではシールド電極層6を
外部電極4aに接続しているが、図11に示すように外
部電極4a,4bに非接続の状態として構わない。この
場合、シールド電極層6に最も近い内部電極3b,3c
を接続する外部電極は4aでなくても構わない。
In the third embodiment, the shield electrode layer 6 is connected to the external electrode 4a, but may be disconnected from the external electrodes 4a and 4b as shown in FIG. In this case, the inner electrodes 3b, 3c closest to the shield electrode layer 6
Need not be 4a.

【0043】即ち、内部電極3b,3cは外部電極4
a,4bのいずれか一方に接続すれば良い。但しこの時
内部電極3dは内部電極3cを接続しなかった方の外部
電極4a,4bの一方に接続するようにする。
That is, the internal electrodes 3b and 3c are
What is necessary is just to connect to either one of a and 4b. However, at this time, the internal electrode 3d is connected to one of the external electrodes 4a and 4b to which the internal electrode 3c is not connected.

【0044】本実施の形態の複合積層サーミスタも実施
の形態1に示した製造方法で作製する。
The composite laminated thermistor of this embodiment is also manufactured by the manufacturing method shown in the first embodiment.

【0045】[0045]

【発明の効果】以上本発明によると、一つの複合積層サ
ーミスタで少なくとも二つのサーミスタ特性を有するこ
とにより、水晶発振子の温度補償回路など複数のサーミ
スタを使用する電子機器において小型化に寄与できる。
As described above, according to the present invention, since one composite laminated thermistor has at least two thermistor characteristics, it is possible to contribute to miniaturization of an electronic device using a plurality of thermistors such as a temperature compensation circuit of a crystal oscillator.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1における複合積層サーミ
スタの斜視図
FIG. 1 is a perspective view of a composite laminated thermistor according to Embodiment 1 of the present invention.

【図2】図1のA−B断面図FIG. 2 is a sectional view taken along a line AB in FIG.

【図3】図1のC−D断面図FIG. 3 is a sectional view taken along line CD of FIG. 1;

【図4】図1に示す複合積層サーミスタの外部電極形成
前の分解斜視図
FIG. 4 is an exploded perspective view of the composite laminated thermistor shown in FIG. 1 before external electrodes are formed.

【図5】本発明の実施の形態2における複合積層サーミ
スタの斜視図
FIG. 5 is a perspective view of a composite laminated thermistor according to Embodiment 2 of the present invention.

【図6】図5のA−B断面図6 is a sectional view taken along a line AB in FIG. 5;

【図7】図5のC−D断面図FIG. 7 is a sectional view taken along line CD of FIG. 5;

【図8】本発明の実施の形態3における複合積層サーミ
スタの斜視図
FIG. 8 is a perspective view of a composite laminated thermistor according to Embodiment 3 of the present invention.

【図9】図8のA−B断面図9 is a sectional view taken along a line AB in FIG.

【図10】図8のC−D断面図FIG. 10 is a sectional view taken along line CD of FIG. 8;

【図11】本発明の一実施の形態における複合積層サー
ミスタの断面図
FIG. 11 is a sectional view of a composite laminated thermistor according to an embodiment of the present invention.

【図12】一般的な水晶発振子の温度補償回路図FIG. 12 is a temperature compensation circuit diagram of a general crystal oscillator.

【図13】従来のサーミスタの断面図FIG. 13 is a sectional view of a conventional thermistor.

【符号の説明】[Explanation of symbols]

1 第1サーミスタ層 2 第2サーミスタ層 3a 内部電極層 3b 内部電極層 3c 内部電極層 3d 内部電極層 4a 外部電極 4b 外部電極 4c 外部電極 5 絶縁体層 6 シールド電極層 DESCRIPTION OF SYMBOLS 1 1st thermistor layer 2 2nd thermistor layer 3a internal electrode layer 3b internal electrode layer 3c internal electrode layer 3d internal electrode layer 4a external electrode 4b external electrode 4c external electrode 5 insulator layer 6 shield electrode layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 沖本 知久 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 佐藤 義之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 ▲高▼橋 雅幸 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 幅田 悦朗 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E034 BA10 BB01 BC01 BC02 DA07 DB11 DC10 DD08  ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tomohisa Okimoto 1006 Kadoma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor ▲ Taka ▼ Masayuki Hashi 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Etsuro 1006 Kadoma Kadoma, Kadoma, Osaka Pref. BA10 BB01 BC01 BC02 DA07 DB11 DC10 DD08

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 サーミスタ層と内部電極層とを交互に積
層した積層体の表面に外部電極を形成した積層サーミス
タを少なくとも二つ積層した複合積層サーミスタにおい
て、前記各積層サーミスタは比抵抗の異なるサーミスタ
層で形成した複合積層サーミスタ。
1. A composite laminated thermistor in which at least two laminated thermistors each having an external electrode formed on the surface of a laminate in which a thermistor layer and an internal electrode layer are alternately laminated, wherein the laminated thermistors have different specific resistances. Composite laminated thermistor formed of layers.
【請求項2】 比抵抗の高い積層サーミスタの外部電極
の一つは比抵抗の低い積層サーミスタの外部電極の形成
面と異なる面に形成した請求項1に記載の複合積層サー
ミスタ。
2. The composite thermistor according to claim 1, wherein one of the external electrodes of the multilayer thermistor having a high specific resistance is formed on a surface different from a surface on which the external electrode of the multilayer thermistor having a low specific resistance is formed.
【請求項3】 積層サーミスタ間に絶縁体層を設けた請
求項1に記載の複合積層サーミスタ。
3. The composite multilayer thermistor according to claim 1, wherein an insulator layer is provided between the multilayer thermistors.
【請求項4】 積層サーミスタ間に隣接する内部電極層
と同じ外部電極に接続したシールド電極層を設けた請求
項1に記載の複合積層サーミスタ。
4. The composite multilayer thermistor according to claim 1, further comprising a shield electrode layer connected to the same external electrode as the internal electrode layer adjacent between the multilayer thermistors.
JP32798399A 1999-11-18 1999-11-18 Composite laminate thermistor Pending JP2001143904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP32798399A JP2001143904A (en) 1999-11-18 1999-11-18 Composite laminate thermistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32798399A JP2001143904A (en) 1999-11-18 1999-11-18 Composite laminate thermistor

Publications (1)

Publication Number Publication Date
JP2001143904A true JP2001143904A (en) 2001-05-25

Family

ID=18205201

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP2001143904A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1470557A1 (en) * 2002-01-10 2004-10-27 Lamina Ceramics, Inc. Temperature compensation device with integral sheet thermistors
JP2005512317A (en) * 2001-12-04 2005-04-28 エプコス アクチエンゲゼルシャフト Electrical device with negative temperature coefficient
WO2006080805A1 (en) * 2005-01-27 2006-08-03 Ls Cable Ltd. Surface-mounting type thermistor having multi layers and method for manufacturing the same
JP2007299777A (en) * 2006-04-27 2007-11-15 Tdk Corp Laminated semiconductor ceramic
US7974070B2 (en) * 2007-09-21 2011-07-05 Tdk Corporation Multilayer ceramic device and mounting structure therefor
WO2015019643A1 (en) * 2013-08-08 2015-02-12 株式会社村田製作所 Thermistor element

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005512317A (en) * 2001-12-04 2005-04-28 エプコス アクチエンゲゼルシャフト Electrical device with negative temperature coefficient
EP1470557A1 (en) * 2002-01-10 2004-10-27 Lamina Ceramics, Inc. Temperature compensation device with integral sheet thermistors
EP1470557A4 (en) * 2002-01-10 2008-12-03 Lamina Ceramics Inc Temperature compensation device with integral sheet thermistors
WO2006080805A1 (en) * 2005-01-27 2006-08-03 Ls Cable Ltd. Surface-mounting type thermistor having multi layers and method for manufacturing the same
JP2007299777A (en) * 2006-04-27 2007-11-15 Tdk Corp Laminated semiconductor ceramic
US7974070B2 (en) * 2007-09-21 2011-07-05 Tdk Corporation Multilayer ceramic device and mounting structure therefor
WO2015019643A1 (en) * 2013-08-08 2015-02-12 株式会社村田製作所 Thermistor element
JPWO2015019643A1 (en) * 2013-08-08 2017-03-02 株式会社村田製作所 Thermistor element

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