JP2000124006A - Laminated thermistor - Google Patents
Laminated thermistorInfo
- Publication number
- JP2000124006A JP2000124006A JP10294945A JP29494598A JP2000124006A JP 2000124006 A JP2000124006 A JP 2000124006A JP 10294945 A JP10294945 A JP 10294945A JP 29494598 A JP29494598 A JP 29494598A JP 2000124006 A JP2000124006 A JP 2000124006A
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- Japan
- Prior art keywords
- thermistor
- layer
- laminated
- resistance
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は水晶発振子等の温度
補償に使用する積層型サーミスタに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated thermistor used for temperature compensation of a crystal oscillator or the like.
【０００２】[0002]
【従来の技術】従来の積層型サーミスタは特公昭５０−
１１５８５号公報に開示されており、その構造を図２に
示す。積層型サーミスタはサーミスタ層５を挟んで一対
の内部電極６ａ，６ｂを有し、この内部電極６ａ，６ｂ
の一方の端部はそれぞれ外部電極７ａ，７ｂに接続され
た構成となっている。2. Description of the Related Art A conventional laminated thermistor is disclosed in
It is disclosed in Japanese Patent Publication No. 11585 and its structure is shown in FIG. The laminated thermistor has a pair of internal electrodes 6a and 6b with a thermistor layer 5 interposed therebetween.
Are connected to external electrodes 7a and 7b, respectively.
【０００３】[0003]
【発明が解決しようとする課題】しかし、前記積層型サ
ーミスタの抵抗値Ｒは、内部電極６ａ，６ｂ間の抵抗値
ＲAと、内部電極６ａの先端と外部電極７ｂ間、内部電
極６ｂの先端部と外部電極７ａ間の抵抗値ＲB及び外部
電極７ａ，７ｂ間の抵抗値ＲCによって定まる。即ち、
次式の関係が成立する。However, the resistance value R of the laminated thermistor depends on the resistance value RA between the internal electrodes 6a and 6b, the distance between the tip of the internal electrode 6a and the external electrode 7b, and the tip of the internal electrode 6b. parts and resistance value between the external electrodes 7a R B and the external electrodes 7a, determined by the resistance R C of between 7b. That is,
The following relationship holds.
【０００４】１／Ｒ＝１／ＲA＋１／ＲB＋１／ＲC 従って、従来の積層型サーミスタのように、内部電極６
ａ，６ｂ間及びその他の層を同一材料のセラミックで形
成した場合は、ＲA要素のほかにＲB，ＲC要素の影響を
受けて抵抗値設計が困難となり、歩留まりが低下すると
共に、この積層型サーミスタを厳しい環境下で長期間使
用すると、外部電極７ａ，７ｂ間（特に表面層成分）の
抵抗値ＲCの変化の影響を受け、全体の抵抗変化率が大
きくなるという課題がある。また高い抵抗値を設計する
ために、内部電極６ａと６ｂの間隔を大きくすると更に
その影響が大きくなる。1 / R = 1 / R A + 1 / R B + 1 / R C Therefore, like the conventional laminated thermistor, the internal electrode 6
a, the case of forming the 6b and between the other layers in the ceramic of the same material, in addition to R B of R A element, the resistance value designed under the influence of R C components becomes difficult, the yield is decreased, the If the laminated thermistor is used for a long time in a severe environment, there is a problem that the resistance value RC between the external electrodes 7a and 7b (particularly, a surface layer component) changes, and the overall resistance change rate increases. If the distance between the internal electrodes 6a and 6b is increased in order to design a high resistance value, the influence is further increased.
【０００５】本発明は従来の課題を解決するもので、抵
抗値設計が容易なしかも耐環境性にすぐれた積層型サー
ミスタを提供することを目的とする。An object of the present invention is to solve the conventional problem and to provide a laminated thermistor which is easy to design a resistance value and has excellent environmental resistance.
【０００６】[0006]
【課題を解決するための手段】この課題を解決するため
に本発明の積層型サーミスタは、一対の外部電極とそれ
に電気的に接続された少なくとも一対以上の内部電極を
有する積層型サーミスタにおいて、その最外層を内部電
極間のサーミスタ層より比抵抗の高いセラミック層で形
成することにより、内部電極ＲAに対するＲBとＲCの影
響度を小さくすると共に、外部電極間の表面層抵抗ＲC
の抵抗値変化の影響を小さくすることができ、これによ
り所期の目的を達成するものである。SUMMARY OF THE INVENTION In order to solve this problem, a multilayer thermistor according to the present invention comprises a multilayer thermistor having a pair of external electrodes and at least one pair of internal electrodes electrically connected thereto. by forming the outermost ceramic layer higher than the specific resistance thermistor layer between the internal electrodes, thereby reducing the influence of R B and R C to the internal electrodes R a, the surface layer resistance R C between the external electrodes
The effect of the change in the resistance value can be reduced, thereby achieving the intended purpose.
【０００７】[0007]
【発明の実施の形態】本発明の請求項１記載の発明は、
一対の外部電極とそれに電気的に接続された少なくとも
一対以上の内部電極を有する積層型サーミスタにおい
て、その最外層を前記内部電極間のサーミスタ層より比
抵抗の高いセラミック層で形成した積層型サーミスタで
あり、最外層を比抵抗の高いセラミック層で形成するこ
とによって、内部電極間の抵抗値ＲAに対するその他の
抵抗値成分ＲB，ＲCの影響度を小さくすることができ抵
抗値設計が容易になると共に、耐環境性能も向上させる
ことができるものである。BEST MODE FOR CARRYING OUT THE INVENTION
In a multilayer thermistor having a pair of external electrodes and at least one or more internal electrodes electrically connected thereto, a multilayer thermistor in which the outermost layer is formed of a ceramic layer having a higher specific resistance than the thermistor layer between the internal electrodes is used. Since the outermost layer is formed of a ceramic layer having a high specific resistance, the influence of the other resistance value components R B and R C on the resistance value R A between the internal electrodes can be reduced, and the resistance value can be easily designed. And the environmental resistance can be improved.
【０００８】請求項２記載の発明は、サーミスタ層とセ
ラミック層を同じ温度で焼結するように組成調整をした
請求項１に記載の積層型サーミスタであり、サーミスタ
層とセラミック層を同じ温度で焼結させることにより、
双方の緻密化が同時に進行し、両者の積層界面での歪み
が少なく積層型サーミスタの焼結体の機械的強度の低下
を防ぐことができる。According to a second aspect of the present invention, there is provided the laminated thermistor according to the first aspect, wherein the composition is adjusted so that the thermistor layer and the ceramic layer are sintered at the same temperature. By sintering,
The densification of both layers proceeds at the same time, and the distortion at the interface between the two layers is small, and a decrease in the mechanical strength of the sintered body of the multilayer thermistor can be prevented.
【０００９】請求項３記載の発明は、セラミック層の熱
膨張係数をサーミスタ層の熱膨張係数よりも小さく設定
した請求項１に記載の積層型サーミスタであり、これに
よって積層型サーミスタは常時最外層表面から圧縮応力
が加わった状態となり機械的強度を向上させることがで
きる。According to a third aspect of the present invention, there is provided the multilayer thermistor according to the first aspect, wherein the thermal expansion coefficient of the ceramic layer is set to be smaller than the thermal expansion coefficient of the thermistor layer. The state where the compressive stress is applied from the surface is obtained, and the mechanical strength can be improved.
【００１０】請求項４記載の発明は、セラミック層の厚
さをサーミスタ層の厚さより厚く形成した請求項１に記
載の積層型サーミスタであり、これによって、内部電極
間の抵抗値ＲAに対するその他の抵抗値成分ＲB，ＲCの
影響度を更に小さくすることができるという効果を有す
るものである。[0010] The invention of claim 4, wherein is a laminated thermistor according to claim 1 in which the thickness of the ceramic layer is formed thicker than the thickness of the thermistor layer, whereby, other against the resistance R A between the internal electrodes Has an effect that the degree of influence of the resistance value components R B and R C can be further reduced.
【００１１】以下、本発明の一実施の形態について、添
付図面を用いて説明する。図１は本発明の一実施の形態
における積層型サーミスタの断面図を示す。図において
１はサーミスタ層、２ａ，２ｂは内部電極、３ａ，３ｂ
はセラミック層、４ａ，４ｂは外部電極である。得られ
た積層型サーミスタの抵抗Ｒは次式で表される。An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a sectional view of a laminated thermistor according to an embodiment of the present invention. In the figure, 1 is a thermistor layer, 2a and 2b are internal electrodes, 3a and 3b
Is a ceramic layer, and 4a and 4b are external electrodes. The resistance R of the obtained laminated thermistor is expressed by the following equation.
【００１２】１／Ｒ＝１／Ｒ1＋１／Ｒ2＋１／Ｒ3 但し、Ｒは積層型サーミスタの抵抗値 Ｒ1は内部電極２ａ，２ｂ間で発生する抵抗値 Ｒ2は内部電極２ａ先端部と外部電極４ｂ間、及び内部
電極２ｂの先端部と外部電極４ａ間で発生する抵抗値 Ｒ3は外部電極４ａ，４ｂ間で発生する抵抗値 一般的に、サーミスタ層１、セラミック層３ａ，３ｂを
同じ材料で形成した場合の抵抗値の大きさはＲ1＜Ｒ2＜
Ｒ3の関係にある。また内部電極２ａ，２ｂ間の距離を
Ｔ、内部電極２ａ，２ｂの対向面積をＳ、サーミスタ層
１の比抵抗をｐ 1とするとＲ1は次式で表される。1 / R = 1 / R1+ 1 / RTwo+ 1 / RThree Here, R is the resistance value of the multilayer thermistor R1Is a resistance value R generated between the internal electrodes 2a and 2b.TwoIs between the tip of the internal electrode 2a and the external electrode 4b, and
Resistance value R generated between the tip of electrode 2b and external electrode 4aThreeIs a resistance value generated between the external electrodes 4a and 4b. Generally, the thermistor layer 1 and the ceramic layers 3a and 3b
The resistance value when formed from the same material is R1<RTwo<
RThreeIn a relationship. Also, the distance between the internal electrodes 2a and 2b is
T, the area facing the internal electrodes 2a, 2b is S, thermistor layer
The specific resistance of 1 is p 1Then R1Is represented by the following equation.
【００１３】Ｒ1＝ｐ1・Ｔ／Ｓ サーミスタ層１よりセラミック層３ａ，３ｂの比抵抗を
高い材料で構成しその比抵抗をｐ2、内部電極２ａまた
は２ｂの先端部とそれに相対する外部電極４ｂ，４ａ間
の距離をＬ、外部電極４ａ，４ｂ間の距離をＤとする
と、Ｒ2はｐ1，ｐ 2、Ｌに、Ｒ3はｐ1，ｐ2、Ｄに比例し
た値となる。R1= P1・ T / S The specific resistance of the ceramic layers 3a and 3b from the thermistor layer 1
It is made of high material and its specific resistance is pTwo, The internal electrode 2a or
Is between the tip of 2b and the external electrodes 4b and 4a facing it.
Is L, and the distance between the external electrodes 4a and 4b is D.
And RTwoIs p1, P Two, L, RThreeIs p1, PTwo, Is proportional to D
Value.
【００１４】図２の従来の積層型サーミスタの最外層
を、本実施の形態のサーミスタ層１と同じ材料で構成
し、他のパラメータ（Ｓ，Ｔ，Ｌ，Ｄ）も同じとする
と、従来の積層型サーミスタのＲ2はｐ1、Ｌに、Ｒ3は
ｐ1、Ｄに比例した値となる。Assuming that the outermost layer of the conventional laminated thermistor shown in FIG. 2 is made of the same material as the thermistor layer 1 of the present embodiment and the other parameters (S, T, L, D) are the same, R 2 of the laminated thermistor has a value proportional to p 1 and L, and R 3 has a value proportional to p 1 and D.
【００１５】従ってｐ1＜ｐ2の関係から本実施の形態の
積層型サーミスタのＲ2，Ｒ3は従来のものより小さくな
る。Therefore, from the relation of p 1 <p 2 , R 2 and R 3 of the multilayer thermistor of the present embodiment are smaller than those of the prior art.
【００１６】次に、本発明の具体的な実施例を説明す
る。 （実施例）公知の窯業的手法を用い、Ｍｎ：Ｎｉ：Ｃｒ
＝８１．５：１７．５：１．０（ａｔ％）からなる比抵
抗ｐ1＝２．４ｋΩ・cm、及びＭｎ：Ｎｉ：Ａｌ：Ｃｒ
＝７２．５：１７．５：９．０：１．０（ａｔ％）から
なる比抵抗ｐ2＝１２ｋΩ・cmのそれぞれの材料を作製
した。Next, a specific embodiment of the present invention will be described. (Example) Mn: Ni: Cr using a known ceramic method
= 81.5: 17.5: 1.0 (at%), specific resistance p 1 = 2.4 kΩ · cm, and Mn: Ni: Al: Cr
= 72.5: 17.5: 9.0: 1.0 (at%), and each material having a specific resistance p 2 = 12 kΩ · cm was produced.
【００１７】次に、前記材料を公知のドクターブレード
法を用い、それぞれ厚さ２５μｍのグリーンシートを作
製した。Next, a green sheet having a thickness of 25 μm was prepared from each of the above materials by a known doctor blade method.
【００１８】次いで、公知の積層セラミックコンデンサ
の製造方法に従って積層型サーミスタのグリーンブロッ
クを作製した。Next, a green block of a multilayer thermistor was manufactured according to a known method for manufacturing a multilayer ceramic capacitor.
【００１９】先ず、高比抵抗材料のＭｎ：Ｎｉ：Ａｌ：
Ｃｒ系グリーンシートを５層積層加圧着し最外層セラミ
ック層３ａ，３ｂのグリーンシートを作製する。First, a high resistivity material Mn: Ni: Al:
Five layers of Cr-based green sheets are pressure-bonded to form green sheets of the outermost ceramic layers 3a and 3b.
【００２０】次に、セラミック層３ａのグリーンシート
面に低比抵抗材料のＭｎ：Ｎｉ：Ｃｒ系のグリーンシー
トを２層積層圧着した後、その面にスクリーン印刷によ
ってＰｄを主成分とする電極ペーストで内部電極２ａを
形成した低抵抗材料のＭｎ−Ｎｉ−Ｃｒ系グリーンシー
トの積層圧着を行い、続いて、その面に同様に内部電極
２ｂを形成した低抵抗材料のＭｎ−Ｎｉ−Ｃｒ系グリー
ンシートを内部電極２ａの長手方向に所定寸法ずらし積
層圧着を行う。更に低抵抗材料のＭｎ−Ｎｉ−Ｃｒ系グ
リーンシートを２層積層圧着を行い、最後に高比抵抗材
料のＭｎ：Ｎｉ：Ａｌ：Ｃｒ系セラミック層３ｂのグリ
ーンシートを積層圧着して積層体グリーンブロック（図
示せず）を作製した。Next, two layers of Mn: Ni: Cr-based green sheets of a low resistivity material are laminated and pressed on the green sheet surface of the ceramic layer 3a, and an electrode paste mainly composed of Pd is screen-printed on the surface. The Mn-Ni-Cr-based green sheet of the low-resistance material having the internal electrode 2a formed thereon is laminated and pressed, and subsequently, the Mn-Ni-Cr-based green of the low-resistance material having the same internal electrode 2b formed on its surface. The sheet is shifted by a predetermined dimension in the longitudinal direction of the internal electrode 2a, and is subjected to lamination pressure bonding. Further, two layers of a low-resistance material Mn-Ni-Cr-based green sheet are laminated and pressed, and finally, a green sheet of a high-resistivity material Mn: Ni: Al: Cr-based ceramic layer 3b is laminated and pressed, thereby obtaining a green laminate. A block (not shown) was made.
【００２１】その後、作製したグリーンブロックを、所
定寸法に切断しグリーンチップを得る。得られたグリー
ンチップは一方の端面に内部電極２ａの端面が、対向す
る他方の端面には低抵抗材料のＭｎ−Ｎｉ−Ｃｒ系グリ
ーンシートを挟んで内部電極２ｂの端面が露出した状態
となっている。Thereafter, the produced green block is cut into a predetermined size to obtain a green chip. In the obtained green chip, the end surface of the internal electrode 2a is exposed on one end surface, and the end surface of the internal electrode 2b is exposed on the other end surface with a Mn-Ni-Cr-based green sheet of a low-resistance material interposed therebetween. ing.
【００２２】得られたグリーンチップを大気中の１３５
０℃の温度で焼成し焼結体を作製した後、焼結体の面取
りを行い、焼結体の両端面に内部電極２ａ，２ｂの一方
の端面を完全に露出させる。The obtained green chip was put into air at 135
After firing at a temperature of 0 ° C. to produce a sintered body, the sintered body is chamfered to completely expose one end surface of each of the internal electrodes 2a and 2b to both end surfaces of the sintered body.
【００２３】続いて、焼結体の両端面部にＡｇを主成分
とする電極ペーストを塗布した後、８００℃の温度で焼
付けを行って外部電極４ａ，４ｂを形成した。Subsequently, an electrode paste containing Ag as a main component was applied to both end portions of the sintered body, and baked at a temperature of 800 ° C. to form external electrodes 4a and 4b.
【００２４】次に、外部電極４ａ，４ｂの面上に電解メ
ッキ法により、ニッケル膜、更にその上に半田膜を形成
し、図１に示す積層型サーミスタを完成させた。Next, a nickel film was formed on the surfaces of the external electrodes 4a and 4b by electrolytic plating, and a solder film was further formed thereon, thereby completing the multilayer thermistor shown in FIG.
【００２５】また、比較例として全ての層を低抵抗材料
のＭｎ−Ｎｉ−Ｃｒ系グリーンシートを用いて、本実施
例と同様に図２に示す従来の積層型サーミスタを作製し
た。As a comparative example, a conventional multi-layer thermistor shown in FIG. 2 was prepared in the same manner as in this example, using Mn-Ni-Cr-based green sheets of low resistance material for all layers.
【００２６】作製した、本実施例及び従来例の積層型サ
ーミスタの抵抗値Ｒのバラツキと、温度８５℃、湿度８
５％の恒温恒湿槽に１０００時間放置する湿中放置試験
前後の抵抗値変化率の評価を行いその結果を（表１）に
示した。Variations in the resistance value R of the laminated thermistors of the present embodiment and the conventional example, a temperature of 85 ° C. and a humidity of 8
The rate of change in resistance was evaluated before and after a wet test in which the sample was left in a 5% constant temperature / humidity chamber for 1000 hours. The results are shown in Table 1.
【００２７】[0027]
【表１】 [Table 1]
【００２８】（表１）に示すように、本発明の積層型サ
ーミスタは従来例に比較し、抵抗値変動係数が１／２、
湿中放置試験での抵抗変化率が１／５と小さくなってい
ることが分かる。これは本発明の最外層に高比抵抗のセ
ラミック層３ａ，３ｂを形成することによって、抵抗値
Ｒ1に対する抵抗値Ｒ2，Ｒ3の寄与率が小さくなり、設
計どおりの値を得ることができることを示している。ま
た湿中放置試験においても外部電極４ａ，４ｂ間のセラ
ミック層３ａ，３ｂ表面の抵抗値Ｒ3変化の寄与度が小
さくなり抵抗値変化率も小さくなったものと思われる。As shown in (Table 1), the multilayer thermistor of the present invention has a resistance variation coefficient of 、,
It can be seen that the resistance change rate in the wet test was reduced to 1/5. This is because the contribution ratios of the resistance values R 2 and R 3 to the resistance value R 1 are reduced by forming the ceramic layers 3 a and 3 b having a high specific resistance on the outermost layer of the present invention, and it is possible to obtain a designed value. Indicates that you can do it. Also, it is considered that the contribution of the change in the resistance value R 3 of the surface of the ceramic layers 3a and 3b between the external electrodes 4a and 4b was reduced in the wet test, and the rate of change in the resistance value was also reduced.
【００２９】従って、内部電極２ａ，２ｂの対向面積Ｓ
と距離Ｔを精度よく作製すれば、内部電極２ａ，２ｂの
先端部と外部電極４ａ，４ｂの距離Ｌ、外部電極４ａ，
４ｂ間の間隔Ｄのパラメータによる抵抗値変動要素の影
響の少ない、対環境性の優れた積層型サーミスタを提供
することができ、工業的に効果の高いものとなる。Therefore, the facing area S of the internal electrodes 2a, 2b
And the distance T with high precision, the distance L between the tip of the internal electrode 2a, 2b and the external electrode 4a, 4b, the external electrode 4a,
It is possible to provide a laminated thermistor that is less affected by a resistance value variation element due to the parameter of the distance D between the 4b and is excellent in environmental friendliness, and is industrially highly effective.
【００３０】[0030]
【発明の効果】以上本発明によれば、一対の外部電極と
それに電気的に接続された少なくとも一対以上の内部電
極を有する積層型サーミスタにおいて、その最外層を前
記内部電極間のサーミスタ層より比抵抗の高いセラミッ
ク層で形成することによって、抵抗値設計が容易で、抵
抗値バラツキが小さく、しかも耐湿性に優れた積層型サ
ーミスタの提供が可能となる。As described above, according to the present invention, in a laminated thermistor having a pair of external electrodes and at least one pair of internal electrodes electrically connected to the external electrodes, the outermost layer has a higher ratio than the thermistor layer between the internal electrodes. By forming the ceramic thermistor with a high-resistance ceramic layer, it is possible to provide a laminated thermistor that is easy to design a resistance value, has small resistance value variation, and has excellent moisture resistance.
【図１】本発明の一実施の形態の積層型サーミスタの断
面図FIG. 1 is a sectional view of a laminated thermistor according to an embodiment of the present invention.
【図２】従来の積層型サーミスタの断面図FIG. 2 is a cross-sectional view of a conventional laminated thermistor.
１ サーミスタ層 ２ａ，２ｂ 内部電極 ３ａ，３ｂ セラミック層 ４ａ，４ｂ 外部電極 1 Thermistor layer 2a, 2b Internal electrode 3a, 3b Ceramic layer 4a, 4b External electrode
───────────────────────────────────────────────────── フロントページの続き (72)発明者 ▲高▼橋 雅幸 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 橘井 努 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 佐藤 義之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 幅田 悦朗 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5E034 BA07 BA10 BB01 DA07 DB15 DC01 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor ▲ Taka ▼ Masayuki Hashi 1006 Kadoma, Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. Inside (72) Inventor Yoshiyuki Sato 1006 Kadoma, Kazuma, Osaka Pref. Matsushita Electric Industrial Co., Ltd. (72) Inventor Etsuro Kazuma 1006 Kadoma, Kadoma, Osaka Pref. Matsushita Electric Industrial F-term 5E034 BA07 BA10 BB01 DA07 DB15 DC01
Claims (4)
れた少なくとも一対以上の内部電極を有する積層型サー
ミスタにおいて、その最外層を前記内部電極間のサーミ
スタ層より比抵抗の高いセラミック層で形成した積層型
サーミスタ。In a laminated thermistor having a pair of external electrodes and at least one pair of internal electrodes electrically connected thereto, the outermost layer is formed of a ceramic layer having a higher specific resistance than the thermistor layer between the internal electrodes. Laminated thermistor.
で焼結するように組成調整した請求項１に記載の積層型
サーミスタ。2. The multilayer thermistor according to claim 1, wherein the composition is adjusted so that the thermistor layer and the ceramic layer are sintered at the same temperature.
層の熱膨張係数よりも小さくなるように設定した請求項
１に記載の積層型サーミスタ。3. The multilayer thermistor according to claim 1, wherein the coefficient of thermal expansion of the ceramic layer is set to be smaller than the coefficient of thermal expansion of the thermistor layer.
さより厚く形成した請求項１に記載の積層型サーミス
タ。4. The multilayer thermistor according to claim 1, wherein the thickness of the ceramic layer is formed larger than the thickness of the thermistor layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10294945A JP2000124006A (en) | 1998-10-16 | 1998-10-16 | Laminated thermistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10294945A JP2000124006A (en) | 1998-10-16 | 1998-10-16 | Laminated thermistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2000124006A true JP2000124006A (en) | 2000-04-28 |
Family
ID=17814323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10294945A Pending JP2000124006A (en) | 1998-10-16 | 1998-10-16 | Laminated thermistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2000124006A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030030082A (en) * | 2001-10-08 | 2003-04-18 | 삼화콘덴서공업주식회사 | Negative temperature coefficient thermistor |
| US7140097B2 (en) | 2002-10-02 | 2006-11-28 | Murata Manufacturing Co., Ltd. | Method of manufacturing chip-type ceramic electronic component |
| JP2010258482A (en) * | 2001-12-04 | 2010-11-11 | Epcos Ag | Electrical device with negative temperature coefficient |
| JP2013004985A (en) * | 2011-06-17 | 2013-01-07 | National Cheng Kung Univ | Electronic component and manufacturing method therefor |
| CN103137326A (en) * | 2011-12-01 | 2013-06-05 | 李文熙 | Electronic component and manufacturing method thereof |
-
1998
- 1998-10-16 JP JP10294945A patent/JP2000124006A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030030082A (en) * | 2001-10-08 | 2003-04-18 | 삼화콘덴서공업주식회사 | Negative temperature coefficient thermistor |
| JP2010258482A (en) * | 2001-12-04 | 2010-11-11 | Epcos Ag | Electrical device with negative temperature coefficient |
| US7140097B2 (en) | 2002-10-02 | 2006-11-28 | Murata Manufacturing Co., Ltd. | Method of manufacturing chip-type ceramic electronic component |
| JP2013004985A (en) * | 2011-06-17 | 2013-01-07 | National Cheng Kung Univ | Electronic component and manufacturing method therefor |
| CN103137326A (en) * | 2011-12-01 | 2013-06-05 | 李文熙 | Electronic component and manufacturing method thereof |
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