JP2002015941A - Chip-type electronic component - Google Patents

Chip-type electronic component

Info

Publication number
JP2002015941A
JP2002015941A JP2000194193A JP2000194193A JP2002015941A JP 2002015941 A JP2002015941 A JP 2002015941A JP 2000194193 A JP2000194193 A JP 2000194193A JP 2000194193 A JP2000194193 A JP 2000194193A JP 2002015941 A JP2002015941 A JP 2002015941A
Authority
JP
Japan
Prior art keywords
layer
chip
type electronic
electronic component
reinforcing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000194193A
Other languages
Japanese (ja)
Inventor
Yuichi Murano
Nobuaki Nagai
Naoki Noda
Kazuyuki Okano
Iwao Ueno
巌 上野
和之 岡野
雄一 村野
伸明 永井
直樹 野田
Original Assignee
Matsushita Electric Ind Co Ltd
松下電器産業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Ind Co Ltd, 松下電器産業株式会社 filed Critical Matsushita Electric Ind Co Ltd
Priority to JP2000194193A priority Critical patent/JP2002015941A/en
Publication of JP2002015941A publication Critical patent/JP2002015941A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a high-performance chip-type electronic component, which exhibits high durability with respect to mechanical stresses, such as bending or tensile stress and to thermal stress and exhibits a high stability and reliability of electrical characteristics by improving flexibility which is one of important evaluation items of chip-type electronic components. SOLUTION: With respect to the chip-type electronic component, in which inner electrodes 12a, 12b and 12c are buried in a laminate 11 having effective and ineffective layers and which is provided with reinforcing layers 14 sandwiching the inner electrodes 12a, 12b and 12c, a thickness T1 of each of the inner electrodes 12a, 12b and 12c and a thickness T2 of the reinforcing layers 14 are respectively set within a range of 1-7 μm and are constituted so that |T1-T2|<= 4 μm.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、スイッチング電源
回路、DC−DCコンバータ回路、照明用インバータ回
路用としてプリント基板に表面実装される例えば積層セ
ラミックコンデンサ等のチップ型電子部品に関するもの
である。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type electronic component such as a multilayer ceramic capacitor which is surface-mounted on a printed circuit board for a switching power supply circuit, a DC-DC converter circuit, and a lighting inverter circuit.

【0002】[0002]

【従来の技術】従来より、プリント基板に表面実装され
る種々のチップ型電子部品が知られているが、例えばそ
の一例として積層セラミックコンデンサがある。以下に
この積層セラミックコンデンサの従来の技術について図
面を用いて説明する。
2. Description of the Related Art Conventionally, various chip-type electronic components mounted on a printed circuit board have been known. For example, there is a multilayer ceramic capacitor as an example. The conventional technology of this multilayer ceramic capacitor will be described below with reference to the drawings.

【0003】従来の積層セラミックコンデンサとして、
例えば特開平9−251903号公報に開示されている
ようなものがある。それによると、図5に示すように、
まずセラミック層53と内部電極52a,52b,52
cとを交互に積層して有効層を形成し、該有効層の上下
に設けられた無効層中に補強層54が、その一方の端部
が内部電極52b,52cの露出した両端面に設けられ
た外部電極50と接続されるように構成されていた。
[0003] As a conventional multilayer ceramic capacitor,
For example, there is one disclosed in JP-A-9-251903. According to that, as shown in FIG.
First, the ceramic layer 53 and the internal electrodes 52a, 52b, 52
and c are alternately laminated to form an effective layer, and a reinforcing layer 54 is provided in the ineffective layers provided above and below the effective layer, and one end thereof is provided on the exposed end faces of the internal electrodes 52b and 52c. It is configured to be connected to the external electrode 50 provided.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、このよ
うな従来の構成では積層体51の上下の無効層中に設け
られた補強層54が1層のみであるため、積層体51の
曲げや引っ張り等の機械的応力に対する強度が弱く、場
合によっては破壊に至ることがあり、さらには熱応力に
対する耐久性が不足しているという問題点を有してい
た。また、一般的に上記のような補強層が形成された積
層セラミックコンデンサにおいて、場合によっては補強
層と内部電極の厚みや双方の厚みの不均衡により期待通
りの結果が得られず、逆に曲げや引っ張り等の機械的強
度が低下したり、電気特性が劣化したりしていた。
However, in such a conventional configuration, since only one reinforcing layer 54 is provided in the upper and lower ineffective layers of the laminate 51, the laminate 51 is bent or pulled. Has a problem in that it has low strength against mechanical stress and may be broken in some cases, and has insufficient durability against thermal stress. In general, in a multilayer ceramic capacitor having a reinforcing layer as described above, an expected result cannot be obtained due to an imbalance between the thickness of the reinforcing layer and the internal electrode or the thickness of both, depending on the case. Mechanical strength such as tension and tension was reduced, and electrical characteristics were deteriorated.

【0005】そこで本発明は以上の様な課題を解決し、
曲げや引っ張り等の機械的応力やさらに熱応力に対する
耐久性が高く、チップ型電子部品として重要な評価項目
であるたわみ強度の向上を図り、電気特性の安定性と信
頼性に優れた高性能のチップ型電子部品を提供すること
を目的とするものである。
Therefore, the present invention solves the above problems,
It has high durability against mechanical stress such as bending and tension, and even thermal stress.It improves bending strength, which is an important evaluation item for chip-type electronic components, and has high performance with excellent stability and reliability of electrical characteristics. It is an object to provide a chip-type electronic component.

【0006】[0006]

【課題を解決するための手段】この目的を達成するため
に本発明のチップ型電子部品は、第1の複数のセラミッ
ク層の間に内部電極層を設けた有効層及び第2の複数の
セラミック層の間に設けられ所定間隔で配置された複数
の補強層を備えた無効層を有した基体と、基体の両端部
に設けられ、内部電極層と電気的に接合された一対の外
部電極とを備えたチップ型電子部品であって、内部電極
層の厚みT1と補強層の厚みT2は各々1〜7μmの範
囲内で、且つ|T1−T2|≦4μmとした。
In order to achieve this object, a chip-type electronic component according to the present invention comprises an effective layer having an internal electrode layer between a first plurality of ceramic layers and a second plurality of ceramic layers. A base having an ineffective layer provided with a plurality of reinforcing layers provided at predetermined intervals and provided between the layers, and a pair of external electrodes provided at both ends of the base and electrically connected to the internal electrode layer; The thickness T1 of the internal electrode layer and the thickness T2 of the reinforcing layer are each in the range of 1 to 7 μm, and | T1−T2 | ≦ 4 μm.

【0007】[0007]

【発明の実施の形態】請求項1記載の発明は、第1の複
数のセラミック層の間に内部電極層を設けた有効層及び
第2の複数のセラミック層の間に設けられ所定間隔で配
置された複数の補強層を備えた無効層を有した基体と、
前記基体の両端部に設けられ、前記内部電極層と電気的
に接合された一対の外部電極とを備えたチップ型電子部
品であって、内部電極層の厚みT1と補強層の厚みT2
は各々1〜7μmの範囲内で、且つ|T1−T2|≦4
μmであることを特徴とするチップ型電子部品とするこ
とで、曲げや引っ張り等の機械的応力に対する耐久性が
向上し、亀裂の発生を防止すると共に、たとえ亀裂が発
生したとしても、発生した亀裂の進展が抑制される。こ
こで、内部電極層の厚みT1が1μm未満では内部電極
切れが発生し積層セラミックコンデンサにおいては正規
の静電容量が確保できなくなる恐れがあり、また7μm
を越えると亀裂の発生原因となる為いずれも好ましくな
い。補強層の厚みT2が1μm未満では補強層としての
用をなさず機械的応力に対する十分な耐久性が得られ
ず、また7μmを越えると亀裂の発生原因となり機械的
応力に対する耐久性が劣化するためいずれも好ましくな
い。さらに、補強層の厚みT2と内部電極層の厚みT1
との相違が4μmを越えると、構造的に不均衡となり曲
げや引張り等の機械的応力の局所的な集中が発生し、信
頼性低下の原因となるため好ましくない。
According to the first aspect of the present invention, an effective layer having an internal electrode layer provided between a plurality of first ceramic layers and a second ceramic layer are provided at predetermined intervals. A substrate having an ineffective layer with a plurality of reinforcing layers,
A chip-type electronic component comprising a pair of external electrodes provided at both ends of the base and electrically connected to the internal electrode layer, wherein a thickness T1 of the internal electrode layer and a thickness T2 of the reinforcing layer are provided.
Is in the range of 1 to 7 μm, respectively, and | T1−T2 | ≦ 4
With the chip-type electronic component characterized by having a size of μm, the durability against mechanical stress such as bending and pulling is improved, cracks are prevented from occurring, and even if cracks are generated, Crack growth is suppressed. Here, if the thickness T1 of the internal electrode layer is less than 1 μm, the internal electrode may be cut off, and a proper capacitance may not be secured in the multilayer ceramic capacitor.
If the ratio exceeds the above, cracks are likely to be generated. If the thickness T2 of the reinforcing layer is less than 1 μm, it cannot be used as a reinforcing layer, and sufficient durability against mechanical stress cannot be obtained. If it exceeds 7 μm, cracks are caused and durability against mechanical stress deteriorates. Neither is preferred. Further, the thickness T2 of the reinforcing layer and the thickness T1 of the internal electrode layer
If the difference from 4 μm exceeds 4 μm, the structure becomes unbalanced, and local concentration of mechanical stress such as bending and tension occurs, which is not preferable because it causes a reduction in reliability.

【0008】請求項2記載の発明は、有効層を挟むよう
に前記有効層の両側に無効層を設けたことを特徴とする
請求項1記載のチップ型電子部品とすることで、更に機
械的な強度を向上させることができる。
According to a second aspect of the present invention, there is provided a chip-type electronic component according to the first aspect, wherein an invalid layer is provided on both sides of the effective layer so as to sandwich the effective layer. Strength can be improved.

【0009】請求項3記載の発明は、複数の補強層の内
少なくとも一層の補強層はセラミック層の表面において
複数に分割されていることを特徴とする請求項1記載の
チップ型電子部品とすることで、分割された補強層の配
置を様々換えることで、仕様に応じた機械的強度を得る
ことができる。
According to a third aspect of the present invention, there is provided a chip-type electronic component according to the first aspect, wherein at least one of the plurality of reinforcing layers is divided into a plurality of portions on the surface of the ceramic layer. Thus, by changing the arrangement of the divided reinforcing layers in various ways, it is possible to obtain mechanical strength according to specifications.

【0010】請求項4記載の発明は、複数の補強層の内
少なくとも一層の補強層はセラミック層の表面において
連続した一つの補強層であることを特徴とする請求項1
記載のチップ型電子部品とすることで、補強層の作成が
容易になり生産性が向上する。
According to a fourth aspect of the present invention, at least one of the plurality of reinforcing layers is one continuous reinforcing layer on the surface of the ceramic layer.
With the chip-type electronic component described, the formation of the reinforcing layer is facilitated, and the productivity is improved.

【0011】請求項5記載の発明は、全ての補強層が外
部電極とは非接触となるように構成されたことを特徴と
する請求項1記載のチップ型電子部品とすることで、複
数の補強層と外部電極を非接触としているため積層セラ
ミックコンデンサとして余分な静電容量成分が発生する
ことがなく、また機械的応力に対し十分な耐久性を有す
る信頼性に優れたチップ型電子部品を実現できるという
作用を有する。
According to a fifth aspect of the present invention, there is provided a chip-type electronic component according to the first aspect, wherein all the reinforcing layers are configured to be in non-contact with the external electrode. Since the reinforcing layer and the external electrode are not in contact with each other, no extra capacitance component is generated as a multilayer ceramic capacitor, and a highly reliable chip-type electronic component with sufficient durability against mechanical stress It has the effect that it can be realized.

【0012】請求項6記載の発明は、全ての補強層が外
部電極と接触するように構成されたことを特徴とする請
求項1記載のチップ型電子部品とすることで、最も応力
のかかりやすい補強層の他方の端部が対向する外部電極
と物理的に接合されている為、機械的応力や熱応力に対
し高度な耐久性を有し、信頼性に優れたチップ型電子部
品を実現できるという作用を有する。
According to a sixth aspect of the present invention, in the chip-type electronic component according to the first aspect, all of the reinforcing layers are configured to be in contact with the external electrodes, and the stress is most likely to be applied. Since the other end of the reinforcing layer is physically bonded to the facing external electrode, a highly reliable chip-type electronic component having high durability against mechanical stress and thermal stress can be realized. It has the action of:

【0013】請求項7記載の発明は、複数の補強層の内
一部の補強層は外部電極と非接触に設けられており、他
の補強層は外部電極と接触していることを特徴とする請
求項1記載のチップ型電子部品とすることで、最も応力
のかかりやすい補強層の他方の端部が対向する外部電極
と物理的に接合されている為、機械的応力や熱応力に対
し高度な耐久性を有し、信頼性に優れたチップ型電子部
品を実現できるという作用を有するとともに、補強層と
外部電極を非接触としているため積層セラミックコンデ
ンサとして余分な静電容量成分が発生することがなく、
また機械的応力に対し十分な耐久性を有する信頼性に優
れたチップ型電子部品を実現できるという作用を有す
る。
[0013] The invention according to claim 7 is characterized in that a part of the plurality of reinforcing layers is provided in non-contact with the external electrode, and the other reinforcing layers are in contact with the external electrode. In the chip-type electronic component according to claim 1, since the other end of the reinforcing layer, which is most susceptible to stress, is physically bonded to the external electrode opposed thereto, it is difficult to withstand mechanical stress and thermal stress. It has the function of realizing a chip-type electronic component with high durability and excellent reliability, and the extra capacitance component is generated as a multilayer ceramic capacitor because the reinforcing layer and the external electrode are not in contact. Without
Further, it has an effect that a highly reliable chip-type electronic component having sufficient durability against mechanical stress can be realized.

【0014】請求項8記載の発明は、補強層と外部電極
のそれぞれの構成材料は、同一元素を含むことを特徴と
する請求項1記載のチップ型電子部品とすることで、補
強層と外部電極の物理的接合を容易に行うことができる
という作用を有する。
According to an eighth aspect of the present invention, in the chip-type electronic component according to the first aspect, the constituent materials of the reinforcing layer and the external electrode contain the same element. This has the effect that physical bonding of the electrodes can be easily performed.

【0015】請求項9記載の発明は、同一元素はNiで
あることを特徴とする請求項8に記載のチップ型電子部
品とすることで、周波数特性に優れた、高性能のチップ
型電子部品を実現できるという作用を有する。
According to a ninth aspect of the present invention, the same element is Ni, and the chip-type electronic component according to the eighth aspect has a high frequency characteristic and high performance. Can be realized.

【0016】請求項10記載の発明は、補強層を構成す
る金属と外部電極を構成する金属とは合金を形成するこ
とを特徴とする請求項1記載のチップ型電子部品とする
ことによって、補強層を構成する金属と外部電極を構成
する金属が合金を形成することで、補強層と外部電極の
物理的及び電気的接合が容易になり、引っ張りや曲げ等
の機械的応力を分散することができるため、機械的応力
に対する耐久性が高いチップ型電子部品を実現できると
いう作用を有する。
According to a tenth aspect of the present invention, there is provided a chip-type electronic component according to the first aspect, wherein the metal forming the reinforcing layer and the metal forming the external electrode form an alloy. By forming an alloy between the metal constituting the layer and the metal constituting the external electrode, physical and electrical bonding between the reinforcing layer and the external electrode becomes easy, and mechanical stress such as tension and bending can be dispersed. Therefore, a chip-type electronic component having high durability against mechanical stress can be realized.

【0017】請求項11記載の発明は、外部電極は上
層、下層の二層構造であり、下層は積層体の端面のみに
設けたことを特徴とする請求項1記載のチップ型電子部
品とすることで、外部電極を2層構造にすることにより
外部電極側に分散された引っ張りや曲げ等の機械的応力
をさらに分散できるため、亀裂などの発生を防止でき
る。
According to an eleventh aspect of the present invention, there is provided the chip-type electronic component according to the first aspect, wherein the external electrode has a two-layer structure of an upper layer and a lower layer, and the lower layer is provided only on an end face of the laminate. Thus, by forming the external electrode into a two-layer structure, mechanical stresses such as tension and bending dispersed on the external electrode side can be further dispersed, so that generation of cracks and the like can be prevented.

【0018】請求項12記載の発明は、外部電極の下層
と内部電極のそれぞれの構成材料は、同一元素を含むこ
とを特徴とする請求項11に記載のチップ型電子部品と
するものであり、外部電極の下層と内部電極との物理的
接合が容易になり引っ張りや曲げ等の機械的応力が外部
電極側に分散され易くなり、また外部電極の下層と内部
電極との電気的接続が完璧なものとなるため、機械的耐
久性及び電気特性に優れた高信頼性のチップ型電子部品
を実現できるという作用を有する。
According to a twelfth aspect of the present invention, there is provided the chip-type electronic component according to the eleventh aspect, wherein each constituent material of the lower layer of the external electrode and the internal electrode contains the same element. Physical bonding between the lower layer of the external electrode and the internal electrode is facilitated, mechanical stress such as pulling and bending is easily distributed to the external electrode side, and the electrical connection between the lower layer of the external electrode and the internal electrode is perfect. Therefore, it has an effect that a highly reliable chip-type electronic component having excellent mechanical durability and electrical characteristics can be realized.

【0019】本発明のチップ型電子部品において、セラ
ミック層を構成する主成分化合物としては主にBaTi
3,SrTiO3,MgTiO3等のチタン酸塩系が適
用され、内部電極層を構成する金属としては、Niの他
に場合によってはAg−Pd系,Cu系を使用しても差
し支えない。また、工法上積層体と同時に焼成される下
層外部電極としては上記したようにNiが適用できる
が、その場合上層外部電極には、主としてAg系が用い
られる。また、外部電極にCuを適用しても差し支えな
い。
In the chip type electronic component of the present invention, the main component compound constituting the ceramic layer is mainly BaTi
A titanate such as O 3 , SrTiO 3 , MgTiO 3 or the like is applied. As a metal constituting the internal electrode layer, an Ag—Pd based or Cu based may be used in some cases in addition to Ni. As described above, Ni can be used as the lower external electrode which is fired simultaneously with the laminated body in the construction method. In this case, an Ag-based external electrode is mainly used as the upper external electrode. Also, Cu may be applied to the external electrode.

【0020】また、本発明のチップ型電子部品におい
て、積層体の無効層中に設けられる補強層としてはセラ
ミック層よりも展性や延性に富む金属が好ましく、N
i,Cu,Ag−Pd系等が用いられる。
Further, in the chip-type electronic component of the present invention, the reinforcing layer provided in the ineffective layer of the laminate is preferably a metal having higher malleability and ductility than the ceramic layer.
i, Cu, Ag-Pd type or the like is used.

【0021】以下、実施の形態において、本発明のチッ
プ型電子部品について、当該電子部品の一つである積層
セラミックコンデンサを用いて、図面を参照しながら詳
しく説明する。
Hereinafter, in embodiments, a chip-type electronic component of the present invention will be described in detail with reference to the drawings using a multilayer ceramic capacitor which is one of the electronic components.

【0022】(実施の形態1)図1は本発明の実施の形
態1におけるチップ型電子部品を示す断面図であり、1
1は積層体、12a,12b,12cは内部電極、13
はセラミック層、14は補強層、15は下層外部電極、
16は上層外部電極である。
(Embodiment 1) FIG. 1 is a sectional view showing a chip type electronic component according to Embodiment 1 of the present invention.
1 is a laminate, 12a, 12b and 12c are internal electrodes, 13
Is a ceramic layer, 14 is a reinforcing layer, 15 is a lower external electrode,
Reference numeral 16 denotes an upper external electrode.

【0023】ここで、該積層セラミックコンデンサの製
造方法を説明する。
Here, a method for manufacturing the multilayer ceramic capacitor will be described.

【0024】主成分であるBaTiO3粉末と添加剤の
各粉末を電子天秤で所定量を秤量し、焼結助剤成分と共
にボールミル中で20時間混合した。混合物はシルクス
クリーンで濾過して、テフロン(登録商標)シートを敷
いたステンレスバット中に投入し乾燥させた。乾燥した
塊状物はアルミナ乳鉢中で解砕した後、熱処理してスラ
リー用粉末とした。
Predetermined amounts of BaTiO 3 powder as the main component and each powder of the additive were weighed by an electronic balance and mixed with a sintering aid component in a ball mill for 20 hours. The mixture was filtered through a silk screen, placed in a stainless steel vat covered with a Teflon (registered trademark) sheet, and dried. The dried mass was pulverized in an alumina mortar and then heat-treated to obtain a slurry powder.

【0025】次に、スラリー用粉末100gを溶剤及び
可塑剤と共に混合することにより湿潤した。湿潤後、ポ
リビニルブチラール樹脂より成るビヒクルを使用してシ
ート成形用スラリーを作製した。
Next, 100 g of the slurry powder was wetted by mixing with a solvent and a plasticizer. After wetting, a sheet forming slurry was prepared using a vehicle made of a polyvinyl butyral resin.

【0026】次に、該スラリーを150メッシュのシル
クスクリーンで濾過した後、成膜してセラミック生シー
トを得た。そして、該セラミック生シートと、Niペー
ストより作製した内部電極シート及び補強層となるシ−
トを用いて転写工法により所定の積層仕様に基ずいて積
層した後、切断してグリーンチップを得た。ここで、内
部電極シート及び補強層となるシ−トは、焼成後の厚み
が1〜7μmの範囲内になるように、また双方のシ−ト
の焼成後の厚みの相違が4μm以下となるようにNiペ
ースト塗着量を調整して作製した。
Next, the slurry was filtered through a 150-mesh silk screen and then formed into a film to obtain a ceramic green sheet. Then, the ceramic raw sheet, an internal electrode sheet made of Ni paste and a sheet serving as a reinforcing layer are formed.
Then, after stacking based on a predetermined stacking specification by a transfer method using a sheet, a green chip was obtained by cutting. Here, the sheet to be the internal electrode sheet and the reinforcing layer has a thickness after firing within a range of 1 to 7 μm, and the difference in thickness between both sheets after firing is 4 μm or less. The amount of Ni paste applied was adjusted as described above.

【0027】次に、得られたグリーンチップを面取りし
た後、その両端面に下層外部電極となるNiペーストを
塗布し乾燥した後、脱脂した。そして、回転式雰囲気炉
により還元雰囲気焼成を実施した。グリーンガス、CO
2及びN2により調整したNiの平衡酸素分圧よりも2桁
低い酸素分圧雰囲気中で1250゜Cの温度で2時間保
持した。そして、焼成したチップの両端面に上層外部電
極となるAgを塗布して大気中で焼き付けた後、Ni鍍
金及びSn鍍金を施して本実施の形態の積層セラミック
コンデンサを完成させた。
Next, after the obtained green chip was chamfered, a Ni paste to be a lower external electrode was applied to both end surfaces, dried, and degreased. Then, firing in a reducing atmosphere was performed using a rotary atmosphere furnace. Green gas, CO
It was maintained at a temperature of 1250 ° C. for 2 hours in an oxygen partial pressure atmosphere two orders of magnitude lower than the equilibrium oxygen partial pressure of Ni adjusted by 2 and N 2 . Then, Ag as an upper external electrode was applied to both end surfaces of the fired chip, baked in the air, and then subjected to Ni plating and Sn plating to complete the multilayer ceramic capacitor of the present embodiment.

【0028】該積層セラミックコンデンサは、図1に示
したようにBaTiO3質セラミック層13とNiを含
む内部電極層12a,12b,12cとを交互に積層し
て形成された静電容量取得層となる有効層の上下に無効
層としてBaTiO3質セラミック層13が積層されて
積層体11が形成されており、該無効層中に複数のNi
質補強層14形成されていた。そして、該複数のNi質
補強層14は同一平面上でギャップを隔てて一方の端部
同士が向かい合い、他方の端部は対向するNi質下層外
部電極15と接合されており、該Ni質下層外部電極1
5の上にAg質上層外部電極が設けられていた。
As shown in FIG. 1, the multilayer ceramic capacitor has a capacitance acquisition layer formed by alternately laminating BaTiO 3 ceramic layers 13 and internal electrode layers 12a, 12b and 12c containing Ni. A BaTiO 3 -based ceramic layer 13 is stacked as an ineffective layer above and below the effective layer to form a laminated body 11, and a plurality of Nis are included in the ineffective layer.
The quality reinforcing layer 14 was formed. The plurality of Ni-type reinforcing layers 14 have one end facing each other with a gap on the same plane, and the other end is joined to the opposing Ni-type lower external electrode 15. External electrode 1
5 was provided with an Ag upper layer external electrode.

【0029】また、Ni質補強層14とNi質内部電極
層12a,12b,12cの厚みは、各々1〜7μmの
範囲内に制御されており、且つNi質補強層14とNi
質内部電極層12a,12b,12cの厚みの相違は4
μm以下であった。
The thickness of the Ni-based reinforcing layer 14 and the thickness of the Ni-based internal electrode layers 12a, 12b, 12c are controlled within a range of 1 to 7 μm, respectively.
The difference in thickness between the internal electrode layers 12a, 12b and 12c is 4
μm or less.

【0030】次に、本実施の形態の積層セラミックコン
デンサを図5に示した従来の構造より成る積層セラミッ
クコンデンサと共にたわみ試験に供した。なお、試験に
供した積層セラミックコンデンサは定格電圧が630V
DCで3216サイズの10000PF品として作製し
たものであり、各々20個試験した。その結果を(表
1)に示す。
Next, the multilayer ceramic capacitor of the present embodiment was subjected to a bending test together with the multilayer ceramic capacitor having the conventional structure shown in FIG. The multilayer ceramic capacitor used for the test had a rated voltage of 630V.
It was manufactured as a 3216 size 10000 PF product using DC, and 20 of each were tested. The results are shown in (Table 1).

【0031】[0031]

【表1】 [Table 1]

【0032】たわみ試験はチップ型電子部品の信頼性を
判断する為の重要な評価項目であり、専用のプリント基
板に被試験品を半田付けした後、専用の治具で3点曲げ
を付加させながら静電容量を測定し、静電容量値が急激
に低下した時点での基板のたわみ幅(mm)をたわみ強
度とするものである。通常、静電容量値が急激に低下し
た時点で被試験品に亀裂が発生している。従来の構造よ
り成る積層セラミックコンデンサにおいて、たわみ幅
(mm)が3mmで静電容量値が急激に低下して亀裂が
発生した被試験品が見られたのに対して、本実施の形態
の積層セラミックコンデンサは、全てたわみ幅(mm)
が7mm以上で静電容量値が急激に低下して亀裂が発生
し、たわみ強度の優れたものであった。
The deflection test is an important evaluation item for judging the reliability of the chip-type electronic component. After the DUT is soldered to a dedicated printed circuit board, a three-point bending is applied with a dedicated jig. While measuring the capacitance, the bending width (mm) of the substrate at the time when the capacitance value sharply decreases is defined as the bending strength. Normally, a crack occurs in the DUT at the time when the capacitance value sharply decreases. In the case of a multilayer ceramic capacitor having a conventional structure, a sample under test in which a deflection width (mm) was 3 mm and a capacitance value sharply decreased and a crack was generated was observed, whereas a multilayer ceramic capacitor according to the present embodiment was observed. All ceramic capacitors have a deflection width (mm)
Was 7 mm or more, the capacitance value sharply decreased, cracks occurred, and the flexural strength was excellent.

【0033】本実施の形態の積層セラミックコンデンサ
は、補強層14と下層外部電極15は共にNi質である
ため、物理的接合が完璧になり機械的応力を外部電極側
に分散する事が可能で、たわみ強度が向上し、さらに良
好な周波数特性を有するものである。また、外部電極を
2層構造とすることにより、機械的応力の外部電極側分
散効果が更に高くなる。
In the multilayer ceramic capacitor of the present embodiment, since the reinforcing layer 14 and the lower external electrode 15 are both made of Ni, the physical bonding is perfect and mechanical stress can be dispersed to the external electrode side. , The flexural strength is improved, and more favorable frequency characteristics are obtained. In addition, when the external electrode has a two-layer structure, the effect of dispersing mechanical stress on the external electrode side is further enhanced.

【0034】以上の様に本実施の形態によれば、機械的
応力に対し高度な耐久性を有し、たわみ強度に優れたチ
ップ型電子部品を実現できるという作用を有する。
As described above, according to the present embodiment, there is an effect that a chip-type electronic component having high durability against mechanical stress and excellent in bending strength can be realized.

【0035】(実施の形態2)図2は本発明の実施の形
態2におけるチップ型電子部品を示す断面図であり、2
1は積層体、22a,22b,22cは内部電極、23
はセラミック層、24は補強層、25は下層外部電極、
26は上層外部電極である。
(Embodiment 2) FIG. 2 is a sectional view showing a chip type electronic component according to Embodiment 2 of the present invention.
1 is a laminate, 22a, 22b and 22c are internal electrodes, 23
Is a ceramic layer, 24 is a reinforcing layer, 25 is a lower external electrode,
26 is an upper layer external electrode.

【0036】(実施の形態1)と同様の方法で作製した
該積層セラミックコンデンサは、図2に示したようにB
aTiO3質セラミック層23とNi質内部電極層22
a,22b,22cとを交互に積層して形成された静電
容量取得層となる有効層の上下に無効層としてBaTi
3質セラミック層23のみが積層されて積層体21が
形成されており、該無効層中に複数のNi質補強層24
形成されていた。そして、該複数のNi質補強層24は
同一平面上でギャップを隔てて一方の端部同士が向かい
合い、他方の端部の内少なくとも1層は対向するNi質
下層外部電極と物理的に非接触であり、該Ni質下層外
部電極25の上にAg質上層外部電極が設けられてい
た。
The multilayer ceramic capacitor manufactured by the same method as that of the first embodiment has a structure as shown in FIG.
aTiO 3 -based ceramic layer 23 and Ni-based internal electrode layer 22
a, 22b, and 22c are alternately stacked on top of and below the effective layer serving as a capacitance acquisition layer as a capacitance acquisition layer.
A laminate 21 is formed by laminating only the O 3 -based ceramic layer 23, and a plurality of Ni-based reinforcing layers 24 are provided in the ineffective layer.
Had been formed. The plurality of Ni-type reinforcing layers 24 have one end facing each other with a gap on the same plane, and at least one of the other ends is not in physical contact with the facing Ni-type lower external electrode. The Ag-based upper external electrode was provided on the Ni-based lower external electrode 25.

【0037】また、Ni質補強層24とNi質内部電極
層22a,22b,22cの厚みは、各々1〜7μmの
範囲内に制御されており、且つNi質補強層24とNi
質内部電極層22a,22b,22cの厚みの相違は4
μm以下であった。
The thickness of the Ni-based reinforcing layer 24 and the thickness of the Ni-based internal electrode layers 22a, 22b, 22c are each controlled within the range of 1 to 7 μm.
The difference in thickness between the internal electrode layers 22a, 22b and 22c is 4
μm or less.

【0038】本実施の形態の積層セラミックコンデンサ
も(実施の形態1)と同様に機械的耐久性に優れ、たわ
み強度の良好なものであった。
The multilayer ceramic capacitor of the present embodiment also has excellent mechanical durability and good bending strength as in the case of the first embodiment.

【0039】(実施の形態3)図3は本発明の実施の形
態3におけるチップ型電子部品を示す断面図であり、3
1は積層体、32a,32b,32cは内部電極、33
はセラミック層、34は補強層、35は下層外部電極、
36は上層外部電極である。
(Embodiment 3) FIG. 3 is a sectional view showing a chip-type electronic component according to Embodiment 3 of the present invention.
1 is a laminate, 32a, 32b and 32c are internal electrodes, 33
Is a ceramic layer, 34 is a reinforcing layer, 35 is a lower external electrode,
36 is an upper layer external electrode.

【0040】(実施の形態1)と同様の方法で作製した
該積層セラミックコンデンサは、図3に示したようにB
aTiO3質セラミック層33とNi質内部電極層32
a,32b,32cとを交互に積層して形成された静電
容量取得層となる有効層の上下に無効層としてBaTi
3質セラミック層33のみが積層されて積層体31が
形成されており、該無効層中に複数のNi質補強層34
形成されていた。そして、該複数のNi質補強層34は
同一平面上でギャップを隔てて一方の端部同士が向かい
合い、他方の端部は対向する下層外部電極35と物理的
に非接触であり、該Ni質下層外部電極35の上にAg
質上層外部電極36が設けられていた。
The monolithic ceramic capacitor manufactured by the same method as in the first embodiment has a structure as shown in FIG.
aTiO 3 ceramic layer 33 and Ni internal electrode layer 32
a, 32b, and 32c are alternately stacked, and BaTi is formed as an ineffective layer above and below an effective layer serving as a capacitance acquisition layer.
The laminated body 31 is formed by laminating only the O 3 -based ceramic layers 33, and a plurality of Ni-based reinforcing layers 34 are provided in the ineffective layer.
Had been formed. The ends of the plurality of Ni-based reinforcing layers 34 face each other with a gap on the same plane, and the other end is physically non-contact with the lower external electrode 35 facing the same. Ag on the lower external electrode 35
The upper layer external electrode 36 was provided.

【0041】また、Ni質補強層24とNi質内部電極
層22a,22b,22cの厚みは、各々1〜7μmの
範囲内に制御されており、且つNi質補強層24とNi
質内部電極層22a,22b,22cの厚みの相違は4
μm以下であった。
The thickness of the Ni-based reinforcing layer 24 and the thickness of each of the Ni-based internal electrode layers 22a, 22b, and 22c are controlled within a range of 1 to 7 μm.
The difference in thickness between the internal electrode layers 22a, 22b and 22c is 4
μm or less.

【0042】本実施の形態の積層セラミックコンデンサ
は、複数の補強層と外部電極を非接触としているため積
層セラミックコンデンサとして余分な静電容量成分が発
生することがなく、また、機械的応力に対し十分な耐久
性を有する信頼性に優れたものであった。
In the multilayer ceramic capacitor of the present embodiment, since the plurality of reinforcing layers and the external electrodes are not in contact with each other, no extra capacitance component is generated as the multilayer ceramic capacitor, and the multilayer ceramic capacitor is free from mechanical stress. It had sufficient durability and excellent reliability.

【0043】(実施の形態4)図4は本発明の実施の形
態4におけるチップ型電子部品を示す断面図であり、4
1は積層体、42a,42b,42cは内部電極、43
はセラミック層、44は補強層、45は下層外部電極、
46は上層外部電極である。
(Embodiment 4) FIG. 4 is a sectional view showing a chip-type electronic component according to Embodiment 4 of the present invention.
1 is a laminate, 42a, 42b and 42c are internal electrodes, 43
Is a ceramic layer, 44 is a reinforcing layer, 45 is a lower external electrode,
46 is an upper layer external electrode.

【0044】(実施の形態1)と同様の方法で作製した
該積層セラミックコンデンサは、図4に示したようにB
aTiO3質セラミック層43とNi質内部電極層42
a,42b,42cとを交互に積層して形成された静電
容量取得層となる有効層の上下に無効層としてBaTi
3質セラミック層43が積層されて積層体41が形成
されており、無効層中に複数のNi質補強層44形成さ
れていた。そして、該複数のNi質補強層44は一方の
端部及び他方の端部共に対向する外部電極と物理的に非
接触であり、該Ni質下層外部電極45の上にAg質上
層外部電極46が設けられていた。
The multilayer ceramic capacitor manufactured by the same method as that of the first embodiment has a structure as shown in FIG.
aTiO 3 ceramic layer 43 and Ni internal electrode layer 42
a, 42b, and 42c are alternately stacked on top of and below the effective layer serving as the capacitance acquisition layer as a capacitance acquisition layer.
The laminated body 41 was formed by laminating the O 3 -based ceramic layers 43, and a plurality of Ni-based reinforcing layers 44 were formed in the ineffective layer. The plurality of Ni-based reinforcing layers 44 are not physically in contact with the external electrodes facing one end and the other end, and the Ag-based upper external electrodes 46 are disposed on the Ni-based lower external electrodes 45. Was provided.

【0045】また、Ni質補強層44とNi質内部電極
層42a,42b,42cの厚みは、各々1〜7μmの
範囲内に制御されており、且つNi質補強層44とNi
質内部電極層42a,42b,42cの厚みの相違は4
μm以下であった。また、Ni質補強層24とNi質内
部電極層22a,22b,22cの厚みは、各々1〜7
μmの範囲内に制御されており、且つNi質補強層24
とNi質内部電極層22a,22b,22cの厚みの相
違は4μm以下であった。
The thickness of the Ni-based reinforcing layer 44 and the thickness of the Ni-based internal electrode layers 42a, 42b, 42c are each controlled within a range of 1 to 7 μm.
The difference between the thicknesses of the internal electrode layers 42a, 42b and 42c is 4
μm or less. The thicknesses of the Ni-based reinforcing layer 24 and the Ni-based internal electrode layers 22a, 22b, 22c are respectively 1 to 7
μm, and the Ni-type reinforcing layer 24
And the thickness difference between the Ni internal electrode layers 22a, 22b and 22c was 4 μm or less.

【0046】本実施の形態の積層セラミックコンデンサ
は、余分な静電容量成分が発生することがなく、また、
引っ張りや曲げ等の機械的応力や熱的応力に対し十分な
耐久性を有するものであった。
The multilayer ceramic capacitor of the present embodiment does not generate an extra capacitance component.
It had sufficient durability against mechanical and thermal stresses such as tension and bending.

【0047】なお、上記実施の形態においては内部電極
層が直列構造を有する積層セラミックコンデンサについ
て説明したが、内部電極層が並列構造を有する積層セラ
ミックコンデンサはもちろん、セラミック層と内部電極
層とを交互に積層したチップ型電子部品全般において本
発明は同様の効果が得られるものである。
In the above embodiment, a multilayer ceramic capacitor in which the internal electrode layers have a series structure has been described. However, not only a multilayer ceramic capacitor in which the internal electrode layers have a parallel structure, but also the ceramic layers and the internal electrode layers are alternately arranged. According to the present invention, the same effect can be obtained in all chip-type electronic components stacked on a substrate.

【0048】[0048]

【発明の効果】以上のように本発明によれば、セラミッ
ク層と内部電極層とを交互に積層して形成した有効層の
上下にセラミック層のみを積層して形成した無効層中に
補強層を設け、内部電極層と補強層の厚み及び双方の厚
みの有意差を限定することにより、曲げや引っ張り等の
機械的応力や熱応力に対する耐久性が高く、特にたわみ
強度に優れたチップ型電子部品を提供することができ
る。
As described above, according to the present invention, a reinforcing layer is formed in an ineffective layer formed by laminating only ceramic layers above and below an effective layer formed by alternately laminating ceramic layers and internal electrode layers. By limiting the thickness of the internal electrode layer and the reinforcing layer and the significant difference between the thicknesses, the chip-type electronic device has high durability against mechanical stress such as bending and tension and thermal stress, and particularly has excellent flexural strength. Parts can be provided.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1におけるチップ型電子部
品を示す断面図
FIG. 1 is a sectional view showing a chip-type electronic component according to a first embodiment of the present invention.

【図2】本発明の実施の形態2におけるチップ型電子部
品を示す断面図
FIG. 2 is a sectional view showing a chip-type electronic component according to a second embodiment of the present invention.

【図3】本発明の実施の形態3におけるチップ型電子部
品を示す断面図
FIG. 3 is a sectional view showing a chip-type electronic component according to a third embodiment of the present invention.

【図4】本発明の実施の形態4におけるチップ型電子部
品を示す断面図
FIG. 4 is a sectional view showing a chip-type electronic component according to a fourth embodiment of the present invention.

【図5】従来のチップ型電子部品を示す断面図FIG. 5 is a sectional view showing a conventional chip-type electronic component.

【符号の説明】[Explanation of symbols]

11,21,31,41 積層体 12a,22a,32a,42a 内部電極 12b,22b,32b,42b 内部電極 12c,22c,32c,42c 内部電極 13,23,33,43 セラミック層 14,24,34,44 補強層 15,25,35,45 下層外部電極 16,26,36,46 上層外部電極 50 外部電極 51 積層体 52a 内部電極 52b 内部電極 52c 内部電極 53 セラミック層 54 遊離補強層 11, 21, 31, 41 laminated body 12a, 22a, 32a, 42a internal electrode 12b, 22b, 32b, 42b internal electrode 12c, 22c, 32c, 42c internal electrode 13, 23, 33, 43 ceramic layer 14, 24, 34 , 44 Reinforcement layer 15, 25, 35, 45 Lower external electrode 16, 26, 36, 46 Upper external electrode 50 External electrode 51 Stack 52a Internal electrode 52b Internal electrode 52c Internal electrode 53 Ceramic layer 54 Free reinforcing layer

───────────────────────────────────────────────────── フロントページの続き (72)発明者 上野 巌 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 野田 直樹 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 岡野 和之 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5E001 AB03 AC04 AC06 AC07 AD00 AF00 AF06 AG00 5E082 AA01 AB03 BC33 EE11 FG26 GG10 GG26 GG28 JJ03 JJ23 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Iwao Ueno 1006 Kadoma Kadoma, Osaka Prefecture Inside Matsushita Electric Industrial Co., Ltd. (72) Inventor Naoki Noda 1006 Kadoma Kadoma, Kadoma City Osaka Pref. Matsushita Electric Industrial Co., Ltd. 72) Inventor Kazuyuki Okano 1006 Kadoma, Kazuma, Osaka Pref.F-term (reference) in Matsushita Electric Industrial Co., Ltd.

Claims (12)

    【特許請求の範囲】[Claims]
  1. 【請求項1】第1の複数のセラミック層の間に内部電極
    層を設けた有効層及び第2の複数のセラミック層の間に
    設けられ所定間隔で配置された複数の補強層を備えた無
    効層を有した基体と、前記基体の両端部に設けられ、前
    記内部電極層と電気的に接合された一対の外部電極とを
    備えたチップ型電子部品であって、内部電極層の厚みT
    1と補強層の厚みT2は各々1〜7μmの範囲内で、且
    つ|T1−T2|≦4μmであることを特徴とするチッ
    プ型電子部品。
    1. An ineffective layer comprising an effective layer having an internal electrode layer provided between a first plurality of ceramic layers and a plurality of reinforcing layers provided at predetermined intervals and provided between a second plurality of ceramic layers. A chip-type electronic component comprising: a substrate having a layer; and a pair of external electrodes provided at both ends of the substrate and electrically connected to the internal electrode layer, wherein the thickness T of the internal electrode layer is
    1 and a thickness T2 of the reinforcing layer are each in the range of 1 to 7 μm, and | T1−T2 | ≦ 4 μm.
  2. 【請求項2】有効層を挟むように前記有効層の両側に無
    効層を設けたことを特徴とする請求項1記載のチップ型
    電子部品。
    2. The chip-type electronic component according to claim 1, wherein an invalid layer is provided on both sides of said effective layer so as to sandwich said effective layer.
  3. 【請求項3】複数の補強層の内少なくとも一層の補強層
    はセラミック層の表面において複数に分割されているこ
    とを特徴とする請求項1記載のチップ型電子部品。
    3. The chip-type electronic component according to claim 1, wherein at least one of the plurality of reinforcing layers is divided into a plurality on the surface of the ceramic layer.
  4. 【請求項4】複数の補強層の内少なくとも一層の補強層
    はセラミック層の表面において連続した一つの補強層で
    あることを特徴とする請求項1記載のチップ型電子部
    品。
    4. The chip-type electronic component according to claim 1, wherein at least one of the plurality of reinforcing layers is one continuous reinforcing layer on the surface of the ceramic layer.
  5. 【請求項5】全ての補強層が外部電極とは非接触となる
    ように構成されたことを特徴とする請求項1記載のチッ
    プ型電子部品。
    5. The chip-type electronic component according to claim 1, wherein all the reinforcing layers are configured so as not to contact the external electrodes.
  6. 【請求項6】全ての補強層が外部電極と接触するように
    構成されたことを特徴とする請求項1記載のチップ型電
    子部品。
    6. The chip-type electronic component according to claim 1, wherein all the reinforcing layers are configured to be in contact with the external electrodes.
  7. 【請求項7】複数の補強層の内一部の補強層は外部電極
    と非接触に設けられており、他の補強層は外部電極と接
    触していることを特徴とする請求項1記載のチップ型電
    子部品。
    7. The method according to claim 1, wherein a part of the plurality of reinforcing layers is provided in non-contact with the external electrode, and the other reinforcing layers are in contact with the external electrode. Chip type electronic components.
  8. 【請求項8】補強層と外部電極のそれぞれの構成材料
    は、同一元素を含むことを特徴とする請求項1記載のチ
    ップ型電子部品。
    8. The chip-type electronic component according to claim 1, wherein constituent materials of the reinforcing layer and the external electrode contain the same element.
  9. 【請求項9】同一元素はNiであることを特徴とする請
    求項8に記載のチップ型電子部品。
    9. The chip-type electronic component according to claim 8, wherein the same element is Ni.
  10. 【請求項10】補強層を構成する金属と外部電極を構成
    する金属とは合金を形成することを特徴とする請求項1
    記載のチップ型電子部品。
    10. The method according to claim 1, wherein the metal forming the reinforcing layer and the metal forming the external electrode form an alloy.
    The described chip-type electronic component.
  11. 【請求項11】外部電極は上層、下層の二層構造であ
    り、下層は積層体の端面のみに設けたことを特徴とする
    請求項1記載のチップ型電子部品。
    11. The chip-type electronic component according to claim 1, wherein the external electrode has a two-layer structure of an upper layer and a lower layer, and the lower layer is provided only on an end face of the laminate.
  12. 【請求項12】外部電極の下層と内部電極のそれぞれの
    構成材料は、同一元素を含むことを特徴とする請求項1
    1に記載のチップ型電子部品。
    12. The method according to claim 1, wherein the constituent materials of the lower layer of the external electrode and the internal electrode contain the same element.
    2. The chip-type electronic component according to 1.
JP2000194193A 2000-06-28 2000-06-28 Chip-type electronic component Pending JP2002015941A (en)

Priority Applications (1)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000194193A JP2002015941A (en) 2000-06-28 2000-06-28 Chip-type electronic component

Publications (1)

Publication Number Publication Date
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Family

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Family Applications (1)

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Country Status (1)

Country Link
JP (1) JP2002015941A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263059A (en) * 2009-05-07 2010-11-18 Murata Mfg Co Ltd Electronic component and manufacturing method thereof
EP2410538A1 (en) * 2010-07-21 2012-01-25 Murata Manufacturing Co. Ltd. Ceramic electronic component
JP2013038332A (en) * 2011-08-10 2013-02-21 Tdk Corp Laminated capacitor
JP2013093374A (en) * 2011-10-24 2013-05-16 Murata Mfg Co Ltd Electronic component
JP2013539605A (en) * 2010-09-09 2013-10-24 エプコス アーゲーEpcos Ag Resistance element and manufacturing method thereof
US20140226255A1 (en) * 2013-02-13 2014-08-14 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic device and method for manufacturing the same
US20140240897A1 (en) * 2013-02-26 2014-08-28 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic device
KR101514559B1 (en) * 2013-10-30 2015-04-22 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
JP2016034047A (en) * 2011-09-01 2016-03-10 株式会社村田製作所 Mounting structure
JP2018006781A (en) * 2014-04-30 2018-01-11 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170924A (en) * 1984-02-16 1985-09-04 Matsushita Electric Ind Co Ltd Laminated ceramic condenser
JPH07183163A (en) * 1993-12-22 1995-07-21 Tdk Corp Trimming capacitor
JPH07297071A (en) * 1994-04-25 1995-11-10 Matsushita Electric Ind Co Ltd Multilayered grain boundary insulated semiconductor ceramic capacitor
JPH08181032A (en) * 1994-12-22 1996-07-12 Tokin Corp Laminated ceramic capacitor
JPH08222474A (en) * 1995-02-10 1996-08-30 Murata Mfg Co Ltd Manufacture of ceramic electronic component
JPH08279437A (en) * 1995-04-06 1996-10-22 Mitsubishi Materials Corp Chip type stacked ceramic capacitor
JPH09180956A (en) * 1995-10-03 1997-07-11 Tdk Corp Multilayer ceramic capacitor
JP2000138129A (en) * 1998-10-30 2000-05-16 Kyocera Corp Laminated ceramic capacitor and its manufacture

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60170924A (en) * 1984-02-16 1985-09-04 Matsushita Electric Ind Co Ltd Laminated ceramic condenser
JPH07183163A (en) * 1993-12-22 1995-07-21 Tdk Corp Trimming capacitor
JPH07297071A (en) * 1994-04-25 1995-11-10 Matsushita Electric Ind Co Ltd Multilayered grain boundary insulated semiconductor ceramic capacitor
JPH08181032A (en) * 1994-12-22 1996-07-12 Tokin Corp Laminated ceramic capacitor
JPH08222474A (en) * 1995-02-10 1996-08-30 Murata Mfg Co Ltd Manufacture of ceramic electronic component
JPH08279437A (en) * 1995-04-06 1996-10-22 Mitsubishi Materials Corp Chip type stacked ceramic capacitor
JPH09180956A (en) * 1995-10-03 1997-07-11 Tdk Corp Multilayer ceramic capacitor
JP2000138129A (en) * 1998-10-30 2000-05-16 Kyocera Corp Laminated ceramic capacitor and its manufacture

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010263059A (en) * 2009-05-07 2010-11-18 Murata Mfg Co Ltd Electronic component and manufacturing method thereof
CN102403123B (en) * 2010-07-21 2015-04-08 株式会社村田制作所 Ceramic electronic component
EP2410538A1 (en) * 2010-07-21 2012-01-25 Murata Manufacturing Co. Ltd. Ceramic electronic component
JP2012044148A (en) * 2010-07-21 2012-03-01 Murata Mfg Co Ltd Ceramic electronic component
KR101184175B1 (en) 2010-07-21 2012-09-18 가부시키가이샤 무라타 세이사쿠쇼 Ceramic electronic component
US8630081B2 (en) 2010-07-21 2014-01-14 Murata Manufacturing Co., Ltd. Ceramic electronic component
CN102403123A (en) * 2010-07-21 2012-04-04 株式会社村田制作所 Ceramic electronic component
US8947193B2 (en) 2010-09-09 2015-02-03 Epcos Ag Resistance component and method for producing a resistance component
JP2013539605A (en) * 2010-09-09 2013-10-24 エプコス アーゲーEpcos Ag Resistance element and manufacturing method thereof
JP2013038332A (en) * 2011-08-10 2013-02-21 Tdk Corp Laminated capacitor
JP2016034047A (en) * 2011-09-01 2016-03-10 株式会社村田製作所 Mounting structure
JP2013093374A (en) * 2011-10-24 2013-05-16 Murata Mfg Co Ltd Electronic component
US20140226255A1 (en) * 2013-02-13 2014-08-14 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic device and method for manufacturing the same
US9455085B2 (en) * 2013-02-13 2016-09-27 Samsung Electro-Mechanics Co., Ltd Multilayer ceramic device having a crack guide pattern
US20140240897A1 (en) * 2013-02-26 2014-08-28 Samsung Electro-Mechanics Co., Ltd. Multilayer ceramic device
CN104599839A (en) * 2013-10-30 2015-05-06 三星电机株式会社 Multilayer ceramic capacitor and board with the same mounted thereon
KR101514559B1 (en) * 2013-10-30 2015-04-22 삼성전기주식회사 Multi-layered ceramic capacitor and board for mounting the same
JP2018006781A (en) * 2014-04-30 2018-01-11 サムソン エレクトロ−メカニックス カンパニーリミテッド. Multilayer ceramic electronic component

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