JP3039005B2 - Chip varistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip type varistor using a sintered body made of a material exhibiting a voltage non-linear non-resistance characteristic, and more particularly, to an improved shape of electrodes which are overlapped via a sintered body layer. About varistors.

[0002]

2. Description of the Related Art Conventionally, a varistor has been used as an element for absorbing an abnormal voltage. 2. Description of the Related Art In recent years, electronic components have been formed into chips, and there has been a growing demand for varistors to be miniaturized to increase the packaging density or to lower the voltage in accordance with the integration of integrated circuits. In order to respond to the above demand, a multilayer varistor has been proposed (Japanese Patent Publication No. 58-23921, etc.). As shown in FIG. 2, this laminated varistor has a plurality of internal electrodes 3 to 6 arranged in a sintered body 2 made of a material exhibiting a voltage non-linear resistance characteristic, and opposing end faces 2 a and 2 of the sintered body 2.
b, external electrodes 7, 8 to which the internal electrodes 3 to 6 are electrically connected are formed.

At the time of manufacturing, as shown in FIG. 3, for example, raw sheets 9 to 13 made of a material exhibiting a voltage non-linear resistance characteristic are prepared. Internal electrodes 3 to 6 are formed on the upper surfaces of the raw sheets 10 to 13 by screen-printing a conductive paste as shown by hatching. By laminating and sintering these raw sheets 9 to 13, the sintered body 2 is obtained. In the laminated varistor, the number of internal electrodes must be 10 to 20 in order to obtain a surge resistance of 50 A to 100 A. However, the larger the number of layers, the larger the capacitance, which is suitable for use in power supply lines, but is not suitable for use in inserting into high-frequency signal lines. Therefore, a single-layer varistor in which only one layer of the internal electrode is arranged inside the sintered body and a surface electrode is formed on the surface of the sintered body so as to face the internal electrode has been devised.

[0004]

However, since the single-layer varistor has only one internal electrode, the contact area between the internal electrode and the external electrode is small. Therefore, when a large surge current is applied, a spark is generated due to the current concentration at a connection portion between the internal electrode and the external electrode, and there is a possibility of causing a breakdown. Therefore, an object of the present invention is to provide a chip type varistor which has a large contact area between an internal electrode and an external electrode and can withstand a large surge current.

[0005]

In the chip varistor of the present invention, a surface electrode is formed on the surface of a sintered body made of a material exhibiting a voltage non-linear resistance characteristic. At least one internal electrode is formed so as to face the surface electrode via the layer or to overlap with each other via the sintered body layer. The surface electrode and at least one internal electrode are extended to the first or second end face of the sintered body, and the first and second external electrodes are respectively provided on the first and second end faces. Is formed.

[0006] Then, the first internal electrode, there is a first or wide substantially T-shaped configuration of the second end face side relative width of the sintered body in which the electrode is pulled out even without least It is characterized by.

[0007]

[Action] Internal electrode that is formed into a substantially T-shape is drawn in a large area on the first or second end surface of the sintered body. Therefore, since the connection area between the substantially T-shaped electrode and the external electrode is increased, current concentration is reduced, and the surge withstand capability is increased.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, non-limiting embodiments of the present invention will be described. First, the structure of a chip varistor according to an embodiment of the present invention will be described by describing a method of manufacturing the chip varistor according to the embodiment. First, as shown in FIG. 1, a rectangular raw sheet 21 mainly composed of a material exhibiting a voltage non-linear resistance.
~ 25 are prepared. The upper surface of each of the raw sheets 21 and 22 is screen-printed with a conductive paste, as shown by hatching with diagonal lines, so that the surface electrodes 26 are formed.
And the internal electrodes 27 are formed.

The surface electrode 26 is formed so as to be drawn out to one edge 21a of the raw sheet 21. On the one edge 21a side, the surface electrode 26 is formed so as to reach the entire width of the raw sheet 21. That is, it is printed in a substantially T-shape.
Similarly, the internal electrode 27 is also printed in a substantially T-shape. However, the internal electrode 27 is arranged such that the raw sheets 21 and 22 are stacked in the illustrated direction, and is drawn out to the end face opposite to the surface electrode 26 so that the one edge 22 of the raw sheet 22 is drawn out.
It is printed so that the width is relatively wide on the a side.

[0010] The green sheets 21 to 25 shown in FIG. 1 are laminated, the obtained laminate is pressed in the thickness direction, and then fired, whereby the sintered body 28 shown in FIG. 4 is obtained. Next, the first end face 28a and the second end face 28b of the sintered body 28
Is baked so as to cover at least the first and second external electrodes 29 and 30 electrically connected to the surface electrode 26 and the internal electrode 27, respectively.
Is formed, and a glaze 31 made of, for example, zinc borosilicate is baked on other portions. Thus, FIG.
Can be obtained.

As described above, in the chip varistor 32 according to the present embodiment, the surface electrode 26 and the internal electrode 27 are substantially T-shaped.
And a surface electrode 26 and an internal electrode 27.
The width of the part drawn out from the first and second end faces 28a and 28b of the sintered body 28 is increased. Therefore, the surface electrode 26 and the internal electrode 27 and the first and second external electrodes 2
Since the contact area with the first and second external electrodes 29 and 3 is increased, the contact area between the first and second external electrodes 29 and 3 is increased.
The current concentration at the contact portion with zero is alleviated, and the surge withstand capability is increased.

In this embodiment, both the surface electrode 26 and the internal electrode 27 are formed in a substantially T-shape. However, even in a structure in which only one of them is formed in a substantially T-shape, as described above. The effect of alleviating power concentration can be obtained for the time being. In addition to the internal electrode 27, the present invention can be applied to a chip varistor in which one or more internal electrodes are arranged so as to overlap with each other with a sintered body layer interposed therebetween.
As long as any one of the surface electrode and the plurality of internal electrodes is formed in a substantially T-shape, the effects of the present invention can be obtained for the time being.

Further, with respect to the substantially T-shaped shape in the present invention, the surface electrode 26 and the internal electrode 27 shown in FIG.
It is not limited to the shape. For example, as shown in FIG. 6, the surface electrodes 36, 3 formed on the upper surfaces of the raw sheets 21, 22 are formed.
7, the relatively wide portions 36a, 37a on the side of the edges 21a, 22a and the relatively narrow portions 36b,
37b may be formed into a shape that is continuous with a curve. In addition, the portions of the substantially T-shaped surface electrode and the internal electrode that are extended to the first and second end surfaces do not necessarily need to be formed to have a width that reaches the entire width of the raw sheet as in the illustrated example. In short, it is only necessary that the drawn-out portion of the first or second end face of the sintered body has a relatively large width as compared with the electrode portions in other regions.

Next, specific experimental results of the embodiment described with reference to FIGS. 1, 4 and 5 will be described. ZnO, CoO, MnO, Sb ₂ O _3, and Bi ₂ O ₃ having a purity of 99% or more were respectively 97.8, 0.5, and 0.
Weighed at 5, 0.7 and 0.5 mol%. The weighed materials were mixed in pure water using a ball mill for 24 hours. The obtained mixture was filtered, dried, and then calcined at a temperature of 800 ° C. for 2 hours. Next, the calcined product was pulverized, and the obtained pulverized product was dispersed in alcohol together with a polyvinyl butyral resin to obtain a slurry.

A green sheet was formed from the obtained slurry by a doctor blade method. The obtained raw sheet was punched into a rectangular shape having a predetermined size, and the raw sheet 2 shown in FIG.
1 to 25 were prepared. Next, using a conductive paste composed of an Ag-Pd alloy and an organic vehicle,
A surface electrode 26 and an internal electrode 27 are printed on the upper surface of 22,
Lamination and pressure bonding were performed in the state of FIG. After that, 950 ℃
For 2 hours. First and second of the obtained sintered body
The first and second external electrodes 29 and 30 are formed by baking a conductive paste containing Ag as a main component on the end surfaces of the first and second end surfaces 28a and 28b. Glaze 31 made of zinc was baked.

An impact current of 8/20 μsec is applied twice at 5 minute intervals to the chip varistor of the embodiment obtained as described above, so that the varistor voltage (V _1mA ) does not change by 10% or more. The value (surge tolerance) was measured. For comparison, a chip varistor having a surface electrode 41 and an internal electrode 42 printed in the shape shown in FIG. 7 was manufactured. The difference from the embodiment is that the shapes of the surface electrode 41 and the internal electrode 42 are
It is not just a T-shape as in the embodiment,
Others were made in exactly the same way.

The surge immunity of the chip varistor of the comparative example obtained as described above and a commercially available laminated varistor having a structure equivalent to that of the conventional example of FIG. 2 were measured in the same manner as the chip varistor of the example. The measurement results are shown in Table 1 below together with the varistor voltage (V _{1 mA} ), the voltage nonlinear coefficient (α), and the capacitance (C).

[0018]

[Table 1]

As is clear from Table 1, the chip varistor of this embodiment has a surge withstand capability about 1.5 times that of the chip varistors of the comparative example and the commercially available example. Further, the capacitance is drastically reduced as compared with a commercially available chip varistor, and thus it can be seen that the varistor is suitable for use in a high frequency range.

[0020]

As it is evident from the foregoing description, according to the present invention, since the small without <br/> least one internal electrode is substantially T-shape, the symbolic T
The contact area between the shaped electrode and the external electrode is increased,
Thereby, the surge withstand capability is greatly increased. Therefore,
If the number of stacked internal electrodes is reduced, a chip varistor suitable for a high-frequency signal line can be obtained.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view illustrating a raw sheet and electrode shapes used to obtain a chip varistor according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a conventional multilayer varistor.

FIG. 3 is an exploded perspective view showing a raw sheet used to obtain the laminated varistor of FIG. 2 and the shape of an electrode formed thereon.

FIG. 4 is a sectional view of a chip varistor according to one embodiment of the present invention.

FIG. 5 is a perspective view of a chip varistor according to one embodiment of the present invention.

FIG. 6 is an exploded perspective view for explaining a modification of the substantially T-shaped electrode.

FIG. 7 is an exploded perspective view showing a raw sheet used to obtain a comparative example and shapes of electrodes formed thereon.

[Explanation of symbols]

 26 surface electrode 27 internal electrode 28 sintered body 28a, 28b first and second end surfaces 29 and 30 first and second external electrode 36 surface electrode 37 internal electrode

Continued on the front page (72) Inventor Kazutaka Nakamura 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Inside Murata Manufacturing Co., Ltd. (72) Inventor Yasunobu Yoneda 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Murata Co., Ltd. (56) References JP-A-60-202902 (JP, A) JP-A-63-110702 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01C ⁷ /02- 7/22

Claims (1)

(57) [Claims] 1. A sintered body made of a material exhibiting voltage non-linear resistance characteristics, and a first sintered body formed on a surface of the sintered body.
Or, a surface electrode drawn out to the second end face, and disposed in the sintered body, so as to overlap with the surface electrode via the sintered body layer, or to overlap with each other via the sintered body layer. The first of the sintered body
Or at least one internal electrode drawn out from a second end face, and first and second internal electrodes formed on first and second end faces of the sintered body.
Of the chip varistor and an external electrode, one of the internal electrodes even without least the first or second relatively wide than the rest of the end face near the side of the sintered body in which the electrode is withdrawn A chip varistor characterized in that the chip varistor is formed in a substantially T-shaped shape having a wide width.