JP2985444B2 - Stacked varistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a laminated varistor functioning as a voltage non-linear resistor, and more particularly, it can improve the scattering of organic substances during firing to reduce variations in varistor voltage and capacitance. And a structure capable of reducing leakage current.

[0002]

2. Description of the Related Art In general, a varistor is a resistor element whose resistance value varies non-linearly in accordance with an applied voltage, and is used, for example, as a surge absorbing element for preventing an overvoltage from being applied to an electronic circuit. In recent years, in the field of electronic devices such as communication devices, miniaturization and integration of electronic components have been progressing, and accordingly, demands for miniaturization or low voltage of varistors have been increasing. Conventionally, there is a laminated varistor as shown in FIGS. 6 and 7 (see Japanese Patent Application No. 1-302496). The laminated varistor 30 embeds a pair of internal electrodes 33, 33 in a sintered body 32 formed by laminating a plurality of semiconductor ceramic layers 31, and sinters only one end surface 33a of each of the internal electrodes 33. Left and right end faces 32 of body 32
a, 32b are connected to the external electrodes 34, 34 formed. In the ceramic layer 31 between the internal electrodes 33, a pair of non-connected internal electrodes 35, 35 not connected to the external electrodes 34 are inserted and arranged. The non-connected internal electrodes 35 are sealed in the sintered body 32. Have been. The multilayer varistor 30 obtains a voltage non-linear characteristic by an electric barrier formed at an interface between the ceramic layer 31 and the internal electrodes 33 and the non-connection internal electrodes 35.

[0003]

By the way, as shown in FIG. 7, the laminated varistor 30 prints an Ag / Pd paste on a green sheet-shaped ceramic layer 31 to form an internal electrode 33 and a non-connected internal electrode 35. Are formed and sequentially laminated, and then integrally sintered to form a sintered body 32. However, the above-mentioned conventional multilayer varistor 3
0, the internal electrode 33 and the non-connected internal electrode 3
Since 5 acts as an obstacle, a force is applied to the joint surface between each of the electrodes 33 and 35 and the ceramic layer 31, and in some cases, the electrodes 33 and 35 may peel off. As a result, a voltage non-linear characteristic cannot be obtained in a portion where the separation has occurred, so that there is a problem that varistor voltage and capacitance are varied. Further, at the time of the above firing, the internal electrodes 33
Due to the shrinkage of the metal of the non-connection internal electrode 35 and the evaporation of the organic substance, mesh-like holes may be formed in the internal electrode 33 and the non-connection internal electrode 35 after sintering. As a result, the semiconductor crystal grows through this hole, and voltage non-linear characteristics cannot be obtained in this crystal portion. Therefore, there is a problem that the varistor voltage varies and a leakage current occurs as described above. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems. The present invention has been made to improve the scattering property of organic substances and the like at the time of firing, and to avoid the shrinkage of metals and the generation of holes due to the evaporation of organic substances. It is another object of the present invention to provide a multilayer varistor capable of reducing variations in varistor voltage and capacitance and reducing leakage current.

[0005]

SUMMARY OF THE INVENTION Accordingly, a first aspect of the present invention is to form external electrodes on both end surfaces of a sintered body obtained by laminating semiconductor ceramic layers and integrally sintering them, and a plurality of the sintered bodies are provided in the sintered body. In a laminated varistor in which internal electrodes are embedded and only one end face of each of the internal electrodes is alternately connected to the external electrodes, the internal electrodes are comb-shaped on a plane orthogonal to the thickness direction of the semiconductor ceramic layer. It is characterized by being formed in. The invention according to claim 2 is a laminated varistor in which a non-connected internal electrode not connected to the external electrode is embedded in a semiconductor ceramic layer between the internal electrodes, wherein the internal electrode is formed in a comb shape, The internal electrodes are arranged so as not to overlap in the thickness direction of the ceramic layer.

[0006]

According to the multilayer varistor according to the first aspect of the present invention, since the internal electrodes are formed in a comb shape, organic substances scattered from the ceramic layer during firing are released from gaps between the internal electrodes, so that the scatterability is reduced. And the peeling of the internal electrode can be prevented accordingly. As a result, voltage non-linear characteristics at the interface between the internal electrode and the ceramic layer can be secured, and variations in varistor voltage and capacitance can be reduced. According to the second aspect of the invention, when disposing the non-connected internal electrodes in the semiconductor ceramic layer between the internal electrodes, the internal electrodes are formed in a comb shape and the internal electrodes overlap in the thickness direction. Since no internal electrode is provided, only the internal electrode and the non-connected internal electrode overlap in the thickness direction, so that the overlap can be reduced as compared with the conventional structure. Therefore, holes due to shrinkage of internal electrodes and non-connected internal electrodes and evaporation of organic substances can be reduced, and the growth of crystals through the holes can be reduced accordingly. In this case as well, variations in varistor voltage can be reduced and leakage current can be reduced. .

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIGS. 1 to 3 are views for explaining a multilayer varistor according to an embodiment of the present invention. In the figure, reference numeral 1 denotes a laminated varistor of the present embodiment, which embeds a first internal electrode 3 and a second internal electrode 3 in a rectangular parallelepiped sintered body 2 and, at the same time, a left side of the sintered body 2. , Right end face 2
External electrodes 4 and 4 are formed on a and 2b.

The sintered body 2 is formed by laminating a plurality of semiconductor ceramic layers 5 and integrally sintering the laminated body. An interface between the first and second internal electrodes 3 and the ceramic layer 5 is formed. To obtain a voltage non-linear characteristic.

One end face 3a of each of the internal electrodes 3 is alternately exposed to the left and right end faces 2a, 2b of the sintered body 2, and this one end face 3a is electrically connected to the external electrode 4. Have been. Further, a portion other than the one end face 3 a of the internal electrode 3 is located inside the ceramic layer 5, thereby being embedded in the sintered body 2.

[0010] The first and second internal electrodes 3 are three strip-shaped electrode portions 3b extending in parallel with a predetermined gap a.
The electrode portions 3b are opposed to each other with the ceramic layer 5 interposed therebetween. Thereby, each of the internal electrodes 3
Has a comb shape on a plane orthogonal to the thickness direction of the ceramic layer 5.

Next, a method of manufacturing the multilayer varistor 1 of the present embodiment will be described. First, ZnO (97.9 mol%) is used as a main component, and CoCO ₃ (1.0 mol%), MnCO ₃
(0.5 mol%), Sb ₂ O ₃ (2.0 mol%), Bi ₂ O ₃ (0.5 mol%)
l%) in a molar ratio as described above, and 0.1% by weight of a glass powder composed of B ₂ O ₃ , SiO ₂ , PbO, and ZnO is added to the mixture to prepare a raw material powder. Further, an organic binder is mixed with the raw material powder to form a ceramic green sheet having a thickness of 10 μm by a reverse roller method, and the green sheet is cut into a rectangular shape to form a plurality of semiconductor ceramic layers 5. The uppermost and lowermost ceramic layers 5 are formed by laminating ten green sheets, and the central ceramic layer 5 is composed of only one green sheet.

Next, an organic vehicle is mixed with Pt metal powder to prepare an electrode paste, and this electrode paste is printed on the upper surface of the ceramic layer 5, thereby forming a comb-shaped electrode portion 3b having a band shape. First and second internal electrodes 3 are formed. In this case, only one end face 3a of each internal electrode 3 extends to the edge of the ceramic layer 5, and the other peripheral end face is formed inside.

Next, as shown in FIG. 1, the ceramic layers 5 and the internal electrodes 3 alternately overlap, and one end surfaces 3a of the internal electrodes 3 are alternately exposed at the left and right edges of the ceramic layer 5. The layers are laminated, and a pressure of ² t / cm ² is applied in a thickness direction of the layers to form a laminate, and the laminate is cut into a predetermined size.

Next, the above-mentioned laminate is exposed to air at 1050 to 1150
The sintered body 2 is obtained by firing at a temperature of 3 ° C. for 3 hours. Then, Ag: Pd = 7: on the left and right end faces 2a, 2b of the sintered body 2.
After applying an alloy paste having a weight ratio of 3 and baking, an external electrode 4 is formed. As a result, the multilayer varistor 1 of this embodiment is manufactured.

[0015]

[Table 1]

Table 1 shows the results of tests performed to confirm the effects of this embodiment. In this test, a multilayer varistor 1 was prepared by the manufacturing method described in the present embodiment, and its voltage-current characteristics, electrostatic capacity, and resistance value when 2 V was applied for 30 seconds were measured. For comparison, a similar measurement was performed on a conventional multilayer varistor having a rectangular internal electrode. As is clear from Table 1, in the case of the conventional sample, 3 CV of the varistor voltage is 8.5%, and the capacitance is 3%.
The CV is 10.2% and the resistance is 0.92 MΩ, and the characteristics vary. On the other hand, in the case of the sample of the present embodiment, the varistor voltage is 3 CV is 1.0%, and the capacitance is 3 CV is 3.10%, and the variation can be greatly reduced. Further, the resistance value is improved to 1.20 MΩ, and it can be seen that the leakage current can be reduced.

FIGS. 4 and 5 are views for explaining a laminated varistor according to an embodiment of the present invention. In the drawing, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding parts. In the multilayer varistor 10 of this embodiment, the first and second internal electrodes 11, 11 are embedded in the sintered body 2, and the external electrodes 4 are formed on both end faces 2 a, 2 b of the sintered body 2. The basic structure is substantially the same as that of the above embodiment.

A non-connection internal electrode 12 is provided in the ceramic layer 5 between the first and second internal electrodes 11.
Each end face of the non-connection internal electrode 12 is located inside the sintered body 2. Thus, the unconnected internal electrode 12 is sealed in the sintered body 2 without being electrically connected to the external electrode 4.

The first and second internal electrodes 11 are formed in four strip-shaped electrode portions 1 extending in parallel with a predetermined gap a.
1b. The electrode portions 11b are arranged so as not to overlap in the thickness direction of the ceramic layer 5.

Next, a method of manufacturing the multilayer varistor 10 of this embodiment will be described. The manufacturing method of the present embodiment is basically the same as the above-mentioned method. A raw material powder is prepared by adding glass powder to a ceramic material mainly composed of ZnO, and a ceramic green sheet having a thickness of 10 μm is formed from the raw material powder. Is formed, and the green sheet is cut into a rectangular shape to form a large number of semiconductor ceramic layers 5.

Next, an electrode paste is printed on the upper surface of each of the ceramic layers 5 to form first and second comb-shaped internal electrodes 11 and non-connected internal electrodes 12. This non-connection internal electrode 12 has a ceramic layer 5
It is formed so as to be located inside.

Next, as shown in FIG. 4, the ceramic layers 5 are sequentially stacked and laminated, and then pressed to form a laminate, and the laminate is cut into a predetermined size. Next, the laminate is fired in air at a temperature of 1050 to 1150 ° C. for 3 hours to form a sintered body 2. Thereafter, the external electrodes 4 are formed on the left and right end faces 2a, 2b of the sintered body 2 by baking. Thus, the multilayer varistor 10 of the present embodiment is manufactured.

[0023]

[Table 2]

Table 2 shows the results of tests conducted to confirm the effects of the present embodiment. In this test, the voltage-current characteristics, capacitance, and 4 V of the multilayer varistor 10 of the present embodiment were measured.
The resistance value when applying for 30 seconds was measured. For comparison, a similar test was performed on a conventional multilayer varistor in which the internal electrodes were rectangular and non-connected internal electrodes were provided. As is clear from Table 2, in the case of the conventional sample,
The varistor voltage 3CV is 9.5% and the capacitance 3CV is 9.
The resistance value is 60% and the resistance value is 1.50 MΩ, and the characteristics vary. On the other hand, in the case of the sample of the present embodiment, the varistor voltage 3CV is 1.0% and the capacitance 3CV.
Is 2.50%, and the variation can be greatly reduced. In addition, the resistance value is improved to 2.10 MΩ, which indicates that the leakage current has been reduced.

[0025]

As described above, according to the multilayer varistor according to the first aspect of the present invention, since the internal electrodes are formed in a comb shape, the scattering of organic substances can be improved, and variations in varistor voltage and capacitance can be reduced. There is an effect that can be reduced. According to the second aspect, when the non-connected internal electrodes are provided on the semiconductor ceramic layer between the internal electrodes, the comb-shaped internal electrodes are prevented from overlapping in the thickness direction. This has the effect of reducing voltage variations and reducing leakage current.

[Brief description of the drawings]

FIG. 1 is an exploded perspective view illustrating a laminated varistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of the multilayer varistor of the embodiment.

FIG. 3 is a perspective view of the multilayer varistor of the embodiment.

FIG. 4 is an exploded perspective view for explaining a multilayer varistor according to an embodiment of the present invention;

FIG. 5 is a sectional view of the multilayer varistor of the embodiment.

FIG. 6 is a sectional view showing a conventional multilayer varistor.

FIG. 7 is an exploded perspective view showing a conventional laminated varistor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1,10 Multilayer varistor 2 Sintered body 3,11 Internal electrode 3a One end face of internal electrode 4 External electrode 5 Ceramic layer 12 Unconnected internal electrode

Continued on the front page (72) Inventor Yasunobu Yoneda 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Inside Murata Manufacturing Co., Ltd. (72) Inventor Yukio Sakabe 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Murata Co., Ltd. (56) References JP-A-5-90062 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01C 7/02-7/22

Claims (2)

(57) [Claims] An external electrode is formed on both end surfaces of a sintered body obtained by laminating semiconductor ceramic layers and integrally sintering, a plurality of internal electrodes are buried in the sintered body, and a plurality of internal electrodes are formed. A multilayer varistor, wherein only one end face is alternately connected to the external electrode, wherein the internal electrode is formed in a comb shape on a plane orthogonal to a thickness direction of the semiconductor ceramic layer. 2. The semiconductor device according to claim 1, wherein a non-connected internal electrode that is not connected to the external electrode is embedded in the semiconductor ceramic layer between the internal electrodes, and the internal electrodes do not overlap in the thickness direction of the ceramic layer. A stacked varistor characterized by being arranged as follows.