JPH0214501A - Voltage nonlinear resistor - Google Patents

Voltage nonlinear resistor

Info

Publication number
JPH0214501A
JPH0214501A JP63162703A JP16270388A JPH0214501A JP H0214501 A JPH0214501 A JP H0214501A JP 63162703 A JP63162703 A JP 63162703A JP 16270388 A JP16270388 A JP 16270388A JP H0214501 A JPH0214501 A JP H0214501A
Authority
JP
Japan
Prior art keywords
layer
ineffective
added
green sheet
effective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63162703A
Other languages
Japanese (ja)
Inventor
Akihiro Takami
高見 昭宏
Susumu Matsushima
奨 松島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63162703A priority Critical patent/JPH0214501A/en
Publication of JPH0214501A publication Critical patent/JPH0214501A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To sufficiently display a function as a varistor even when a thickness of an ineffective layer is made equal to or lower than that of an effective layer and to enhance moistureproofness by a method wherein an insulator is used as the effective layer of a laminate-type voltage nonlinear resistor. CONSTITUTION:An additive such as Bi2O3, CoO, MnO or the like is added to ZnO; they are mixed and baked temporarily; after that, an organic binder, a dispersion medium and a plasticizer are added; a green sheet 1 for effective layer use is manufactured by a doctor blade method. Then, an additive in a very small quantity is added to a metal oxide to be used as an insulator; in addition, an organic binder, a dispersion medium and a plasticizer are added; a green sheet is manufactured by the doctor blade method; this green sheet is used as green sheets 2 for ineffective layer use. Internal electrodes 3, 4 are printed on the green sheet 1 for effective layer use; they are piled up; in addition, the green sheets 2 for ineffective layer use are piled up and pressure-bonded onto the upper part and lower part; this assembly is cut to a prescribed size and sintered. Then, this assembly displays a function of a varistor even when a thickness of the ineffective layers 2 in an uppermost layer and a lowermost layer is made equal to or lower that of the effective layer 1; no problem about moistureproofness arises.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は電子機器を誘導基、静電気などの異常電圧から
保護する電圧非直線抵抗器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a voltage nonlinear resistor that protects electronic equipment from abnormal voltages such as inductive groups and static electricity.

(従来の技術) 近年、電子機器の小型化が進み、その構成要素である電
子部品の小型化、特にプリント基板に直接組み込み可能
なチップ化された電子部品が市場から求められている。
(Prior Art) In recent years, electronic devices have become smaller and smaller, and the market is demanding smaller electronic components, especially chip-shaped electronic components that can be directly incorporated into printed circuit boards.

そして、コンデンサ、抵抗器、コイルなど基幹部品のチ
ップ化は急速に進み。
The use of chips for core components such as capacitors, resistors, and coils rapidly progressed.

1990年には電子部品のチップ化率は50%を超える
と予想されている。この電子部品のチップ化への要望は
保護部品である電圧非直線抵抗器に対しても強く、その
要望に応えるものとして積層型のセラミックバリスタ(
特開昭54−106894号公報)が提案されているが
、これは基本的には積層型のセラミックコンデンサと同
様の構成および製造方法からなる。すなわち酸化亜鉛(
Z n O)を主成分とし、これに酸化ビスマス(Bi
20.)、酸化コバルト(Coo)、酸化マンガン(M
 n O、) 、酸化鉛(pbo)などを加え、混合し
、乾燥したのち仮焼し、仮焼後の原料粉末に有機バイン
ダと分散媒。
It is predicted that by 1990, the chip rate of electronic components will exceed 50%. There is a strong demand for the chipping of electronic components, including voltage non-linear resistors, which are protective components, and in response to this demand, a multilayer ceramic varistor (
JP-A-54-106894) has been proposed, which basically has the same structure and manufacturing method as a multilayer ceramic capacitor. That is, zinc oxide (
ZnO) is the main component, and bismuth oxide (Bi
20. ), cobalt oxide (Coo), manganese oxide (M
n O, ), lead oxide (pbo), etc. are added, mixed, dried, and then calcined, and an organic binder and a dispersion medium are added to the calcined raw material powder.

可塑剤を加えて、スラリー状にし、ドクターブレード法
で10.〜200戸程度0厚さの均一な生シート膜を作
る。この生シート膜の上にスクリーン印刷法によって白
金などを内部電極として印刷する。
Add a plasticizer, make a slurry, and use the doctor blade method to process 10. ~Create a uniform raw sheet membrane with zero thickness for about 200 homes. Platinum or the like is printed as an internal electrode on this green sheet film by screen printing.

内部電極を印刷した生シートを所定の枚数積み重ね、さ
らに電極を印刷していない生シートを上下に積み重ね圧
着する。この後カッターで適当な形状に切断し、950
〜1300℃で1時間焼成したのち、内部電極を露出さ
せた両端面に銀電極を塗布し600℃で焼付けるもので
ある。その構造図を第2図(A)、(B)、(C)に示
す。同図において、11は酸化亜鉛(Z n O)を主
成分とする電圧非直線抵抗器の焼結体である。12.1
3は白金(Pt)などからなる内部電極であり、 14
.15は銀からなる外部電極である0次に、第2図(A
)を切断線B−B’c−c’に沿って切断し、矢印の方
向を視た断面図(B)、(C)を使って内部構造を説明
すると、積層焼結部において電圧非直線抵抗機能を発揮
する有効層16と発揮しない無効層17があることがわ
かる。そして無効層17は積層部の最上段と最下段に形
成されている。
A predetermined number of raw sheets with internal electrodes printed on them are stacked one on top of the other, and then raw sheets without electrodes printed on top of the other are stacked and pressed together. After this, cut it into a suitable shape with a cutter and
After baking at ~1300°C for 1 hour, silver electrodes are applied to both end faces with exposed internal electrodes and baked at 600°C. The structural diagrams are shown in FIGS. 2(A), (B), and (C). In the figure, 11 is a sintered body of a voltage nonlinear resistor whose main component is zinc oxide (ZnO). 12.1
3 is an internal electrode made of platinum (Pt) or the like; 14
.. 15 is an external electrode made of silver.
) is cut along the cutting line B-B'c-c' and the internal structure is explained using cross-sectional views (B) and (C) viewed in the direction of the arrow. It can be seen that there is an effective layer 16 that exhibits a resistance function and an ineffective layer 17 that does not. The ineffective layer 17 is formed at the top and bottom of the laminated portion.

(発明が解決しようとする課題) 一般に積層型の電圧非直線抵抗器(以下積層型セラミッ
クバリスタと略す)を作るとき、注意すべき点は、相対
向する内部電極の電極間距離、すなわち有効層の厚さt
工が対向する外部電極と内部電極との最短の電極間距離
(第2図(B)における内部電極と外部電極の電極間距
離tx)より小さいこと、好ましくはt2/11)1.
3である。何故なら、t□>1.なら電流は有効層の部
分を流れないことになり、バリスタとして異常電圧を十
分に吸収し、抑制することができない。このため、第2
図に示すように外部電極が端面部から開平面部にまわり
込んでいる場合(プリント基板に直接半田付けする場合
は外部電極は端面部から両手面部にまわり込んでいる)
、無効層の厚さを大きくすることが必要であり、小型化
することができない。さらに焼結体として、酸化亜鉛(
ZnO)に酸化ビスマス(Bi20.)や酸化鉛(pb
o)を加えているため、焼結過程にBiやpbが飛散す
ることにより、焼結体内部に多くの気孔を含むことにな
り、耐湿性を考えた場合、無効層の厚さは必然的に大き
くなる。通常無効層の厚さは有効層の厚さの3〜5倍に
なっている。
(Problem to be Solved by the Invention) Generally, when making a multilayer voltage nonlinear resistor (hereinafter abbreviated as a multilayer ceramic varistor), one thing to be careful of is the distance between the opposing internal electrodes, that is, the effective layer thickness t
(preferably t2/11)1.
It is 3. This is because t□>1. In this case, current will not flow through the effective layer, and the varistor will not be able to sufficiently absorb and suppress abnormal voltage. For this reason, the second
As shown in the figure, when the external electrode goes around from the end face to the open plane part (when soldering directly to the printed circuit board, the external electrode goes around from the end face to the open plane part)
, it is necessary to increase the thickness of the ineffective layer, and miniaturization is not possible. Furthermore, as a sintered body, zinc oxide (
ZnO), bismuth oxide (Bi20.) and lead oxide (pb
o), the sintered body contains many pores due to the scattering of Bi and PB during the sintering process, and when moisture resistance is considered, the thickness of the ineffective layer is inevitably increased. becomes larger. Usually, the thickness of the ineffective layer is 3 to 5 times the thickness of the effective layer.

本発明の目的は、従来の欠点を解消し、無効層の厚さを
有効層と同等、またはそれ以下にしてもバリスタとして
の機能は十分に発揮し、耐湿性も問題ない積層型セラミ
ックバリスタを提供することである。
The purpose of the present invention is to eliminate the conventional drawbacks, and to provide a multilayer ceramic varistor that can fully function as a varistor even when the thickness of the ineffective layer is equal to or less than that of the effective layer, and has no moisture resistance problems. It is to provide.

(課題を解決するための手段) 本発明の電圧非直線抵抗器は、複数の内部電極と電圧非
直線抵抗焼結体と絶縁体とが積層構造になっており、端
面部に内部電極と電気的に接続している外部電極を形成
してなる電圧非直線抵抗器において、積層構造の少なく
とも最上段層と最下段層が絶縁体である構造である。
(Means for Solving the Problems) The voltage nonlinear resistor of the present invention has a laminated structure of a plurality of internal electrodes, a voltage nonlinear resistance sintered body, and an insulator, and has an internal electrode and an electrical In the voltage nonlinear resistor formed by forming external electrodes that are connected to each other, at least the uppermost layer and the lowermost layer of the laminated structure are insulators.

(作 用) 上記構成により、最上段層と最下段層の無効層の厚さを
有効層の厚さと同等もしくはそれ以下にしても、バリス
タ機能は十分に発揮し、耐湿性にも問題なく、小型化と
いう積層型セラミックバリスタの使命を十分に発揮する
ことができる。
(Function) With the above configuration, even if the thickness of the ineffective layer of the uppermost layer and the lowermost layer is equal to or less than the thickness of the effective layer, the varistor function is fully exhibited, and there is no problem in moisture resistance. The multilayer ceramic varistor's mission of miniaturization can be fully demonstrated.

(実施例) 本発明の実施例を第1図(A)、(B)、(C)に基づ
いて説明する。
(Example) An example of the present invention will be described based on FIGS. 1(A), (B), and (C).

第1実施例と第2実施例の基本的な製造方法および構造
は共通するので、それを先に説明する。
Since the basic manufacturing method and structure of the first embodiment and the second embodiment are the same, they will be explained first.

本発明では、まず焼結後バリスタ特性を有する有効層用
の生シートを準備する。これは酸化亜鉛(ZnO)に酸
化ビスマス(Bit03)r酸化コバルト(CaO)、
酸化マンガン(M n O、)などの添加物を加えて混
合し、仮焼したのちに有機バインダと分散媒、可塑剤を
加えて、ドクターブレード法で生シートを作る0次に、
無効層用の生シートを作るが、これは絶縁体となる金属
酸化物に微量添加物を加え、さらに有機バインダと分散
媒、可塑剤を加えてドクターブレード法で生シートをつ
くり、無効層用生シートにする。そして、有効層用生シ
ートとに内部電極を印刷し、これを積み重ね、さらに無
効層用生シートを上下に積み重ねて圧着したのち、所定
の大きさに切断し、焼結する。これに外部電極に付与す
る製造方法を用いる。その構造を第1図(A)、(B)
、(C)に示す。同図において、1は有効層を形成する
焼結体、2は無効層を形成する絶縁体、3,4は内部電
極であり、5゜6は外部電極である。
In the present invention, first, a raw sheet for an effective layer having varistor properties after sintering is prepared. This is zinc oxide (ZnO), bismuth oxide (Bit03), cobalt oxide (CaO),
Additives such as manganese oxide (MnO) are added and mixed, and after calcining, an organic binder, a dispersion medium, and a plasticizer are added, and a green sheet is made using the doctor blade method.
A green sheet for the ineffective layer is made by adding a small amount of additives to the metal oxide that will serve as the insulator, and then adding an organic binder, a dispersion medium, and a plasticizer to create a green sheet using the doctor blade method. Make raw sheets. Then, internal electrodes are printed on the raw sheets for the effective layer and these are stacked, and the raw sheets for the ineffective layer are stacked one above the other and pressed together, and then cut into a predetermined size and sintered. For this purpose, a manufacturing method is used in which external electrodes are provided. The structure is shown in Figure 1 (A) and (B).
, shown in (C). In the figure, 1 is a sintered body forming an effective layer, 2 is an insulator forming an ineffective layer, 3 and 4 are internal electrodes, and 5.6 is an external electrode.

(実施例1) まず有効層用生シートを作る。原料として酸化亜鉛(Z
nO)に酸化ビスマス(Bi、O−)、酸化コバルト(
Cod)、酸化マンガン(M n Ot )−酸化アン
チモン(Sb20s)+酸化珪素(s x O2) を
酸化クロム(CrzOi)をそれぞれ0.1〜5mo1
%加え、純水を用いてボールミルで24時間混合する。
(Example 1) First, a raw sheet for an effective layer is prepared. Zinc oxide (Z
nO), bismuth oxide (Bi, O-), cobalt oxide (
Cod), manganese oxide (MnOt) - antimony oxide (Sb20s) + silicon oxide (s
% and mixed for 24 hours in a ball mill using pure water.

次に乾燥し、乾燥物を乾式粉砕し、アルミナルツボに入
れて、800〜950℃で2時間仮焼する。仮焼後、さ
らに再度粉砕し、有機バインダとともに溶媒中に分散さ
せ、スラリー状とする。これをドクターブレード法によ
って50.程度の厚さの均一な生シートにする。この生
シートを1100mmX80の矩形に打ち抜き、この上
にスクリーン印刷法によって白金(Pt)を内部電極と
してペースト状にして、所定の大きさにスクリーン印刷
する0次に無効層用生シートを作る。原料として7. 
nz S iO4粉末に酸化アンチモン(sb、○、)
、酸化珪素(Sio、)をそれぞれ微量添加し、有機バ
インダとともに溶媒中に分散させ、スラリー状とする。
Next, it is dried, and the dried product is dry-pulverized, placed in an alumina crucible, and calcined at 800 to 950°C for 2 hours. After calcining, it is further ground again and dispersed in a solvent together with an organic binder to form a slurry. This was done by the doctor blade method for 50 minutes. Make a uniform raw sheet with a certain thickness. This raw sheet is punched out into a rectangle of 1100 mm x 80 mm, and platinum (Pt) is pasted onto this as an internal electrode by screen printing to create a zero-order invalid layer raw sheet that is screen printed to a predetermined size. 7. As a raw material.
Antimony oxide (sb,○,) in nz SiO4 powder
, silicon oxide (Sio, ) are added in small amounts, and dispersed together with an organic binder in a solvent to form a slurry.

これをドクターブレード法によって50戸程度の厚さの
均一な生シートにする。この生シートを10100mX
80の矩形に打ち抜き、無効層用生シートにする6次に
内部電極を印刷した有効層用生シートを10枚積み重ね
、さらに無効層用生シートを上下に積み重ね圧着する。
This is made into a uniform green sheet with a thickness of about 50 doors using the doctor blade method. This raw sheet is 10100mX
80 rectangles are punched out to form a raw sheet for an ineffective layer. 6. Next, 10 raw sheets for an effective layer on which internal electrodes have been printed are stacked, and further raw sheets for an ineffective layer are stacked one above the other and pressed together.

その後、カッターで切断し、1250℃で1時間焼成す
る0次に内部電極を露出させた両端面にAg−Pd電極
を塗布し900℃で焼付ける。無効層の焼結組織は緻密
であり、この素子の耐湿特性を調べるため、プレッシャ
ークツカーテスト(121℃、2気圧中に放置)を実施
した結果、100時間放置後でもバリスタ電圧の変化率
は一2%以下であった。一方、比較のため、従来技術の
方法で作製した素子は一25%の変化を示し、実施例1
が方法の有効であることを確認した。
Thereafter, it is cut with a cutter and baked at 1250°C for 1 hour.Ag-Pd electrodes are applied to both end faces with exposed internal electrodes and baked at 900°C. The sintered structure of the invalid layer is dense, and in order to investigate the moisture resistance properties of this element, we conducted a pressure couture test (leaving it at 121°C in 2 atm) and found that the rate of change in varistor voltage remained the same even after leaving it for 100 hours. It was less than 12%. On the other hand, for comparison, the device fabricated by the conventional method showed a change of -25%, and Example 1
The validity of the method was confirmed.

(実施例2) 次に絶縁物の原料として、AJ、03とMgOを用いた
場合について説明する。有効層生シートの作成法は実施
例1と同じである。無効層用生シートはAJ20.の場
合、AJ、O,の粉末に酸化硼素(BZ O−) 、酸
化珪素(SiO2)をそれぞれ微量添加し、有機バイン
ダとともに溶媒中に分散させ、スラリー状にし、ドクタ
ーブレード法によって50−程度の厚さの均一な生シー
トにする。積層以降は実施例1と同じである。但し、焼
成温度は1350℃である。
(Example 2) Next, a case will be described in which AJ, 03 and MgO are used as raw materials for the insulator. The method for preparing the effective layer raw sheet is the same as in Example 1. The raw sheet for the ineffective layer is AJ20. In the case of AJ, O, a small amount of boron oxide (BZ O-) and silicon oxide (SiO2) are added to the powder, dispersed in a solvent together with an organic binder, made into a slurry, and made into a slurry using a doctor blade method. Make a raw sheet of uniform thickness. The steps after lamination are the same as in Example 1. However, the firing temperature is 1350°C.

一方MgOの場合、無効層用生シートはMgO粉末に酸
化硼素(3,03)、酸化珪素(Sin、)をそれぞれ
微量添加し、Al1203の場合と同様の方法で生シー
トを作る。積層以降は実施例1と同じである。但し、焼
成温度は1300℃である。AI!20.の場合も、M
gOの場合も無効層の焼結組織は緻密であった。この素
子の耐湿特性を調べるため、プレッシャークツカーテス
ト(121℃、2気圧中に放置)を実施した結果、10
0時間放置後でもバリスタ電圧の変化率はAJ20.の
場合で一1%。
On the other hand, in the case of MgO, a green sheet for the invalid layer is prepared by adding trace amounts of boron oxide (3,03) and silicon oxide (Sin, ) to MgO powder in the same manner as in the case of Al1203. The steps after lamination are the same as in Example 1. However, the firing temperature is 1300°C. AI! 20. Also in the case of M
In the case of gO, the sintered structure of the invalid layer was also dense. In order to investigate the moisture resistance properties of this element, we conducted a pressure couture test (left at 121°C and 2 atm) and found that 10
Even after leaving it for 0 hours, the rate of change in varistor voltage is AJ20. 11% in the case of

MgOの場合で−2,5%であった。In the case of MgO, it was -2.5%.

一方比較のため、従来技術の方法で作成した素子は一2
5%の変化を示し、実施例2の場合も有効であった。
On the other hand, for comparison, the device made by the conventional method is 12
It showed a change of 5%, and the case of Example 2 was also effective.

(発明の効果) 本発明によれば、積層型の電圧非直線抵抗器の無効層に
絶縁体を用いることにより、従来例より小型で、しかも
耐湿特性に優れたものになり、電子機器の小型化に有効
な部品として、その実用的価値は大なるものがある。
(Effects of the Invention) According to the present invention, by using an insulator for the ineffective layer of a multilayer voltage nonlinear resistor, it becomes smaller than the conventional example and has excellent moisture resistance, which makes it possible to reduce the size of electronic equipment. It has great practical value as a component that is effective for development.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(A)は本発明の一実施例における電圧非直線抵
抗器の斜視図、第1図CB)および(C)は同断面図、
第2図(A)は従来の電圧非直線抵抗器の斜視図、第2
図(B)および(C)は同断面図である61 ・・・焼
結体、 2・・・絶縁体、3.4 ・・・内部電極、5
,6・・・外部電極。 特許出願人 松下電器産業株式会社 箪 図 箪 図
FIG. 1(A) is a perspective view of a voltage nonlinear resistor in one embodiment of the present invention, FIG. 1 CB) and (C) are the same cross-sectional views,
Figure 2 (A) is a perspective view of a conventional voltage nonlinear resistor;
Figures (B) and (C) are the same cross-sectional views. 61... Sintered body, 2... Insulator, 3.4... Internal electrode, 5
, 6... external electrode. Patent applicant Matsushita Electric Industrial Co., Ltd. Tanzu Tanzu

Claims (1)

【特許請求の範囲】[Claims]  複数の内部電極と電圧非直線抵抗焼結体と絶縁体とが
積層構造になっており、端面部に、前記内部電極と電気
的に接続している外部電極を形成してなる電圧非直線抵
抗器において、前記積層構造の少なくとも最上段層と最
下段層が、前記絶縁体であることを特徴とする電圧非直
線抵抗器。
A plurality of internal electrodes, a voltage nonlinear resistance sintered body, and an insulator have a laminated structure, and an external electrode electrically connected to the internal electrodes is formed on the end face. A voltage nonlinear resistor, wherein at least the uppermost layer and the lowermost layer of the laminated structure are the insulator.
JP63162703A 1988-07-01 1988-07-01 Voltage nonlinear resistor Pending JPH0214501A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63162703A JPH0214501A (en) 1988-07-01 1988-07-01 Voltage nonlinear resistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63162703A JPH0214501A (en) 1988-07-01 1988-07-01 Voltage nonlinear resistor

Publications (1)

Publication Number Publication Date
JPH0214501A true JPH0214501A (en) 1990-01-18

Family

ID=15759696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63162703A Pending JPH0214501A (en) 1988-07-01 1988-07-01 Voltage nonlinear resistor

Country Status (1)

Country Link
JP (1) JPH0214501A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006106717A1 (en) * 2005-04-01 2006-10-12 Matsushita Electric Industrial Co., Ltd. Varistor and electronic component module using same
JP2008182280A (en) * 2008-04-21 2008-08-07 Tdk Corp Laminated chip varistor
JP2010073759A (en) * 2008-09-16 2010-04-02 Tdk Corp Laminated chip varistor and electronic component
WO2013175795A1 (en) * 2012-05-25 2013-11-28 パナソニック株式会社 Varistor and method of manufacturing same
CN106782956A (en) * 2016-09-29 2017-05-31 立昌先进科技股份有限公司 A kind of method for preparing MLV and by its obtained piezo-resistance
EP3300087A1 (en) * 2016-09-26 2018-03-28 SFI Electronics Technology Inc. Multilayer varistor and process for producing the same
JP2020150012A (en) * 2019-03-11 2020-09-17 パナソニックIpマネジメント株式会社 Multilayer varistor

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5823921A (en) * 1981-07-30 1983-02-12 オフイシ−ネ・サビオ・エス・ピ−・エイ Paraffin coater for double twister
JPS6057905A (en) * 1983-09-09 1985-04-03 マルコン電子株式会社 Laminated voltage nonlinear resistor
JPS6257905A (en) * 1985-08-02 1987-03-13 Asahi Chem Ind Co Ltd Spinneret

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5823921A (en) * 1981-07-30 1983-02-12 オフイシ−ネ・サビオ・エス・ピ−・エイ Paraffin coater for double twister
JPS6057905A (en) * 1983-09-09 1985-04-03 マルコン電子株式会社 Laminated voltage nonlinear resistor
JPS6257905A (en) * 1985-08-02 1987-03-13 Asahi Chem Ind Co Ltd Spinneret

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006106717A1 (en) * 2005-04-01 2006-10-12 Matsushita Electric Industrial Co., Ltd. Varistor and electronic component module using same
JPWO2006106717A1 (en) * 2005-04-01 2008-09-11 松下電器産業株式会社 Varistor and electronic component module using the same
US7940155B2 (en) 2005-04-01 2011-05-10 Panasonic Corporation Varistor and electronic component module using same
JP4720825B2 (en) * 2005-04-01 2011-07-13 パナソニック株式会社 Barista
JP2008182280A (en) * 2008-04-21 2008-08-07 Tdk Corp Laminated chip varistor
JP2010073759A (en) * 2008-09-16 2010-04-02 Tdk Corp Laminated chip varistor and electronic component
WO2013175795A1 (en) * 2012-05-25 2013-11-28 パナソニック株式会社 Varistor and method of manufacturing same
EP3300087A1 (en) * 2016-09-26 2018-03-28 SFI Electronics Technology Inc. Multilayer varistor and process for producing the same
JP2018056559A (en) * 2016-09-26 2018-04-05 立昌先進科技股▲分▼有限公司 Multilayer varistor and method for producing the same
CN106782956A (en) * 2016-09-29 2017-05-31 立昌先进科技股份有限公司 A kind of method for preparing MLV and by its obtained piezo-resistance
JP2020150012A (en) * 2019-03-11 2020-09-17 パナソニックIpマネジメント株式会社 Multilayer varistor

Similar Documents

Publication Publication Date Title
JP2556151B2 (en) Stacked Varistor
KR20060046265A (en) Multilayer chip varistor
KR101013017B1 (en) varistor
JP2976046B2 (en) Chip varistor
JPH03173402A (en) Chip varistor
JPH0214501A (en) Voltage nonlinear resistor
JP3008567B2 (en) Chip type varistor
US6362720B1 (en) Chip type varistor and method of manufacturing the same
JP3832071B2 (en) Multilayer varistor
JPH10199709A (en) Multilayer type varistor
JP2976250B2 (en) Manufacturing method of multilayer varistor
JPH0142612B2 (en)
JP2666605B2 (en) Stacked varistor
JPS62282411A (en) Voltage-dependent nonlinear resistor
JPH0536503A (en) Laminated varistor
JP3186199B2 (en) Stacked varistor
JP2985444B2 (en) Stacked varistor
JPH056806A (en) Chip varistor
JPH08153606A (en) Laminated varistor
JPH0613206A (en) Laminated varistor
JP3000662B2 (en) Multilayer varistor
JPH05283209A (en) Laminated varistor
JP3245933B2 (en) Resistor
JPH03239303A (en) Laminated varistor
JP2621681B2 (en) Stacked varistor