JPH056806A - Chip varistor - Google Patents

Abstract

PURPOSE:To provide a chip varistor which prevents the growth of a semiconductor crystal at the time of baking for reducing the variations in varistor voltage and for reducing a lead current that prevents an electric field from concentrating on an end of an electrode for incresing a surge resistance. CONSTITUTION:In a ceramic body 2 which is fabricated by laminating the plurality of semiconductor ceramic layers 7a-7c, a first and a second internal electrode 3, 4 are so buried that they may not overlap each other in the thickness direction 't' of the ceramic layer 7a. Only one end 3a, 4a of each of the first and the second internal electrode 3, 4 is connected to an external electrode 6 which is formed on left and right end faces 2a, 2b of the ceramic body 2. Meanwhile, an unconnected internal electrode 5 not connected to the external electrode 6 is buried in the ceramic body 2 so that it may overlap the first and the second internal electrode 3, 4 through the semiconductor ceramic layer 7a. The first and the second internal electrode 3, 4 and the unconnected internal electrode 5 are installed on different planes. Thus, a chip varistor 1 is fabricated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip varistor functioning as a voltage non-linear resistor, and in particular, it reduces variations in varistor voltage when varistor characteristics are obtained at the interface between an internal electrode and a semiconductor ceramic layer. The present invention relates to a structure capable of reducing leakage current, avoiding concentration of an electric field at the electrode end portion, and improving surge withstand capability.

[0002]

2. Description of the Related Art Generally, a voltage non-linear resistor (hereinafter referred to as a varistor) whose resistance value changes non-linearly according to an applied voltage is widely used as a surge absorbing element and a voltage stabilizing element. The electrical characteristics of such a varistor are I
_{/ I = (V / V i} ) is represented by ^a. The above I is the current flowing through the element, V is the applied voltage, V _i is the voltage between the terminals when the current iA flows through the device, is referred to as a varistor voltage V _1mA takes a value of usually 1 mA. Further, a is a voltage nonlinear coefficient, which shows how the voltage is controlled when the varistor is incorporated into an electric circuit. The larger the value of a, the better the voltage control. Further, in recent years, in the field of electronic devices such as communication devices, miniaturization, IC integration of electronic components, and integration have been advanced, and accordingly, miniaturization of varistor in order to improve mounting density, or The demand for lower voltage is increasing. In order to meet such requirements, a laminated varistor has been proposed in place of the disk type (see, for example, Japanese Patent Publication No. 58-23921).
.. According to this laminated varistor, since it is possible to reduce the number of grain boundaries between the internal electrodes without growing crystal grains of the semiconductor ceramic layer enormously, it is possible to reduce the operating voltage and reduce the size. It can also be adapted. Further, as an improved type of the laminated varistor disclosed in the above publication, conventionally,
A laminated varistor as shown in FIG. 5 has been proposed (see Japanese Patent Application No. 1-302496). This laminated varistor 20 has a pair of internal electrodes 22, 23 embedded in a sintered body 21 formed by laminating a large number of semiconductor ceramic layers, and only one end faces 22a, 23a of each internal electrode 22, 23 are embedded. The sintered body 21 is connected to the external electrodes 24 and 25 formed on the left and right end faces 21a and 21b. In the ceramic layer 28 between the internal electrodes 22 and 23, the unconnected internal electrode 2 that is not connected to the external electrodes 24 and 25 is used.
7 is embedded, and each non-connection internal electrode 27 is sealed in the sintered body 21. In this laminated varistor 20, the internal electrodes 22 and 23 and the non-connected internal electrode 27 are used.
The varistor characteristic is obtained at the interface between the semiconductor ceramic layer 28 and the semiconductor ceramic layer 28. In this laminated varistor 20, the number of grain boundaries in the thickness direction of the ceramic layer 28 sandwiched between the internal electrodes 22 and 23 and the non-connected internal electrode 27 is set to 2 or less. The voltage can be reduced and the surge resistance can be improved.

[0003]

By the way, in the above-mentioned conventional laminated varistor, since each internal electrode and unconnected internal electrode are formed on the ceramic green sheet, they are integrally sintered to obtain a sintered body. During the firing, the internal electrodes after firing are contracted due to the contraction of metals such as the above internal electrodes and the evaporation of organic substances.
A mesh-like hole is likely to be formed in the unconnected internal electrode. As a result, there is a problem that a semiconductor crystal grows through this hole, the varistor voltage varies, and the leakage current increases.

The present invention has been made to solve the above-mentioned conventional problems, and provides a chip varistor capable of suppressing the growth of semiconductor crystals during firing to reduce variations in varistor voltage and leakage current. The purpose is to do.

[0005]

Means for Solving the Problems Here, the inventors of the present invention have examined the cause of the formation of mesh holes in the internal electrodes and the non-connected internal electrodes during the above firing, and found that each electrode is formed in the thickness direction of the ceramic layer. It was considered that the overlapping points facilitated formation of holes due to evaporation of organic substances. From this, we have come to the idea that it is effective to arrange the internal electrodes and the non-connected internal electrodes so that they do not overlap in the thickness direction as much as possible in order to suppress the generation of the holes. Therefore, the present inventors have devised a chip varistor 10 as shown in FIGS. 4 (a) and 4 (b). Chip varistor 1 shown in Fig. 4 (a)
0 means that the first and second internal electrodes 12 and 13 are embedded in the ceramic sintered body 11 on the same plane so as not to overlap in the thickness direction t of the ceramic layer 14a, and the first and second internal electrodes 12 and 13 are embedded. 2 One end surface 1 of the internal electrodes 12 and 13
Only 2a and 13a are left and right end faces 11 of the sintered body 11.
It is configured to be connected to the external electrodes 15 and 15 formed on a and 11b. A non-connecting internal electrode 16 that is not connected to the external electrode 15 is embedded in the sintered body 11, and the non-connecting internal electrode 16 is the ceramic layer 1 described above.
The first and second internal electrodes 12, 13 are overlapped with each other with 4a interposed therebetween. In the structure shown in FIG. 4 (b), the first and second internal electrodes 12 and 13 in the sintered body 11 do not overlap in the thickness direction t of the ceramic layer 14a and are arranged on different planes. The non-connecting internal electrode 17 is provided on the same plane as the first internal electrode 12, and the non-connecting internal electrode 1 is also provided on the same plane as the second internal electrode 13.
8 are arranged. According to each chip varistor 10 having the above structure, the thickness direction t of the ceramics layer 14a is t.
In each of the internal electrodes 12 and 13 and the non-connected internal electrodes 16 to
Since only 18 overlap, the number of overlaps can be reduced as compared with the conventional structure. As a result, it is possible to suppress the generation of holes during firing, reduce the growth of the semiconductor crystal to that extent, reduce the varistor voltage variation, and reduce the leakage current.

By the way, one chip varistor having the above structure is used.
At 0, since the internal electrodes 12 and 13 are located on the same plane, or the internal electrodes 12 and 13 and the unconnected internal electrodes 17 and 18 are located on the same plane, an electric field is generated at the ends of these electrodes. It is easy to concentrate, and in some cases, there is a risk of destruction when a surge current is applied, and improvement in this respect is required.

Therefore, according to the present invention, the first and second internal electrodes are embedded in a sintered body formed by laminating a plurality of semiconductor ceramic layers so as not to overlap in the thickness direction of the ceramic layers, and the first internal electrodes are embedded. , Connecting only one end surface of the second internal electrode to the external electrodes formed on the left and right end surfaces of the sintered body, and at least one unconnected internal electrode not connected to the external electrode in the sintered body, The chip varistor is characterized in that it is embedded so as to overlap the first and second internal electrodes with the semiconductor ceramic layer interposed therebetween, and the first and second internal electrodes and the unconnected internal electrode are arranged on different planes. .. Here, when disposing the non-connecting internal electrodes, one non-connecting internal electrode may be disposed so as to overlap with both the first and second internal electrodes, or each of the two non-connecting internal electrodes may be arranged. May be arranged so as to overlap with each of the first and second internal electrodes. Further, it is desirable that three or more of the internal electrodes and the non-connected internal electrodes do not overlap each other in the thickness direction. This is because if it exceeds this, the effect of suppressing the generation of holes decreases.

[0008]

According to the chip varistor of the present invention, the first and second internal electrodes are arranged in the sintered body so as not to overlap each other in the thickness direction, and the first and second internal electrodes and the semiconductor ceramic layer are formed. Since the non-connection internal electrodes are arranged so as to overlap with each other, only the internal electrodes and the non-connection internal electrodes overlap in the thickness direction, and the number of overlaps can be reduced as compared with the conventional structure. Therefore, the generation of holes during firing can be suppressed, and the growth of the semiconductor crystal can be reduced accordingly. As a result, variation in varistor voltage can be reduced and
Leakage current can be reduced. Further, in the present invention,
Since the second internal electrode and the non-connected internal electrode are arranged on different planes, it is possible to avoid local concentration of the electric field at the electrode end, improve surge withstand by that much, and ensure breakdown due to surge current intrusion. It can be prevented.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 1 and 2 are views for explaining a chip varistor according to an embodiment of the present invention. In the figure, reference numeral 1 is a chip varistor of this embodiment, in which a first rectangular parallelepiped ceramic sintered body 2 is embedded with a first internal electrode 3 and a second internal electrode 4 and a non-connected internal electrode 5 is embedded. The external electrodes 6 and 6 are formed on the left and right end surfaces 2a and 2b of the sintered body 2.

The sintered body 2 is formed by laminating a large number of semiconductor ceramic layers 7a to 7c and integrally sintering them, and the first and second internal electrodes 3, 4 of the sintered body 2 are formed. The portion sandwiched between the non-connecting internal electrode 5 and the non-connecting internal electrode 5 is a ceramics layer 7a that exhibits voltage nonlinearity. The upper and lower parts of the sintered body 2 other than the ceramics layer 7a are ceramics layers 7b and 7c as dummy.

The end surfaces 3a and 4a of the first and second internal electrodes 3 and 4 are respectively the left and right end surfaces 2a and 2 of the sintered body 2.
It is exposed at b and is connected to the external electrode 6, and the remaining end faces of the internal electrodes 3 and 4 are enclosed in the sintered body 2. Furthermore, each end face of the non-connected internal electrode 5 is located inside the sintered body 2, so that the non-connected internal electrode 5 is not electrically connected to the external electrode 6 and is not inside the sintered body 2. It is enclosed in.

Then, the first and second internal electrodes 3, 4
Are located at both ends of the sintered body 2 so as not to overlap in the thickness direction t of the ceramic layers 7a to 7c. The first and second internal electrodes 2 and 3 are arranged on different planes, the first internal electrode 3 is located above the sintered body 2, and the second internal electrode 4 is located below. .. Further, the non-connecting internal electrode 5 is arranged in the ceramic layer 7a between the first and second internal electrodes 3, 4 so that the non-connecting internal electrode 5 is different from each of the internal electrodes 2, 3. It is located on a plane. Further, both ends of the unconnected internal electrode 5 overlap with the first and second internal electrodes 3 and 4 with the ceramics layer 7a sandwiched therebetween, and the opposing parts of these are varistor characteristic parts.

Next, a method of manufacturing the chip varistor 1 of this embodiment will be described. First, ZnO, Bi ₂ O ₃ , Co
_{2 O 3, MnO, Sb 2} O 3, and Cr ₂ O _3, respectively 97.9 mol%, 0.5mol%, 0.5mol %, 0.5mol%, 0.3mol
%, And 0.3 mol% are weighed so as to have a composition ratio, ion-exchanged water is added to this, and mixed by a ball mill for 24 hours. Next, this is filtered, dried, calcined at 800 ° C for 2 hours, and then pulverized again to prepare raw material powder. Further, an organic binder is mixed with the raw material powder to form a ceramic green sheet having a thickness of 20 μm by a reverse roller method, and the green sheet is cut into a rectangular shape to form a large number of ceramic layers 7a to 7c. Next, an electrode paste was prepared by mixing a metal powder of Pt with an organic vehicle.
As shown in, the paste is printed on the upper surface of the one ceramic layer 7a to form the first internal electrode 3. In this case, only one end surface 3a of the internal electrode 3 is located at the left end edge of the ceramic layer 7a, and the remaining end surface is located inside the ceramic layer 7a. Further, the above-mentioned paste is printed on the upper surface of the other ceramic layer 7a to form the unconnected internal electrode 5. In this case, all the end faces are formed so as to be located inside the peripheral edge of the ceramic layer 7a. Further, the paste is printed on the upper surface of one dummy ceramic layer 7c to form the second internal electrode 4. In this case as well, similarly to the above, one end surface 4a of the internal electrode 4 is formed.
Only the ceramic layer 7a is located at the right edge of the ceramic layer 7a, and the remaining end surface is located inside the ceramic layer 7c. Then, as shown in FIG. 2, the ceramic layer 7a having the non-connecting internal electrode 5 formed thereon is stacked on the lower surface of the ceramic layer 7a having the first internal electrode 3 formed thereon, and the second internal electrode 4 is formed on the lower surface thereof. Ceramics layer 7c in which
And further stacking a large number of dummy ceramic layers 7b and 7c on the upper and lower parts thereof respectively, and applying a pressure of ² t / cm ^{2 in} the thickness direction of the layers to form a laminated body,
The laminated body is cut into a predetermined size. And the said laminated body is baked at 1200 degreeC x 2 hours in air, and the sintered compact 2 is obtained. At the time of this firing, since the electrodes overlap each other in the thickness direction t of the sintered body 2, the organic substances are easily evaporated, and the pores (pores) generated at the interface are reduced accordingly. Finally, each internal electrode 3 of the sintered body 2 is
Left and right end faces 2a, 2 of which one end faces 3a, 4a of 4 are exposed
After coating Ag paste on b, it is baked at 700 ° C. for 10 minutes to form the external electrode 6. As a result, the chip varistor 1 of this embodiment is manufactured.

As described above, according to this embodiment, the first and second
Since the internal electrodes 3 and 4 are arranged so as not to overlap in the thickness direction t, and the unconnected internal electrode 5 is arranged so as to overlap the internal electrodes 3 and 4 with the semiconductor ceramic layer 7a interposed therebetween, The number of electrodes overlapped in the direction t can be reduced to two, and the generation of mesh holes during firing can be reduced. As a result, it is possible to suppress the growth of the semiconductor crystal, reduce variations in varistor voltage, and reduce leakage current. Further, in the present embodiment, since the first and second internal electrodes 3 and 4 and the non-connected internal electrode 5 are arranged on different planes, the electric field concentrates on the ends of the electrodes when a surge current invades. Can be avoided and the surge withstand capability can be improved accordingly.

FIG. 3 is a diagram for explaining another example of the above embodiment. In the figure, the same reference numerals as in FIG. 1 indicate the same or corresponding parts. In this chip varistor 1 ′, the first and second internal electrodes 3 and 4 are arranged in the sintered body 2 so as not to overlap in the thickness direction t of the ceramic layer 7 a and on different planes. Two unconnected internal electrodes 8 and 9 are arranged in the ceramic layer 7a between the second internal electrodes 3 and 4, and each unconnected internal electrode 8 and 9 is arranged on a different plane. The non-connecting internal electrode 8 overlaps with the first internal electrode 3 via the ceramics layer 7a, and the non-connecting internal electrode 9 overlaps with the second internal electrode 4 via the ceramics layer 7a. Also in this example, since the number of electrodes overlapped in the thickness direction t can be two, and the internal electrodes 2 and 3 and the unconnected internal electrodes 8 and 9 are arranged on different planes, respectively, variations in varistor voltage, The leakage current can be reduced and the surge resistance can be improved, and the same effect as that of the above-described embodiment can be obtained.

[0016]

[Table 1]

Table 1 shows the results of tests conducted to confirm the effects of the chip varistor 1 of the above-mentioned embodiment. In this test, an example sample was prepared by the above-described manufacturing method, and the varistor voltage V _{1mA of} this sample, the limiting voltage ratio V _2A / V _1mA ,
The surge withstand amount A, the insulation resistance value MΩ, and the capacitance pF were measured. The insulation resistance value is the resistance value when 50% of the varistor voltage is applied for 30 seconds. Further, for comparison, the same measurement was performed for the chip varistor having the structure shown in FIG. As is clear from the table, the varistor voltage, the limiting voltage ratio, the insulation resistance value, and the capacitance of the example sample and the comparative sample are substantially the same, and the variation of the varistor voltage and the leakage current are improved. Has been done. In addition, the surge resistance is 20 A for the comparative sample, and the electric field is concentrated. On the other hand, the sample of this example has a current of 50 A, which shows that the surge resistance is significantly improved.

[0018]

As described above, according to the chip varistor of the present invention, the first and second internal electrodes are embedded in the sintered body so as not to overlap each other in the thickness direction, and the external electrode is provided in the sintered body. At least one non-connecting internal electrode that is not connected to the substrate is embedded, and the non-connecting internal electrode is disposed so as to overlap with the first and second internal electrodes through the semiconductor ceramic layer, and the first and second internal electrodes and Since the non-connecting internal electrodes are arranged on different planes, it is possible to suppress the growth of semiconductor crystals during firing to reduce variations in varistor voltage and leakage current, and reduce the concentration of electric fields at the electrode edges to reduce surge withstand. There is an effect that can improve.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating a chip varistor according to an embodiment of the present invention.

FIG. 2 is an exploded perspective view of the chip varistor of the above embodiment.

FIG. 3 is a sectional view for explaining a chip varistor according to another example of the above embodiment.

FIG. 4 is a cross-sectional view of a chip varistor for explaining the formation process of the present invention.

FIG. 5 is a sectional view showing a conventional laminated varistor.

[Explanation of symbols]

 1,1 'Chip varistor 2 Sintered bodies 2a, 2b Left and right end faces of the sintered body 3 First internal electrode 3a One end face 4 Second internal electrode 4a One end face 5,8,9 Non-connected internal electrode 6 External electrode 7a ~ 7c Semiconductor ceramics layer t Thickness direction

Front page continuation (72) Inventor Yasunobu Yoneda 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto, Murata Manufacturing Co., Ltd. (72) Yukio Sakabe 2-26-10 Tenjin, Nagaokakyo, Kyoto Murata Manufacturing Co., Ltd. (72) Inventor Shigeaki Gotoga 2-26-10 Tenjin, Nagaokakyo-shi, Kyoto Inside Murata Manufacturing Co., Ltd.

Claims (1)

Claim: What is claimed is: 1. A sintered body formed by laminating a plurality of semiconductor ceramic layers, wherein first and second internal electrodes are embedded so as not to overlap in the thickness direction of the ceramic layers, and At least one unconnected internal electrode that connects only one end surface of the first and second internal electrodes to the external electrodes formed on the left and right end surfaces of the sintered body and is not connected to the external electrode in the sintered body. Is embedded so as to overlap the first and second internal electrodes with the semiconductor ceramic layer interposed therebetween, and the first and second internal electrodes are embedded.
A chip varistor in which a second internal electrode and a non-connected internal electrode are arranged on different planes.