JP2008270391A - Multilayer chip varistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer chip varistor which is highly reliable and corresponds to thinning, while holding a varistor characteristic with respect to an electrostatic surge voltage, and to provide its manufacturing method. <P>SOLUTION: The multilayer chip varistor includes: a lamination body 10 where a plurality of varistor parts are arranged along a prescribed direction, having varistor material layers 12 composed of zinc oxide as a main component so as to express a voltage nonlinear characteristic and a plurality of internal electrodes 11 arranged to sandwich the varistor material layers 12: glass ceramic material layers 13, 14 which are arranged on at least the upper and lower main surfaces of the lamination body 10 and where ceramic powder containing at least alumina or silica is mixed with glass powder containing SiO<SB>2</SB>-Al<SB>2</SB>O<SB>3</SB>-MO (M is at least the one to be selected from Ca, Ba, Sr)-base crystallized glass; and a pair of terminal electrodes 15 to be connected to the internal electrodes 11. A part of the configuration components of the varistor material layers 12 exists in the glass ceramic material layers 13, 14 and a part of glass components of the glass ceramic material layers 13, 14 exists in the varistor material layers 12. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a multilayer chip varistor that protects an electronic device from an overvoltage such as an electrostatic pulse, and a method of manufacturing the same.

  A conventional multilayer chip varistor will be described below with reference to the drawings.

  2. Description of the Related Art In recent years, electronic devices such as mobile phones have been rapidly downsized and enhanced in performance, and electronic device circuits have become denser and voltage resistance of electronic devices has been reduced. Therefore, the destruction of the electric circuit inside the device due to the electrostatic pulse generated when the human body and the terminal of the electronic device contact each other is increasing.

  As a countermeasure against such an electrostatic pulse, there is a method in which a laminated chip varistor is provided between a line where static electricity enters and the ground, and the voltage applied to the electric circuit of the electronic device is suppressed by bypassing the static electricity.

  FIG. 9 is a sectional view of the multilayer chip varistor.

  In FIG. 9, the multilayer chip varistor includes a varistor material layer 2 having an internal conductor 1 and a terminal electrode 3 connected to the internal electrode 1 on an end face of the varistor material layer 2. A high resistance layer 4 is formed on the surface of the varistor material layer 2.

For example, Patent Document 1 is known as prior art document information related to the present invention.
Japanese Patent No. 3453857

  In the conventional multilayer chip varistor, a nickel or tin film is formed on the surface of the terminal electrode conductor by plating in order to improve the solderability and wettability of the terminal electrode. However, since the varistor material mainly composed of zinc oxide exhibits semiconductor electrical characteristics, a plated metal film is also formed on the surface of the varistor material layer in the terminal electrode plating process described above, and in the worst case, both terminal electrodes are short-circuited. End up. In addition, it has been found by the inventors that ordinary zinc oxide varistor materials exhibit superior varistor characteristics in voltage nonlinearity when sintered at a temperature lower than the temperature at which they are sintered completely densely. In such a sintered state, the plating solution penetrates into the varistor material layer in the terminal electrode plating step, and the varistor material is eroded and reliability is lowered. Also, since the firing conditions are sensitive to temperature variations in the firing furnace, varistor characteristics such as varistor voltage (voltage when a current of 1 mA is passed) and voltage nonlinearity are likely to vary.

  Therefore, the conventional multilayer chip varistor has been baked under strictly controlled conditions or by a special method. In Patent Document 1, the varistor element is embedded in an oxide mixed powder such as silica and fired, or the varistor element is fired while rotating and stirring the oxide mixed powder and the varistor element together with balls such as zirconia. A method is disclosed. According to this firing method, variation in varistor characteristics can be suppressed, and the high resistance layer 4 made of glass or oxide is formed on the surface of the varistor material, so that the plating resistance and moisture resistance of the varistor material are improved. However, such a firing method is inefficient and unsuitable as a mass production method.

  In recent years, the thickness of integrated circuit elements and blue diodes protected by the multilayer chip varistor has been reduced, and a thin multilayer chip varistor has been desired. The multilayer chip varistor, usually called 1005 size, has outer dimensions of 1.0 mm, 0.5 mm, and a thickness of 0.5 mm. However, a thickness of 0.3 mm or less is desired in accordance with the thickness of an integrated circuit element or the like. . As a multilayer chip varistor having a thickness of 0.3 mm, a 0603 size (outer dimensions: 0.6 mm, 0.3 mm, thickness: 0.3 mm) has been put into practical use. A 0603 size chip component is mounted on a substrate. For this purpose, a dedicated mounting machine is required, so it is not common outside some industries. Under these circumstances, a 1005 size thin laminated chip varistor having a thickness of 0.3 mm or less is required. However, since the strength of the varistor material itself is low, the terminal electrode is formed or mounted on the substrate. There was a problem of being destroyed.

  SUMMARY OF THE INVENTION The present invention solves the above problems, and provides a multilayer chip varistor that has excellent varistor electrical characteristics with small variations, and that is improved in reliability and compatible with thinning, and a manufacturing method that is excellent in mass productivity. The purpose is that.

  In order to achieve the above object, the present invention has the following configuration.

The multilayer chip varistor of the present invention includes a varistor material layer that exhibits voltage nonlinear characteristics including zinc oxide as a main component and at least bismuth oxide as a subcomponent, and a plurality of internal electrodes arranged so as to sandwich the varistor material layer. And a ceramic powder containing at least alumina or silica arranged on at least the upper and lower main surfaces of the laminate, and SiO ₂ —Al ₂ O _3. A glass ceramic material layer in which glass powder containing MO (M is at least one selected from Ca, Ba, Sr) based crystallized glass and a pair of terminal electrodes connected to the internal electrodes, the glass ceramic Part of the constituent components of the varistor material layer is present in the material layer, and part of the glass component of the glass ceramic material layer is present in the varistor material layer. And wherein the door.

Also, the manufacturing method of the multilayer chip varistor of the present invention includes a varistor material layer exhibiting voltage nonlinear characteristics including zinc oxide as a main component and at least bismuth oxide as a subcomponent, and a plurality of internal varistor layers sandwiching the varistor material layer. A step of producing a varistor laminated body in which electrodes are arranged; and ceramic powder containing at least alumina or silica and SiO ₂ —Al ₂ O ₃ —MO (M is Ca, Ba, Sr) on at least the upper and lower main surfaces of the varistor laminated body. At least one selected from: a step of producing a composite laminate in which a glass ceramic material layer mixed with glass powder containing a crystallized glass is laminated, and the composite laminate is fired at a temperature at which the varistor material layer is sintered. And a step of chamfering the sides and corners of the composite laminate by a mechanical method before or after the firing step, and a connection with the internal electrode. Characterized in that it comprises at least the step of forming the terminal electrodes of the.

The multilayer chip varistor of the present invention comprises at least one selected from ceramic powder containing at least alumina or silica on the upper and lower principal surfaces of the varistor material layer and SiO ₂ —Al ₂ O ₃ —MO (M is Ca, Ba, Sr). ) Glass ceramic material layer mixed with glass powder containing crystallized glass is laminated and fired, and the bismuth oxide, which is a minor component of varistor material, is not excessively evaporated. Since it is diffused and fixed, a multilayer chip varistor having small variation and excellent varistor electrical characteristics can be obtained by a simple method.

  In addition, a part of the glass component of the glass ceramic material diffuses in the varistor material layer, and in particular, the varistor material is fixed on the side surface of the varistor material layer to form a dense and highly insulating layer. Plating deposition on the layer surface and erosion of the varistor material layer by the plating solution can be easily suppressed, and as a result, reliability can be improved.

  In addition, because the glass ceramic material with higher mechanical strength than the varistor material is laminated on the top and bottom main surfaces, it is a thin laminated type with high strength that can suppress breakage when forming terminal electrodes or mounting on the substrate A chip varistor can be obtained.

  As a result, it is possible to provide a multilayer chip varistor that has excellent varistor electrical characteristics with small variations, improved reliability, and that can be made thinner, and a manufacturing method that is excellent in mass productivity.

(Embodiment 1)
Hereinafter, the inventions described in claims 1 to 4 and 8 of the present invention will be described with reference to the first embodiment of the present invention.

  1 is a cross-sectional view of a multilayer chip varistor according to Embodiment 1 of the present invention, and FIG. 2 is a perspective view of the multilayer chip varistor. 1 and 2, the multilayer chip varistor according to the first embodiment of the present invention includes a laminate 10 composed of a varistor material layer 12 in which two or more internal electrodes 11 are laminated, and upper and lower surfaces of the laminate 10. The laminated glass ceramic material layers 13 and 14, the terminal electrode 15 connected to the internal electrode 11 of the varistor material layer 12, and the plating films 16 and 17 of the terminal electrode 15 are provided.

  The varistor material constituting the varistor material layer 12 is mainly composed of zinc oxide, contains at least bismuth oxide as a subsidiary component, and exhibits varistor characteristics by adding antimony oxide, manganese oxide, cobalt oxide, etc. A material that is fired at around 950 ° C. by adding s. Note that oxides other than the above may be added as other subcomponents as long as they exhibit excellent varistor characteristics.

  The varistor material powder, a binder resin, and a plasticizer are mixed with a solvent, and a green sheet having a thickness of about 50 μm is formed by a known doctor blade method or the like. A conductive paste mainly composed of a silver-palladium alloy is formed on the green sheet by patterning the internal electrode 11 by a method such as screen printing, and the internal electrode 11 is partially opposed with the varistor material layer 12 sandwiched as shown in FIG. Laminate so that

The glass ceramic material constituting the glass ceramic material layers 13 and 14 includes ceramic powder containing at least alumina or silica, and SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, and Sr). A material mixed with glass powder containing system crystallized glass was used. The reason for selecting the glass ceramic material having such a composition will be described later. As for the glass ceramic material, a green sheet having a thickness of about 40 μm is formed by the same method as the varistor material, and the glass ceramic material green sheet is laminated on the upper and lower main surfaces of the laminate 10 as shown in FIG. , 14 are formed. Thus, a composite laminate is formed.

A temperature (85 ° C.) and a pressure (500 kg / cm ² ) are applied to the composite laminate for 1 minute, and then, the composite laminate is cut into individual chip laminates with a cutter. This is put into a baking furnace, the resin component is incinerated at a temperature of about 500 ° C., and then baked at 950 ° C. for 2 hours. During the firing, zinc oxide as a main component constituting the varistor material, bismuth oxide as a subsidiary component, and the like are formed on the glass ceramic material layers 13 and 14 by SiO ₂ —Al ₂ O ₃ —MO (where M is the glass ceramic material). At least one selected from Ca, Ba, and Sr) system crystallized glass mutually diffuses in the varistor material layer 12, and the varistor material layer and the glass ceramic material layer are bonded and integrated.

  In order to prevent chipping during the terminal electrode coating process or mounting on the substrate, the composite laminate chip is barrel-polished with an alumina ball and water with SiC attached to the surface with a planetary ball mill, etc. Round the edges and corners. This step may be performed before or after the composite laminate chip is fired, as long as barrel polishing can be efficiently performed without destroying the composite laminate chip. This barrel polishing process is also effective for eliminating the distortion shape due to the difference in the firing behavior of the glass ceramic material layer and the varistor material layer.

  A terminal electrode 15 is formed by applying and baking a silver-palladium electrode paste on the side surface where the internal electrode of the composite laminate chip is exposed. When the nickel plating film 16 and the tin plating film 17 are formed on the surface of the terminal electrode 15 by the electrolytic plating method or the like, the multilayer chip varistor shown in FIGS. 1 and 2 is completed.

  As described above, the glass constituting the glass ceramic material layer is diffused in the varistor material layer, but a particularly high concentration of glass is diffused on the side surface of the varistor material layer, compared with the inside of the varistor material layer. The insulation resistance value is high. Therefore, according to this configuration of the present invention, the possibility that the plating film is deposited on the surface of the varistor material layer by the electroplating process is extremely low.

  In addition to the structure shown in FIGS. 1 and 2, the terminal electrode 15 is formed only on the surface of the glass ceramic material layers 13 and 14 as shown in the sectional view of FIG. 3, and the internal electrode 11 is a via as an internal via conductor. The electrode 18 may be electrically connected. In this case, the internal electrode 11 does not need to be exposed on the side surface of the composite laminate chip. In this structure, since the terminal electrode 15 is formed on the glass ceramic material layer having an originally high insulation resistance value, even if a plating film is deposited on the side surface of the varistor material layer 12, the surface of the glass ceramic material layers 13, 14 The possibility of depositing a plating film is even lower. Therefore, according to this more preferable structure, the possibility that the left and right terminal electrodes 15 are electrically short-circuited due to abnormal deposition of the plating film is extremely low.

Next, as a material constituting the glass ceramic material layer, ceramic powder containing at least alumina or silica, and SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, Sr) based crystallized glass The reason for selecting the material mixed with the glass powder containing the will be described. Table 1 shows the results of measuring the varistor electrical characteristics when the glass ceramic material type was changed and the thickness of the glass ceramic material layer after firing.

As is apparent from Table 1, ceramic powder containing at least alumina or silica as a material constituting the glass ceramic material layer, and SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, Sr) ) When a material mixed with glass powder containing system crystallized glass is selected, the voltage change with respect to the current change is small and excellent varistor characteristics are exhibited. On the other hand, when a glass ceramic material outside the scope of the present invention is laminated (No. 23 to 26) or when a glass ceramic material layer produced as a comparative example is not laminated (No. 27), the varistor voltage V _{1 mA} ( Only a varistor characteristic inferior in voltage non-linearity is obtained, which is high when the current of 1 mA is passed, and has a large voltage change with respect to the current change. Varistor materials that contain zinc oxide as the main component and at least bismuth oxide as a subcomponent evaporate and diffuse subcomponents such as bismuth oxide during firing, and subcomponents such as zinc oxide and bismuth oxide contain highly insulating compounds. By forming at the grain boundaries, voltage non-linearity, so-called varistor characteristics are developed. The type and thickness of the insulating compound layer at the grain boundary affect the superiority or inferiority of the varistor characteristics. When the thickness becomes particularly thin, the voltage nonlinearity is lost and the voltage-current characteristics conform to Ohm's law. When firing under conditions where the evaporation of subcomponents such as bismuth oxide without laminating a glass ceramic material layer as in the comparative example is performed, the thickness of the insulating compound at the grain boundary becomes too thin and hardly exhibits voltage nonlinearity. On the other hand, when the glass ceramic material layer having the composition of the present invention is laminated on the upper and lower main surfaces of the varistor material layer, subcomponents such as bismuth oxide are first directed to the upper and lower surfaces on which the glass ceramic material layer is laminated rather than the side surfaces of the varistor material layer. It is diffused selectively. Subcomponents such as bismuth oxide diffused into the glass ceramic material layer are alumina, silica, SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, Sr) constituting the glass ceramic material layer. A compound is formed with the system crystallized glass and is fixed in the glass ceramic material layer. At the same time, the glass component of the glass ceramic material layer diffuses particularly to the side surface of the varistor material layer to form a compound having high insulation resistance. When baked in this state, excessive evaporation of secondary components such as bismuth oxide is suppressed, high resistance insulating compounds are uniformly formed at the grain boundaries of zinc oxide, and varistors exhibiting excellent voltage nonlinearity characteristics are baked. It is considered possible. The present invention is limited to alumina, silica, SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, and Sr) based crystallized glass as a material constituting the glass ceramic material layer. This is because it has been newly confirmed that the above phenomenon is stably expressed.

The weight ratio of the ceramic powder containing alumina or silica constituting the glass ceramic material to the SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, Sr) based crystallized glass powder is ceramic It is preferable that the powder is in the range of 30 to 60% by weight and the crystallized glass powder is in the range of 70 to 40% by weight. If the glass ceramic material layer has a weight ratio outside this range, the strength of the glass ceramic material will be low, and if a thin multilayer chip varistor is produced, cracks may occur in the glass ceramic material layer when the terminal electrode is formed or mounted on the substrate. This is because the defect is likely to occur. When the glass ceramic material layer is not stacked, cracks are generated in almost all varistor material layers when forming the terminal electrode, but the frequency of defects is extremely low, but in order to accommodate thinner multilayer chip varistors. Is preferably a glass ceramic material within the above weight ratio range.

  Moreover, it is preferable that the thickness after baking of a glass-ceramic material layer exists in the range of 10 micrometers-40 micrometers. Table 2 shows the thickness of the glass-ceramic material layer after firing (in Table 2, expressed as the glass-ceramic thickness), the varistor characteristics immediately after production, and the varistor characteristics after being left in a high-temperature and high-humidity tank at 85 ° C. and 85% for 24 hours. It is the result of measuring the relationship. When the thickness is less than 10 μm, the varistor characteristics immediately after fabrication are also slightly deteriorated, and further, the varistor characteristics after being left in a high-temperature and high-humidity tank are further deteriorated. When the thickness is 40 μm or more, the varistor characteristics immediately after fabrication are excellent, but the varistor characteristics after leaving in a high-temperature and high-humidity tank are degraded. Both show superior characteristics than when the glass ceramic material layer is not laminated, but the stipulated thickness within the range of 10 μm to 40 μm shows better varistor characteristics and is higher. A multilayer chip varistor that can ensure reliability can be obtained.

  As shown in the cross-sectional view of FIG. 4, the glass ceramic material layer is not limited to the upper and lower surfaces of the varistor material layer, and even if the glass ceramic material layer 19 is arranged at the center, there is no problem.

(Embodiment 2)
Hereinafter, the invention described in claims 5 to 7 of the present invention will be described in particular using Embodiment 2 of the present invention.

  By adjusting the sintering behavior of the varistor material and the glass ceramic material, increasing the sintering speed of the glass ceramic material than the varistor material, and increasing the firing shrinkage of the varistor material layer after the sintering of the glass ceramic material layer, As shown in the cross-sectional view of FIG. 5, the side perimeter of the center portion of the varistor material layer 12 is shorter than the side perimeter of the upper and lower glass ceramic material layers 13 and 14, and the center portion of the varistor material layer 12 is curved in a concave shape ( This is a spelled shape with a constriction in the so-called stacking direction.) Such a shape is optimal as the shape of the thin plate-shaped multilayer chip varistor because stress is dispersed and hardly broken when force is applied from the upper and lower surfaces.

  In addition, in order to completely suppress plating film deposition on the surface of the varistor material layer, an insulator such as silicone resin is formed on the side surface of the varistor material layer where the internal electrode is exposed and the terminal electrode is not formed before the plating step. Is desirable. As shown in the cross-sectional view of FIG. 6, when the central portion of the varistor material layer 12 is curved in a concave shape, the insulator 20 can be formed thick, and the adhesive strength between the varistor material layer 12 and the insulator 20 is dramatically increased. Therefore, there is almost no possibility that problems such as peeling off of the insulator occur in the processes after plating.

  Also, when forming a terminal electrode connected to the internal electrode exposed on the side surface of the varistor material layer, the plated metal film is abnormally deposited on the side surface of the varistor material layer where the internal electrode is not exposed, thus completely preventing an electrical short circuit between the terminal electrodes. Therefore, it is desirable to form the terminal electrode only on the side surface where the internal electrode is exposed and the glass ceramic material layer above and below the side electrode, and prevent the terminal electrode from being formed on the side surface where the internal electrode is not exposed. . However, in a normal rectangular cross-sectional chip laminate, the terminal electrode thickness is thin, so that a desired terminal electrode strength cannot be obtained. On the other hand, if the central portion of the varistor material layer is concavely curved as described above, sufficient thickness can be obtained even if the terminal electrode 15 is formed only on the surface where the internal electrode 11 is exposed as shown in the sectional view of FIG. Therefore, a highly reliable multilayer chip varistor can be obtained.

  Even if the glass ceramic material layer is arranged not only on the upper and lower surfaces of the varistor material layer but also in the center portion, if the sintering behavior of the varistor material and the glass ceramic material is adjusted as described above, as shown in the sectional view of FIG. The same effect as above can be obtained.

  As described above, the multilayer chip varistor and the manufacturing method thereof according to the present invention have excellent varistor electrical characteristics with small variations, can improve reliability, and are compatible with thinning, and are thus mass-productive. Therefore, it can be applied to various electronic devices that are vulnerable to electrostatic pulse voltage.

Sectional drawing of the multilayer chip varistor in Embodiment 1 of this invention Perspective view of the same multilayer chip varistor Sectional drawing of the other multilayer chip varistor in Embodiment 1 Sectional drawing of the other multilayer chip varistor in Embodiment 1 Sectional drawing of the multilayer chip varistor in Embodiment 2 of this invention Sectional drawing of the other multilayer chip varistor in Embodiment 2 Sectional drawing of the other multilayer chip varistor in Embodiment 2 Sectional drawing of the other multilayer chip varistor in Embodiment 2 Cross-sectional view of a conventional multilayer chip varistor

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Laminated body 11 Internal electrode 12 Varistor material layer 13 Glass ceramic material layer 14 Glass ceramic material layer 15 Terminal electrode 16 Nickel plating film 17 Tin plating film 18 Via-hole electrode 19 Glass ceramic material layer 20 Insulator

Claims (8)

A plurality of varistor portions each having a varistor material layer exhibiting voltage nonlinear characteristics including zinc oxide as a main component and at least bismuth oxide as a subcomponent and a plurality of internal electrodes arranged so as to sandwich the varistor material layer are predetermined. And a ceramic powder containing at least alumina or silica and SiO ₂ —Al ₂ O ₃ —MO (M is Ca, Ba) disposed on at least the upper and lower main surfaces of the laminate. And a glass ceramic material layer mixed with glass powder containing a crystallized glass, and a pair of terminal electrodes connected to the internal electrode, wherein the glass ceramic material layer includes the varistor material layer. And a part of the glass component of the glass ceramic material layer is present in the varistor material layer. Varistor. 2. The multilayer chip varistor according to claim 1, wherein the glass ceramic material layer has a ceramic powder content of 30 wt% to 60 wt% and a glass powder content of 70 wt% to 40 wt%. The multilayer chip varistor according to claim 1, wherein the glass ceramic material layer has a thickness of 10 μm to 40 μm. 2. The multilayer chip varistor according to claim 1, wherein a terminal electrode is formed only on the surface of the glass ceramic material layer, and the terminal electrode and the internal electrode are connected by an internal via conductor. The side perimeter of the central part of the varistor material layer in the stacking direction is shorter than the side perimeter of the glass ceramic material layer, and the center of the varistor material layer in the stacking direction is curved in a cross-sectional concave shape than the glass ceramic material layer. The multilayer chip varistor according to claim 1, wherein the multilayer chip varistor is formed. 6. The multilayer chip varistor according to claim 5, wherein an insulator is filled in the concave curved portion of the cross section of the varistor material layer on the surface where the internal electrode is not exposed. 6. The multilayer chip varistor according to claim 5, wherein a conductor is formed only on the concave curved surface of the varistor material layer on the surface where the internal electrode is exposed and the glass ceramic material layer above and below the concave curved part surface. A step of producing a varistor laminated body in which a varistor material layer expressing a voltage non-linear characteristic including zinc oxide as a main component and at least bismuth oxide as a subcomponent, and a plurality of internal electrodes arranged so as to sandwich the varistor material layer;
At least the upper and lower main surfaces of the varistor laminate include ceramic powder containing at least alumina or silica and SiO ₂ —Al ₂ O ₃ —MO (M is at least one selected from Ca, Ba, Sr) based crystallized glass. Producing a composite laminate in which glass ceramic material layers mixed with glass powder are laminated;
Firing the composite laminate at a temperature at which the varistor material layer is sintered;
Before or after the firing step, chamfering the sides and corners of the composite laminate by a mechanical method;
A method of manufacturing a multilayer chip varistor, comprising at least a step of forming a pair of terminal electrodes connected to the internal electrodes.

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