JP2005353845A - Laminated chip varistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip varistor that appropriately maintains ESD withstand, while reducing the capacitance. <P>SOLUTION: The laminated chip varistor 1 comprises a laminate 3, and a pair of external electrodes 5 formed in the laminate 3. The laminate 3 has a varistor 7, and a pair of external layers 9 arranged so that the varistor 7 is sandwiched. The varistor 7 includes a varistor layer 11 manifesting varistor characteristics itself, and a pair of internal electrodes 13 are arranged so that the varistor layer 11 is sandwiched. The pair of internal electrodes 13 are electrically connected to the external electrode 5. The relative dielectric constant of the external layer is set smaller than that of a region overlapping the pair of internal electrodes 13 in the varistor layer 11. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a multilayer chip varistor.

As this type of multilayer chip varistor, a varistor part including a varistor layer that expresses a voltage nonlinear characteristic (hereinafter referred to as “varistor characteristic”) and a pair of internal electrodes arranged so as to sandwich the varistor layer; It is known to have a laminate having a pair of outer layer portions arranged so as to sandwich the varistor portion, and a pair of external electrodes formed in the laminate and connected to the pair of internal electrodes, respectively. (For example, refer to Patent Document 1). In the multilayer chip varistor described in Patent Document 1, the outer layer portion is made of the same material as the varistor layer.
JP-A-11-265805

  The present invention provides a multilayer chip varistor capable of achieving low electrostatic capacity while maintaining good resistance to ESD (Electrostatic Discharge) (hereinafter referred to as “ESD resistance”). Is an issue.

  In recent high-speed interfaces, the structure of the IC itself is becoming vulnerable to ESD in order to achieve high speed. For this reason, there is an increasing demand for ESD countermeasures in high-speed transmission ICs, and multilayer chip varistors are used as ESD countermeasure parts. As a characteristic required for a multilayer chip varistor as an ESD countermeasure component for a high-speed transmission system, it is essential to reduce capacitance. If the developed electrostatic capacity is large, there is a problem in signal quality, and in the worst case, communication may be disabled.

  As a technique for reducing the capacitance of the multilayer chip varistor, a technique of reducing the area of the portion where the internal electrodes overlap with each other can be considered. By reducing the area of the portion where the internal electrodes overlap each other, the area where the electrostatic capacity is developed is reduced, and the electrostatic capacity is reduced. However, if the area of the portion where the internal electrodes overlap with each other is reduced, a new problem that the ESD resistance decreases is caused. When a surge voltage such as ESD is applied, the electric field distribution in the portion where the internal electrodes overlap with each other is concentrated at the end of the portion where the internal electrodes overlap each other. When the electric field distribution of the portion where the internal electrodes overlap with each other is concentrated at the end portion, the ESD tolerance decreases rapidly as the area of the portion where the internal electrodes overlap with each other decreases.

  Therefore, as a result of intensive studies on a multilayer chip varistor that can achieve a low capacitance while maintaining good ESD resistance, the present inventors have newly found the following facts.

The electrostatic capacity C _total of the varistor includes not only the electrostatic capacity C ₁ in the varistor characteristic expression area but also the electrostatic capacity C in an area other than the varistor characteristic expression area as shown by the following equation (1). _{2 is} also included.
C _total = C ₁ + C ₂ (1)
C ₁ : Capacitance in a region overlapping the pair of internal electrodes in the varistor layer (hereinafter referred to as “varistor characteristic expression region”) C ₂ : Capacitance in a region other than the varistor characteristic expression region

The relative dielectric constant of the varistor characteristic manifestation region is generated because the potential formed at the crystal grain boundary behaves as a capacitor component, and is usually in the order of several hundreds. For this reason, when the area other than the varistor characteristic expression area is made of the same material as the varistor characteristic expression area, the ratio of the area other than the varistor characteristic expression area is reduced in order to reduce the capacitance of the multilayer chip varistor. The dielectric constant cannot be ignored. That is, if it is possible to reduce the dielectric constant of the region other than the varistor characteristics expression region, the capacitance C ₂ of the region other than the varistor characteristic expression region is lowered, the low capacitance of the capacitance C _total of the varistor Can be achieved.

  Based on such research results, the multilayer chip varistor according to the present invention includes a varistor part including a varistor layer that exhibits voltage nonlinear characteristics and a pair of internal electrodes arranged so as to sandwich the varistor layer, and the varistor part. A laminate having a pair of outer layer portions arranged so as to sandwich the pair, and a pair of external electrodes formed in the laminate and respectively connected to the pair of internal electrodes, and the relative dielectric constant of the outer layer portion is It is characterized in that it is set smaller than the relative dielectric constant of the region overlapping the pair of internal electrodes in the varistor layer.

  In the multilayer chip varistor according to the present invention, since the relative dielectric constant of the outer layer portion is set smaller than the relative dielectric constant of the region overlapping the pair of internal electrodes in the varistor layer, the capacitance of the outer layer portion is the varistor layer. It becomes low compared with the electrostatic capacitance of the area | region which overlaps with a pair of internal electrode in. As a result, the capacitance of the multilayer chip varistor can be reduced. In addition, since the area of the portion where the internal electrodes overlap each other can be set in consideration of the ESD tolerance, the ESD tolerance can be maintained well.

  According to the present invention, it is possible to provide a multilayer chip varistor capable of achieving a low capacitance while maintaining good ESD tolerance.

  Hereinafter, preferred embodiments of a multilayer chip varistor according to the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  First, the configuration of the multilayer chip varistor 1 according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining a cross-sectional configuration of the multilayer chip varistor according to the present embodiment.

  As shown in FIG. 1, the multilayer chip varistor 1 includes a multilayer body 3 and a pair of external electrodes 5 that are respectively formed on opposite end surfaces of the multilayer body 3. The laminate 3 includes a varistor part 7 and a pair of outer layer parts 9 arranged so as to sandwich the varistor part 7, and is configured by laminating the varistor part 7 and the pair of outer layer parts 9. Yes. The laminated body 3 has a rectangular parallelepiped shape, for example, the length is set to 1.6 mm, the width is set to 0.8 mm, and the height is set to 0.8 mm. The multilayer chip varistor 1 according to this embodiment is a so-called 1608 type multilayer chip varistor.

  The varistor portion 7 includes a varistor layer 11 that exhibits varistor characteristics, and a pair of internal electrodes 13 that are arranged so as to sandwich the varistor layer 11. In the varistor part 7, the varistor layers 11 and the internal electrodes 13 are alternately laminated. A region 11 a overlapping the pair of internal electrodes 13 in the varistor layer 11 functions as a region that develops varistor characteristics.

  The varistor layer 11 contains ZnO (zinc oxide) as a main component, and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K) as subcomponents. , Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and the like, and a first element body containing these oxides. In the present embodiment, the varistor layer 11 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. Thereby, the region 11a overlapping the pair of internal electrodes 13 in the varistor layer 11 has a region composed of a first element body containing ZnO as a main component and containing Co and Pr.

  Pr and Co are materials for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. The content of ZnO in the varistor layer 11 is not particularly limited, but is usually 99.8 to 69.0% by mass when the total material constituting the varistor layer 11 is 100% by mass. The thickness of the varistor layer 11 is, for example, about 5 to 60 μm.

The pair of internal electrodes 13 are provided substantially in parallel so that one end portions of the pair of internal electrodes 13 are alternately exposed at opposite end surfaces of the stacked body 3. Each internal electrode 13 is electrically connected to the external electrode 5 at each one end. The internal electrode 13 includes a conductive material. The conductive material contained in the internal electrode 13 is not particularly limited, but is preferably made of Pd or an Ag—Pd alloy. The thickness of the internal electrode 13 is, for example, about 0.5 to 5 μm. When the multilayer chip varistor 1 has a low capacitance, the area of the overlapping portion 13a of the internal electrode 13 is usually 0.001 to 0.5 mm ^{2 as} viewed from the stacking direction of the stacked body 3, preferably 0.002. About 0.1 mm ² .

  The external electrode 5 is provided so as to cover both end faces of the multilayer body 3. The external electrode 5 is preferably made of a metal material that can be electrically connected to a metal such as Pd constituting the internal electrode 13 in an excellent manner. For example, Ag is suitable as a material for the external electrode because it has good electrical connectivity with the internal electrode 13 made of Pd and has good adhesion to the end face of the laminate 3. Such an external electrode 5 is normally about 10 to 50 μm thick.

  On the surface of the external electrode 5, a Ni plating layer (not shown) having a thickness of about 0.5 to 2 μm and a Sn plating layer (not shown) having a thickness of about 2 to 6 μm so as to cover the external electrode 5. Are formed in order. These plating layers are formed mainly for the purpose of improving solder heat resistance and solder wettability when the multilayer chip varistor 1 is mounted on a substrate or the like by solder reflow.

  The plating layer formed on the surface of the external electrode 5 is not necessarily limited to the combination of materials described above as long as the purpose of improving solder heat resistance and solder wettability is achieved. Other materials that can form the plating layer include, for example, Sn—Pb alloy and the like, and may be used in combination with the above-described Ni or Sn. Further, the plating layer is not necessarily limited to the two-layer structure, and may have a structure of one layer or three or more layers.

  The outer layer portion 9 contains ZnO as a main component, and includes rare earth metal elements, Co, IIIb group elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs) as subcomponents. ) And alkaline earth metal elements (Mg, Ca, Sr, Ba) and the like and a second element body containing these oxides. In the present embodiment, the outer layer portion 9 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. The Co content in the second element body is set lower than the Co content in the first element body. As a result, the outer layer portion 9 has a region composed of the second element body containing ZnO as a main component and containing less Co than the first element body. The thickness of the outer layer portion 9 is, for example, about 0.30 to 0.38 μm.

  The Co content in the first element body is 0.1 mol% or more with respect to 100 mol% of the total amount of zinc oxide and other metal atoms in consideration of the expression of varistor characteristics in the varistor layer 11 (region 11a). It is preferable that Accordingly, the Co content in the second element body is preferably less than 0.1 mol% with respect to 100 mol% of the total amount of zinc oxide and other metal atoms. Note that the Co content in the second element body is zero, that is, the second element body may not contain Co.

  As described above, according to the multilayer chip varistor 1 of the present embodiment, the outer layer 9 has the second element body in which the content of Co as a material for expressing the varistor characteristics is smaller than that of the first element body. Therefore, the potential formed at the crystal grain boundary in the outer layer portion 9 becomes small. As a result, the relative dielectric constant of the outer layer portion 9 becomes smaller than the relative dielectric constant of the region 11 a overlapping the pair of internal electrodes 13 in the varistor layer 11, and the capacitance of the outer layer portion 9 is lowered. As a result, the capacitance of the entire multilayer chip varistor 1 can be reduced. Further, since the area of the portion where the internal electrodes 13 overlap can be set in consideration of the ESD tolerance, the multilayer chip varistor 1 can maintain the ESD tolerance favorably.

  When the second element body does not contain Co, the potential formed at the crystal grain boundary in the outer layer portion 9 becomes extremely small. As a result, the relative dielectric constant of the outer layer portion 9 is extremely smaller than the relative dielectric constant of the region 11a, and the capacitance of the outer layer portion 9 is significantly reduced. As a result, the capacitance of the multilayer chip varistor 1 can be further reduced.

  As a modification of the present embodiment, the Co content in the second element body is set to be smaller than the Co content in the first element body, and the rare earth metal in the second element body (in this embodiment, , Pr) may be set lower than the rare earth metal content in the first element body. In this case, the outer layer portion 9 has a region composed of a second element body containing ZnO as a main component and containing less Co and rare earth metal than the first element body. Note that the content of the rare earth metal in the second element body is zero, that is, the second element body may not include the rare earth metal.

  In consideration of the expression of varistor characteristics in the varistor layer 11 (region 11a), the Pr content in the first element body is 0.05 mol% or more with respect to 100 mol% of the total amount of zinc oxide and other metal atoms. It is preferable that Therefore, the Pr content in the second element body is preferably less than 0.05 mol% with respect to 100 mol% of the total amount of zinc oxide and other metal atoms. Note that the Pr content is not necessarily limited to the above numerical range because it is related to the Co content.

  In the above modification, the outer layer portion 9 has a region composed of the second element body in which the content ratios of Co and rare earth metal are less than the first element body, respectively, so that only the Co content ratio is as in the above embodiment. The potential formed at the crystal grain boundary in the outer layer portion 9 is smaller than that in the case where the number is reduced, that is, the relative dielectric constant of the region 11a where the relative dielectric constant of the outer layer portion 9 overlaps the pair of internal electrodes 13 in the varistor layer 11 Smaller than. As a result, the capacitance of the outer layer portion 9 is further reduced, and the capacitance of the entire multilayer chip varistor 1 can be further reduced.

  When the second element body does not include Co and rare earth metal, the potential formed at the crystal grain boundary in the outer layer portion 9 is smaller than that in the case where only Co is not included, that is, the dielectric constant of the outer layer portion 9. The ratio is smaller than the relative dielectric constant of the region 11 a overlapping the pair of internal electrodes 13 in the varistor layer 11. As a result, the capacitance of the outer layer portion 9 is significantly reduced, and the capacitance of the multilayer chip varistor 1 can be further reduced.

  When the second element body contains Co, or when the second element body contains Co and rare earth metal, the second element body does not contain Co, or the second element body contains Co and rare earth metal. Compared to the case where no is included, the difference in the reduction ratio between the second element body and the first element body is reduced. For this reason, when the second element body contains Co, or when the second element body contains Co and a rare earth metal, a difference in shrinkage between the second element body and the first element body is a factor. It is possible to suppress changes in characteristics due to the residual stress on the boundary surface, peeling of internal electrodes, and the like.

  Next, a manufacturing process of the multilayer chip varistor 1 having the above-described configuration will be described with reference to FIGS. FIG. 2 is a flowchart for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment. FIG. 3 is a view for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment.

  First, after weighing each of ZnO, which is a main component constituting the varistor layer 11, and a trace amount additive such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides to a predetermined ratio. The varistor material is adjusted by mixing the components (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a first green sheet (step S102).

  Next, a paste-like Pd as a material for the internal electrode 13 is applied in a predetermined pattern on the first green sheet S1 by a printing method such as screen printing, and then the conductive paste is dried. An electrode layer having a predetermined pattern is formed (step S103).

  On the other hand, after weighing ZnO, which is the main component constituting the outer layer part 9, and trace additives such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides to a predetermined ratio. The varistor material is prepared by mixing the components (step S104). At this time, the Co content is set to be smaller than the Co content in the case of manufacturing the first green sheet. Further, the Co content may be zero. Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a second green sheet (step S105).

  Next, the first green sheet on which the electrode layer is formed, the first green sheet on which the electrode layer is not formed, and the second green sheet are stacked in a predetermined order to form a sheet laminate (step S106). . The sheet laminate thus obtained is cut into a desired size to obtain a green chip (step S107). In the obtained green chip, as shown in FIG. 3, a plurality of second green sheets S2, a first green sheet S1, two first green sheets S1 on which an electrode layer EL is formed, One green sheet S1, two first green sheets S1 on which an electrode layer EL is formed, a plurality of first green sheets S1, and a plurality of second green sheets S2 in this order. S2 is laminated. Note that it is not always necessary to stack the first green sheet S1 on which the electrode layer EL is not formed.

  Next, the green chip was subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and further fired at 1000 to 1400 ° C. for about 0.5 to 8 hours. (Step S108) to obtain the stacked body 3. By this firing, the first green sheet S1 between the electrode layers EL in the green chip becomes the varistor layer 11, and the second green sheet S2 becomes the outer layer portion 9. The electrode layer EL becomes the internal electrode 13. The laminated body 3 thus obtained may be subjected to a smoothing process on the surface of the element by putting it in a polishing container together with an abrasive or the like before performing the next step.

  Next, an alkali metal (for example, Li, Na, etc.) is diffused from the surface of the laminated body 3 (step S109). Here, first, an alkali metal compound is attached to the surface of the obtained laminate 3. A sealed rotating pot can be used for adhesion of the alkali metal compound. Although it does not specifically limit as an alkali metal compound, It is a compound which an alkali metal can diffuse from the surface of the laminated body 3 to the vicinity of the internal electrode 13 by heat processing, and an alkali metal oxide, hydroxide, chloride Nitrate, borate, carbonate, oxalate and the like are used.

  And the laminated body 3 to which this alkali metal compound adheres is heat-processed by predetermined temperature and time with an electric furnace. As a result, the alkali metal from the alkali metal compound diffuses from the surface of the laminate 3 to the vicinity of the internal electrode 13. A preferable heat treatment temperature is 700 to 1000 ° C., and the heat treatment atmosphere is air. The heat treatment time (holding time) is preferably 10 minutes to 4 hours.

  Next, an external electrode paste mainly containing Ag is applied to both ends of the laminate 3 so as to be in contact with each of the pair of internal electrodes 13, and then the paste is heated (baked) at about 550 to 850 ° C. ) Processing is performed to form a pair of external electrodes 5 made of Ag (step S110). Then, a Ni plating layer and a Sn plating layer are sequentially laminated on the outer surface of the external electrode 5 by electrolytic plating or the like. Thus, the multilayer chip varistor 1 is obtained.

  As described above, according to the manufacturing method of the present embodiment, the outer layer portion 9 is formed of the second green sheet S2 having a lower Co content than the first green sheet S1, and thus is formed at the crystal grain boundary. Thus, the outer layer portion 9 having a reduced potential is obtained. As a result, it is possible to obtain the multilayer chip varistor 1 with a reduced electrostatic capacity. Of course, since the area of the portion where the internal electrodes 13 overlap can be set in consideration of the ESD tolerance, the obtained multilayer chip varistor 1 maintains the ESD tolerance favorably.

  When the second green sheet S2 does not contain Co, the multilayer chip varistor 1 in which the potential formed at the crystal grain boundary in the outer layer portion 9 is extremely small and the capacitance is further reduced is obtained. Can do.

  As a modification of the manufacturing method according to the present embodiment, the Co content in the second green sheet S2 is set to be smaller than the Co content in the first green sheet S1, and the rare earth in the second green sheet S2 is set. The metal (Pr) content may be set lower than the rare earth metal content in the first green sheet S1. Note that the content of the rare earth metal in the second green sheet S2 is zero, that is, the second green sheet S2 may not contain the rare earth metal.

  In the above modification, the outer layer portion 9 is formed of the second green sheet S2 in which the content ratios of Co and rare earth metal are less than those of the first green sheet S1, respectively. Compared with the case where only the content of is reduced, the potential formed at the crystal grain boundary in the outer layer portion 9 becomes smaller, that is, the relative dielectric constant of the outer layer portion 9 becomes smaller than the relative dielectric constant of the varistor layer 11. As a result, it is possible to obtain the multilayer chip varistor 1 further reducing the capacitance.

  When the second green sheet S2 does not contain Co and rare earth metal, the potential formed at the crystal grain boundary in the outer layer part 9 is smaller than that in the case where only the Co is not contained, that is, the ratio of the outer layer part 9 The dielectric constant becomes smaller than the relative dielectric constant of the varistor layer 11. As a result, the multilayer chip varistor 1 having an extremely small capacitance can be obtained.

  The preferred embodiments of the present invention have been described above, but the present invention is not necessarily limited to these embodiments. For example, the above-described multilayer chip varistor 1 has a structure in which a pair of internal electrodes 13 sandwich a varistor layer 11, but the varistor of the present invention has a multilayer chip varistor in which a plurality of such structures are stacked. It may be. According to such a laminated varistor, it is possible to further improve electrostatic resistance, further drive at a low voltage, and the like.

  In the multilayer chip varistor 1 described above, the varistor layer 11 as a whole is composed of a first element body containing ZnO as a main component and containing Co and Pr. It suffices that the region 11a overlapping the electrode 13 has in part a region made of the first element body. Further, although the entire outer layer portion 9 is a second element body containing ZnO as a main component and containing less Co than the first element body, the present invention is not limited to this. It suffices to have a part of the region.

  In the manufacturing method described above, the two electrode layers EL are formed on the first green sheet S1, but the present invention is not limited to this, and one electrode layer EL is formed on the second green sheet S2. May be. Further, the two electrode layers EL may be formed on the second green sheet S2, and the sheets S1 and S2 may be laminated so that the first green sheet S1 is sandwiched between the second green sheets S2. .

  EXAMPLES Hereinafter, although an Example demonstrates this invention still in detail, this invention is not limited to these Examples.

(Example 1)
Regarding the varistor material used for the varistor layer (first green sheet), Pr (0.5 mol%), Co (1.5 mol%), ZnO (97.725 mol%) with a purity of 99.9%, Prepared by adding Al (0.005 mol%), K (0.05 mol%), Cr (0.1 mol%), Ca (0.1 mol%) and Si (0.02 mol%). . Regarding the varistor material used for the outer layer part (second green sheet), ZnO (99.175 mol%) with a purity of 99.9%, Pr (0.5 mol%), Co (0.05 mol%), Prepared by adding Al (0.005 mol%), K (0.05 mol%), Cr (0.1 mol%), Ca (0.1 mol%) and Si (0.02 mol%). . In parallel with this, a conductive paste for forming an internal electrode was prepared by mixing a metal powder composed of Pd particles, an organic binder, and an organic solvent.

Using this varistor material and conductive paste, a 1608 type multilayer chip varistor was manufactured according to the manufacturing process shown in FIG. The area of the overlapping portion of the internal electrodes was 0.05 mm ² .

Regarding the alkali metal diffusion treatment, the obtained laminate (sintered body) was mixed with Li ₂ CO ₃ powder (average particle size: 3 μm) as an alkali metal compound in an enclosed rotating pot, and the laminate 1 1 μg of Li ₂ CO ₃ powder was deposited per piece. The amount of Li ₂ CO ₃ powder introduced into the sealed rotating pot was in the range of 0.01 μg to 10 mg per laminate. The heat treatment temperature was 900 ° C., and the heat treatment time was 10 minutes.

(Examples 2 and 3)
The stacked chip varistors of Examples 2 and 3 were made in the same manner as in Example 1 except that the amount of Co added to the varistor material used for the outer layer portion (second green sheet) was set to 0.01 mol% and zero. Obtained. In order to change the amount of Co added to Example 1, in Examples 2 and 3, the amount of ZnO is adjusted so that the total amount of ZnO and other metal atoms is 100 mol%.

(Examples 4 to 7)
Except that the amount of Pr added to the varistor material used for the outer layer portion (second green sheet) is set to 0.05 mol%, 0.01 mol%, 0.005 mol%, and zero, the same as in Example 1. Thus, multilayer chip varistors of Examples 4 to 7 were obtained. In addition, in order to change the addition amount of Pr with respect to Example 1, in Examples 4-7, the quantity of ZnO is adjusted and the whole quantity of ZnO and another metal atom is 100 mol%.

(Example 8)
A multilayer chip varistor of Example 8 was obtained in the same manner as in Example 1 except that the addition amount of Co and the addition amount of Pr in the varistor material used for the outer layer portion (second green sheet) were set to zero. In addition, in order to change the addition amount of Co and Pr with respect to Example 1, in Example 8, the amount of ZnO is adjusted, and the total amount of ZnO and other metal atoms is 100 mol%.

(Comparative Example 1)
A multilayer chip varistor of Comparative Example 1 was obtained in the same manner as Example 1 except for the following. The amount of Co added to the varistor material used for the outer layer part (second green sheet) is set to 1.5 mol%, that is, the varistor material and the varistor layer (first green) used for the outer layer part (second green sheet). The varistor material used for the sheet is the same. Li ₂ CO ₃ powder is not adhered, that is, Li is not diffused into the laminate.

(Comparative Example 2)
A laminated chip varistor of Comparative Example 2 was obtained in the same manner as Example 1 except for the following. The amount of Co added to the varistor material used for the outer layer part (second green sheet) is set to 1.5 mol%, that is, the varistor material and the varistor layer (first green) used for the outer layer part (second green sheet). The varistor material used for the sheet is the same. Li ₂ CO ₃ powder is not adhered, that is, Li is not diffused into the laminate. The area of the overlapping part of the internal electrodes is set to 0.025 mm ² .

(Comparative Example 3)
The amount of Co added to the varistor material used for the outer layer part (second green sheet) is set to 1.5 mol%, that is, the varistor material and the varistor layer (first green) used for the outer layer part (second green sheet). A laminated chip varistor of Comparative Example 3 was obtained in the same manner as in Example 1 except that the varistor material used for the sheet was the same. In addition, in order to change the addition amount of Co with respect to Example 1, in Comparative Examples 1-3, the quantity of ZnO was adjusted and the whole quantity of ZnO and another metal atom was 100 mol%.

  Using the multilayer chip varistor thus obtained, the relative permittivity εA of the region overlapping the pair of internal electrodes in the varistor layer, the relative permittivity εB of the outer layer portion, the nonlinear coefficient α, the capacitance C, Each ESD tolerance was measured. Further, the ratio (εA / εB) between the relative dielectric constant εA and the relative dielectric constant εB was calculated. The results are shown in FIG.

The method for obtaining the relative dielectric constant εB is as follows. First, to form external electrodes as a distance d _B between the area S _B, the internal electrodes, measuring the capacitance C _B. Next, the relative dielectric constant εB is obtained from the following equation (2).
εB = C _B * d _B / ε ₀ * S _B (2)

The method for obtaining the relative dielectric constant εA is as follows. First, the capacitance C of the produced multilayer chip varistor is measured. Next, the relative dielectric constant εA is obtained from the following equation (3).
εA = (C−C _B ) * d _A / ε ₀ * S _A (3)
d _A : interval between internal electrodes S _A : area of overlapping portion of internal electrodes

The non-linear coefficient α indicates the relationship between the voltage and current applied between the electrodes of the multilayer chip varistor when the current flowing through the multilayer chip varistor changes from 1 mA to 10 mA, and was obtained from the following equation (4). .
α = log (I ₁₀ / I ₁ ) / log (V ₁₀ / V ₁ ) (4)
Here, V ₁₀ means a varistor voltage when a current of I ₁₀ = 10 mA is passed through the multilayer chip varistor, and V ₁ is a varistor when a current of I ₁ = 1 mA is passed through the multilayer chip varistor. Means voltage. The larger the nonlinear coefficient α, the better the varistor characteristics.

  The electrostatic capacity C is an electrostatic capacity at 1 MHz, and was measured by a 4284A apparatus manufactured by HP. In this example, when the capacitance C was 2.0 pF or less, it was determined that the capacitance of the multilayer chip varistor was sufficiently low, and “good (◯)” was determined. The reason why the criterion is 2.0 pF or less is that when the capacitance of the multilayer chip varistor is 2.0 pF or less, it is possible to cope with a high frequency of 100 MHz or more.

  The ESD tolerance was measured by an electrostatic discharge immunity test defined in IEC (International Electrotechnical Commission) standard IEC61000-4-2. In this example, when the ESD tolerance was 8 kV or more, it was determined that the ESD tolerance was sufficient, and “good (◯)” was determined. The reason why the criterion is 8 kV or more is that the level 4 of IEC61000-4-2 is satisfied.

  The multilayer chip varistors of Examples 1 to 8 have a capacitance C of 2.0 pF or less and an ESD resistance of 8 kV or more. In contrast, the multilayer chip varistors of Comparative Examples 1 and 3 have an ESD resistance of 8 kV or more, but have a capacitance C larger than 2.0 pF. In addition, although the multilayer chip varistors of Comparative Examples 1 and 3 have an electrostatic capacity C of 2.0 pF or less, the ESD resistance is lower than 8 kV. From the above, the effectiveness of the present invention was confirmed.

It is a figure explaining the section composition of the multilayer chip varistor concerning this embodiment. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a graph which shows Examples 1-8 by the multilayer chip varistor concerning this invention, and Comparative Examples 1-3.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer chip varistor, 3 ... Laminated body, 5 ... External electrode, 7 ... Varistor part, 9 ... Outer layer part, 11 ... Varistor layer, 11a ... Area | region which overlaps with a pair of internal electrode in a varistor layer, 13 ... Internal electrode, 13a: overlapping portion of internal electrodes, EL: electrode layer, S1: first green sheet, S2: second green sheet.

Claims (1)

A laminate having a varistor part including a varistor layer that exhibits voltage nonlinear characteristics and a pair of internal electrodes arranged so as to sandwich the varistor layer, and a pair of outer layer parts arranged so as to sandwich the varistor part When,
A pair of external electrodes formed on the laminate and connected to the pair of internal electrodes,
The multilayer chip varistor is characterized in that a relative dielectric constant of the outer layer portion is set smaller than a relative dielectric constant of a region overlapping the pair of internal electrodes in the varistor layer.

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