JP5301852B2 - Multilayer chip varistor - Google Patents

Multilayer chip varistor Download PDF

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JP5301852B2
JP5301852B2 JP2008042251A JP2008042251A JP5301852B2 JP 5301852 B2 JP5301852 B2 JP 5301852B2 JP 2008042251 A JP2008042251 A JP 2008042251A JP 2008042251 A JP2008042251 A JP 2008042251A JP 5301852 B2 JP5301852 B2 JP 5301852B2
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洋二 五味
高志 北見
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a laminated chip varistor improved in moisture resistance, plating resistance, and also improved in surge resistance and energy resistance. <P>SOLUTION: The laminated chip varistor is mainly composed of zinc oxide, wherein a borosilicate zinc-based glass (ZnO-SiC<SB>2</SB>-B<SB>2</SB>O<SB>3</SB>-BaO) and spherical Ag particles of 0.5-6.0 &mu;m in diameter are contained as the glass composition of its external electrode material. In concrete, the external electrode material is composed of 5-20 wt.% of borosilicate zinc-based glass and 80-95 wt.% of spherical Ag particles. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は積層チップバリスタに関し、例えば、電子回路等においてノイズやサージ等を除去するため、また、携帯電話機における静電気保護素子として使用される酸化亜鉛型積層チップバリスタに関するものである。   The present invention relates to a multilayer chip varistor, for example, a zinc oxide multilayer chip varistor for removing noise, surge, etc. in an electronic circuit or the like and used as an electrostatic protection element in a mobile phone.

電子機器や携帯端末等の高周波化、大容量化に伴い電子回路、電子部品等を各種サージやパルス性ノイズ等の異常電圧から保護するノイズ吸収素子として、また、ESD対策のためにバリスタ(酸化亜鉛型積層チップバリスタ)が使用されており、これにより機器の回路保護や動作の安定性、ノイズ規制への対応が可能となる。この種のバリスタは、一般的には半導体素子と並列に接合して用いられ、ESDや雷サージから回路を保護する安全部品としての役割を担う。酸化亜鉛型バリスタは、大きくディスク形状のバリスタと積層型のチップバリスタとに分けられ、その使い分けは、使用用途によって棲み分けされている。すなわち、主として雷サージや自動車等に代表されるロードダンプサージ等の大きな負荷からの保護回路にはディスク形状のバリスタが使用され、狭ピッチの面実装でESD等の比較的弱い負荷からの保護回路には積層型のチップバリスタが使用されてきた。   Varistors (oxidizers) are used as noise absorbing elements to protect electronic circuits, electronic components, etc. from abnormal voltages such as various surges and pulse noises, and to prevent ESD as electronic devices and mobile terminals increase in frequency and capacity. Zinc-type multilayer chip varistors) are used, which makes it possible to protect the circuit of the equipment, stabilize the operation, and comply with noise regulations. This type of varistor is generally used by being connected in parallel with a semiconductor element, and plays a role as a safety component for protecting a circuit from ESD or lightning surge. Zinc oxide type varistors are broadly divided into disc-shaped varistors and stacked chip varistors, and the proper use is divided according to the intended use. In other words, a disk-shaped varistor is used for a protection circuit from a large load such as a light dump surge or a load dump surge represented by an automobile, etc., and a protection circuit from a relatively weak load such as an ESD by surface mounting with a narrow pitch. In the past, multilayer chip varistors have been used.

このような各種機器の小型化、高周波化、電子化等に伴い、従来はディスク形状のバリスタを使用してきた車載等の高負荷回路の保護にチップバリスタが用いられることが多くなってきた。併せて、環境負荷試験の負荷率も厳しくなり、結果として絶縁性の低い酸化亜鉛バリスタ特有の耐湿寿命試験での劣化が起りやすくなった。これは、チップバリスタの電極間距離が、機器の小型化により狭くなり、酸化亜鉛という材料が本来的に持つ絶縁性が環境負荷率に十分でないことを意味している。また、車載特有のサージ負荷、エネルギー負荷の増加に伴い、外部電極が溶融し、素子の機能を十分に活用できないという問題も確認されている。   As these various devices are miniaturized, increased in frequency, digitized, etc., chip varistors are often used to protect high load circuits such as in-vehicle vehicles that have conventionally used disk-shaped varistors. At the same time, the load factor of the environmental load test became strict, and as a result, the deterioration in the moisture-resistant life test peculiar to zinc oxide varistors with low insulation properties was likely to occur. This means that the distance between the electrodes of the chip varistor becomes narrower due to the miniaturization of the device, and the inherent insulating property of the material called zinc oxide is not sufficient for the environmental load factor. In addition, as the surge load and energy load peculiar to the vehicle are increased, the problem that the external electrode melts and the function of the element cannot be fully utilized has been confirmed.

上記の耐湿負荷寿命試験の試験条件は、温度85℃、湿度85RH%の下、バリスタ電圧の0.85倍の電圧を1000時間、印加したときの電圧変化率が、バリスタ電圧±10%以内であることを要する。ここでバリスタ電圧とは、バリスタに1mAの電流が流れたときに示す電圧(通常、V1mAと表記する。)である。高圧バリスタ品、特にバリスタ電圧が50V以上のバリスタの場合、耐湿性における特性劣化がみられるため、耐湿負荷寿命特性の向上が急務となる。この耐湿負荷寿命特性を改善するには、(i)素体表面の絶縁抵抗を高抵抗化する、(ii)電極のイオン移動度を下げる(例えば、合金の使用や焼結緻密性の改善等)、といった方法が考えられる。 The test conditions of the moisture resistance load life test are as follows: the voltage change rate when a voltage of 0.85 times the varistor voltage is applied for 1000 hours under a temperature of 85 ° C. and a humidity of 85 RH% is within ± 10% of the varistor voltage. It needs to be. Here, the varistor voltage is a voltage (usually expressed as V 1 mA ) indicated when a current of 1 mA flows through the varistor. In the case of a high-voltage varistor product, particularly a varistor having a varistor voltage of 50 V or more, characteristic deterioration in moisture resistance is observed, so improvement of the moisture resistance load life characteristic is urgent. In order to improve the moisture resistance load life characteristics, (i) increase the insulation resistance of the element body surface, (ii) decrease the ion mobility of the electrode (for example, use of an alloy or improvement of sintered density) ), And so on.

そこで、バリスタの素体表面にガラス膜を形成することで、湿度等に対する耐環境特性を向上させたもの(例えば、特許文献1)や、バリスタの下地電極層にガラス層を形成するとともに外側電極層にガラスフリットを含有しない金属を使用し、さらに外側電極層の上に半田付け性の良好な金属からなるメッキ膜を形成することで、耐湿性を改善すると同時に外部電極における金属移動(マイグレーション)を防止したもの(例えば、特許文献2)がある。   Therefore, by forming a glass film on the surface of the varistor element, the environmental resistance against humidity and the like is improved (for example, Patent Document 1), and a glass layer is formed on the base electrode layer of the varistor and the outer electrode. By using a metal that does not contain glass frit for the layer, and forming a plating film made of a metal with good solderability on the outer electrode layer, the moisture resistance is improved and at the same time metal migration in the external electrode (migration) (For example, Patent Document 2).

特許第2560891号公報Japanese Patent No. 2560891 特開2003−68508号公報JP 2003-68508 A

しかしながら、上述した2つの方法は耐湿負荷寿命特性を向上させるために有効ではあるが、これらのうち、いずれか一方を改善すれば耐湿性の向上を図ることができるというものではない。確かに、素体表面の絶縁性を向上させるためにガラスコートの採用が望ましいといえるが、外部電極の構成に関し従来のバリスタは、実用上、生産等を考慮した十分な対応がなされていない。実際の問題として、素体表面の絶縁性をいくら改善しても、上述した耐湿負荷寿命試験において下地電極の銀(Ag)の形成が適切でなければ、イオンマイグレーションが容易に発生することが確認されている。   However, although the two methods described above are effective for improving the moisture resistance load life characteristics, if any one of them is improved, it is not possible to improve the moisture resistance. Certainly, it is desirable to use a glass coat in order to improve the insulation on the surface of the element body. However, conventional varistors have not been practically adequately taken into consideration in terms of production and the like regarding the configuration of the external electrodes. As a matter of fact, no matter how much the insulation of the element surface is improved, it is confirmed that ion migration easily occurs if the formation of silver (Ag) of the base electrode is not appropriate in the above-mentioned moisture resistance load life test. Has been.

本発明は、上述した課題に鑑みなされたものであり、その目的とするところは、外部電極の緻密性を向上させ、メッキ液の残渣による絶縁劣化を防ぎ、かつ大きいサージやエネルギー負荷でも電流を素早く拡散し、回路保護機能に優れた積層チップバリスタを提供することである。   The present invention has been made in view of the above-described problems, and the object of the present invention is to improve the denseness of the external electrodes, prevent insulation deterioration due to the residue of the plating solution, and to supply current even with a large surge or energy load. It is to provide a multilayer chip varistor that diffuses quickly and has an excellent circuit protection function.

上記の目的を達成し、上述した課題を解決する一手段として、例えば、以下の構成を備える。すなわち、本発明は、酸化亜鉛を主成分とする積層チップバリスタであって、外部電極材のガラス組成としてホウケイ酸亜鉛系ガラス(ZnO−SiO2−B23−BaO)と、0.5乃至6.0μmの球状Ag粒子とを含んでなり、前記ホウケイ酸亜鉛系ガラスは、酸化亜鉛(ZnO)を25乃至45重量%、酸化ケイ素(SiO2)を5乃至15重量%、酸化バリウム(BaO)を40乃至60重量%含むとともに結晶質であることを特徴とする。
例えば、上記外部電極材は、5乃至20重量%の上記ホウケイ酸亜鉛系ガラスと、80乃至95重量%の上記球状Ag粒子とからなることを特徴とする。また、例えば、さらに、酸化カルシウム(CaO)、酸化マグネシウム(MgO)、酸化アルミニウム(Al23)、酸化ジルコニウム(ZrO2)、酸化ストロンチウム(SrO)、酸化ナトリウム(Na2O)、酸化リチウム(Li2O)、酸化カリウム(K2O)の中から2種類以上を5重量%以下、含有することを特徴とする。
As a means for achieving the above object and solving the above-described problems, for example, the following configuration is provided. That is, the present invention is a multilayer chip varistor mainly composed of zinc oxide, and a zinc borosilicate glass (ZnO—SiO 2 —B 2 O 3 —BaO) as a glass composition of the external electrode material, 0.5 The zinc borosilicate glass comprises zinc oxide (ZnO) in an amount of 25 to 45 wt%, silicon oxide (SiO 2 ) in an amount of 5 to 15 wt% , and barium oxide (inclusive). It is characterized in that it contains 40 to 60% by weight of BaO) and is crystalline.
For example, the external electrode material is composed of 5 to 20 wt% of the zinc borosilicate glass and 80 to 95 wt% of the spherical Ag particles. Further, for example, calcium oxide (CaO), magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), strontium oxide (SrO), sodium oxide (Na 2 O), lithium oxide It is characterized by containing 5% by weight or less of two or more of (Li 2 O) and potassium oxide (K 2 O).

本発明によれば、外部電極の緻密性が向上し、耐湿性・耐メッキ性が改善され、かつ、緻密性の向上に伴う電界分散によるインパルス耐量の向上によって回路保護機能を高めた積層チップバリスタを提供できる。   According to the present invention, a multilayer chip varistor with improved circuit protection function due to improved impulse resistance due to electric field dispersion associated with improved denseness, with improved external electrode denseness, improved moisture resistance and plating resistance. Can provide.

本発明に係る実施の形態例を、添付図面等を参照して詳細に説明する。図1は、本発明の実施の形態例に係る酸化亜鉛系の積層チップバリスタの製造工程を示すフローチャートである。積層チップバリスタ(以下、単にバリスタとも呼ぶ。)の最初の製造工程(ステップS1)において、バリスタ素子の原料調合を行う。ここでは、バリスタ素子の材料としてメジアン平均粒径が3μm程度の酸化亜鉛(ZnO)、酸化ビスマス(Bi23)、酸化コバルト(CoO)、酸化マンガン(MnO)を秤量する。単位バリスタ電圧により酸化アンチモン(Sb23)や酸化クロム(Cr23)等の粒成長抑制物質を添加する。また、焼結助剤として酸化ケイ素(SiO2)、酸化ホウ素(B23)、酸化ゲルマニウム(GeO2)等のガラスを添加する。ステップS2では、ボールミル等で上記の原料を粉砕し、粒を揃えた後、ステップS3において、900℃で熱処理を行い、反応性や粒径を調整する(仮焼き)。そして、ステップS4で、仮焼きした原料をボールミル等により粉砕して粒を揃える。 Embodiments according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a flowchart showing a manufacturing process of a zinc oxide based multilayer chip varistor according to an embodiment of the present invention. In the first manufacturing process (step S1) of the multilayer chip varistor (hereinafter also simply referred to as “varistor”), the raw material of the varistor element is prepared. Here, zinc oxide (ZnO), bismuth oxide (Bi 2 O 3 ), cobalt oxide (CoO), and manganese oxide (MnO) having a median average particle size of about 3 μm are weighed as materials for the varistor element. A grain growth inhibitor such as antimony oxide (Sb 2 O 3 ) or chromium oxide (Cr 2 O 3 ) is added according to the unit varistor voltage. Further, glass such as silicon oxide (SiO 2 ), boron oxide (B 2 O 3 ), and germanium oxide (GeO 2 ) is added as a sintering aid. In step S2, the above-mentioned raw materials are pulverized by a ball mill or the like to prepare grains, and in step S3, heat treatment is performed at 900 ° C. to adjust the reactivity and particle size (calcination). In step S4, the calcined raw material is pulverized by a ball mill or the like to align the grains.

ステップS5では、スラリーを作製する。すなわち、重合度3000のPVB、フタル酸エステル系可塑剤、ポリカルボン酸系分散剤、PEG#600の離型材、エタノール/トルエン系希釈溶剤を加えてスラリーを作製する。続くステップS7では、ドクターブレードにより成膜し、10〜100μm程度のグリーンシートを作製する。ステップS8において、そのグリーンシート上にPtあるいはPd電極ペーストを印刷してコンデンサパターンを作製し、ホットプレス等で積層する。ステップS9では、積層体を製品のサイズに合わせて切削し(ダイシング)、ステップS11で、ダイシング後のバリスタ素子を500℃、10時間での脱バインダーを行う。その後、ステップS12において、950〜1300℃でバリスタ素子を焼成し、続くステップS13では、700℃でアニールを行う。   In step S5, a slurry is prepared. That is, a slurry is prepared by adding PVB having a polymerization degree of 3000, a phthalate ester plasticizer, a polycarboxylic acid dispersant, a release agent of PEG # 600, and an ethanol / toluene dilution solvent. In subsequent step S7, a film is formed by a doctor blade to produce a green sheet of about 10 to 100 μm. In step S8, a Pt or Pd electrode paste is printed on the green sheet to produce a capacitor pattern and laminated by hot pressing or the like. In step S9, the laminate is cut according to the size of the product (dicing), and in step S11, the varistor element after dicing is debindered at 500 ° C. for 10 hours. Thereafter, in step S12, the varistor element is baked at 950 to 1300 ° C., and in step S13, annealing is performed at 700 ° C.

ステップS15において、バリスタ素子にAgあるいはAg/Pdで端子電極(外部電極)を形成する。その後、ステップS16でNi層、Sn層の順にメッキを施す。そして、ステップS17で、作製されたバリスタのバリスタ電圧、漏れ電流等の電気的な特性を検測する。   In step S15, a terminal electrode (external electrode) is formed on the varistor element with Ag or Ag / Pd. Thereafter, plating is performed in the order of the Ni layer and the Sn layer in step S16. In step S17, electrical characteristics such as varistor voltage and leakage current of the manufactured varistor are measured.

本発明の実施の形態例に係る積層チップバリスタは、上述のようにZnOを主成分としており、その外部電極には、ホウケイ酸亜鉛系ガラスを含む、0.5〜6.0μmの球状Ag電極で構成される外部電極材を使用する。ここでは、バリスタ素子の端部に形成された外部電極を650℃以上の温度で焼き付けることで緻密化する。これにより、メッキ工程において外部電極内部へのメッキ液の侵入が抑えられるとともに、メッキ液残渣である電解液等も残らない、安定した外部電極を形成できる。さらには、サージやエネルギー負荷に対して電流拡散効率が上がり、外部電極の溶断も抑えることができる。なお、このような本実施の形態例に係る積層チップバリスタの耐メッキ性は、使用したホウケイ酸亜鉛系ガラスが結晶質であることも大きく作用している。   The multilayer chip varistor according to the embodiment of the present invention is mainly composed of ZnO as described above, and the external electrode thereof includes a spherical Ag electrode of 0.5 to 6.0 μm containing zinc borosilicate glass. An external electrode material composed of Here, the external electrode formed at the end of the varistor element is densified by baking at a temperature of 650 ° C. or higher. Accordingly, it is possible to form a stable external electrode that suppresses the penetration of the plating solution into the external electrode in the plating process and does not leave the electrolytic solution that is a plating solution residue. Furthermore, the current diffusion efficiency is increased against surges and energy loads, and the fusing of the external electrodes can be suppressed. Note that the plating resistance of the multilayer chip varistor according to the present embodiment is greatly affected by the fact that the zinc borosilicate glass used is crystalline.

次に、上記ホウケイ酸亜鉛系ガラスのガラス組成について説明する。本実施の形態例に係る積層チップバリスタのホウケイ酸亜鉛系ガラスは、主成分として酸化亜鉛(ZnO)を25〜45重量%、酸化ケイ素(SiO2)を5〜15重量%、酸化ホウ素(B23)を2〜13重量%、酸化バリウム(BaO)を40〜60重量%の組成比で構成されるホウケイ酸亜鉛系の結晶化ガラス組成物である。なお、これらに対して酸化カルシウム(CaO)、酸化マグネシウム(MgO)、酸化アルミニウム(Al23)、酸化ジルコニウム(ZrO2)、酸化ストロンチウム(SrO)、酸化ナトリウム(Na2O)、酸化リチウム(Li2O)、酸化カリウム(K2O)の中から2種類以上を5重量%以下、含有させてもよい。 Next, the glass composition of the zinc borosilicate glass will be described. The zinc borosilicate glass of the multilayer chip varistor according to this embodiment is composed of 25 to 45% by weight of zinc oxide (ZnO), 5 to 15% by weight of silicon oxide (SiO 2 ), and boron oxide (B 2 O 3 ) is a crystallized glass composition based on zinc borosilicate composed of 2 to 13% by weight and barium oxide (BaO) in a composition ratio of 40 to 60% by weight. In addition to these, calcium oxide (CaO), magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), strontium oxide (SrO), sodium oxide (Na 2 O), lithium oxide (Li 2 O), 5 wt% of two or more of the potassium oxide (K 2 O) or less, may be contained.

外部電極材の固形分比率は、5〜20重量%のホウケイ酸亜鉛(ZnO−SiO2−B23−BaO)系ガラスと、80〜95重量%の0.5〜6.0μmの球状Agで構成される。実際には、これらの固形分粉末にベンジルアルコール、ターピオネール、ブチルセルソルブ等の希釈溶剤と、エチルセルロース等の樹脂が添加され電極ペーストを構成している。 The solid content ratio of the external electrode material is 5 to 20% by weight of zinc borosilicate (ZnO—SiO 2 —B 2 O 3 —BaO) glass and 80 to 95% by weight of 0.5 to 6.0 μm spherical. It is composed of Ag. Actually, a diluent solvent such as benzyl alcohol, terpionol, or butyl cellosolve and a resin such as ethyl cellulose are added to these solid powders to constitute an electrode paste.

以下、酸化亜鉛系積層チップバリスタの適切な外部電極の形成について種々の検討を行った結果を詳細に説明する。なお、「適切な外部電極」であるためには、(i)イオンマイグレーションを牽引するメッキ液の侵入がなく、残渣もない緻密性の高い外部電極、(ii)メッキ浴のペーハー(pH)変化に対し、容易に溶解しないガラス組成、という構成条件を満たす必要がある。   Hereinafter, the results of various studies on the formation of an appropriate external electrode of the zinc oxide-based multilayer chip varistor will be described in detail. In order to be an “appropriate external electrode”, (i) a dense external electrode that does not penetrate the plating solution that pulls ion migration and has no residue, and (ii) changes in pH (pH) of the plating bath On the other hand, it is necessary to satisfy the constitutional condition that the glass composition does not dissolve easily.

<ガラス組成の検討>
本実施の形態例に係る積層チップバリスタの外部電極材のガラス組成として、緻密性に大きく影響する種々のガラスについて検討した。表1は、具体的な検討結果を示しており、ここでのサンプル評価数は100であり、個々の組成に対して以下の指標で評価、判断した。
(1)耐メッキ液:メッキ液によりガラスが侵食されるかどうかにつき、外観上、明らかな侵食が発生した確率を示す。
(2)半田濡れ性:外部電極の半田濡れ性がメッキ後に95%以上を満足できなかった確率を示す。
(3)耐湿負荷寿命:メッキ後に耐湿負荷寿命試験を実施し、それを1000時間行った結果、特性に不具合が生じた確率を示す。
(4)電気的特性:外部電極形成後にサージ耐量およびエネルギー耐量試験を行い、その限界値を示す。
<Examination of glass composition>
As the glass composition of the external electrode material of the multilayer chip varistor according to the present embodiment, various glasses that greatly affect the denseness were examined. Table 1 shows specific results of the examination. The number of sample evaluations here is 100, and evaluation and judgment were performed on the individual compositions with the following indices.
(1) Anti-plating solution: This indicates the probability of apparent erosion on the appearance of whether the glass is eroded by the plating solution.
(2) Solder wettability: indicates the probability that the solder wettability of the external electrode could not satisfy 95% or more after plating.
(3) Moisture resistance load life: The humidity resistance load life test is carried out after plating, and the result of performing the test for 1000 hours indicates the probability that a problem occurs in the characteristics.
(4) Electrical characteristics: Surge resistance and energy resistance tests are performed after external electrodes are formed, and the limit values are shown.

ガラス組成の検討にあたり、電極形成を以下の条件で行った。すなわち、Ag粒子を固形分として85重量%に固定し、ガラスを15重量%に固定した電極ペーストを作製した。Ag粒子は、微結晶状で粒径D50:0.2μmのものを使用した。これらAg粒子とガラス固形分100%に対し、樹脂として、エチルセルロースを8重量部、希釈溶剤としてターピオネール5重量部、ブチルセロソルブ5重量部、ベンジルアルコール5重量部を加えた。電極の塗布をチップスター方式で行い、製品サイズを2.0×1.2mmとした。また、電極の焼き付けは、使用するガラスの融点により異なるため統一せず、各ガラスの融点に合わせて設定した。さらに、Ni層メッキ、Sn層メッキは、すべて同じ条件で行った。   In the examination of the glass composition, the electrodes were formed under the following conditions. That is, an electrode paste in which Ag particles were fixed to 85% by weight as a solid content and glass was fixed to 15% by weight was produced. Ag particles having a microcrystalline shape and a particle size D50: 0.2 μm were used. 8 parts by weight of ethyl cellulose as a resin, 5 parts by weight of terpionol, 5 parts by weight of butyl cellosolve, and 5 parts by weight of benzyl alcohol were added as a resin to the Ag particles and the glass solid content of 100%. The electrode was applied by the chip star method, and the product size was set to 2.0 × 1.2 mm. Also, the baking of the electrodes was not unified because it differs depending on the melting point of the glass used, and was set according to the melting point of each glass. Furthermore, the Ni layer plating and the Sn layer plating were all performed under the same conditions.

Figure 0005301852
Figure 0005301852

ここでは、図1に示す工程で作製された積層チップバリスタ(バリスタ電圧が27V、製品サイズが2.0×1.2mm)のバリスタ素子に電極を形成した。また、内部電極総数を10層とし、1000℃で2時間、焼結し、700℃で10時間のアニール処理の後、バリスタ素子に外部電極を形成した。   Here, electrodes were formed on the varistor element of the multilayer chip varistor (varistor voltage is 27 V, product size is 2.0 × 1.2 mm) manufactured in the process shown in FIG. The total number of internal electrodes was 10 layers, sintered at 1000 ° C. for 2 hours, and annealed at 700 ° C. for 10 hours, and then external electrodes were formed on the varistor element.

上記検討の結果、酸化亜鉛(ZnO)を入れて結晶化したガラスは、耐メッキ液の値が高く、絶縁性に優れていることが判明した。これは、ガラスが結晶化しているということと、線膨張係数が素体に適合していることによると解される。また、ガラスに酸化バリウム(BaO)を入れた場合、ガラスが電極表面に著しく浮く現象が抑えられ、半田濡れ性において優れた結果が得られた。これは、Baイオンのイオン半径が大きいため、流動性がCa等に比べ低いことによると考えられる。結果的には、4種類のガラス組成のうち、Baを入れたホウケイ酸亜鉛系ガラスが最も良好な特性を示した。なお、各ガラス組成における電気的特性(サージ耐量およびエネルギー耐量)に差異および改善は見られなかった。   As a result of the above examination, it has been found that glass crystallized with zinc oxide (ZnO) has a high value of the plating solution resistance and is excellent in insulation. This is understood to be due to the fact that the glass is crystallized and that the linear expansion coefficient is adapted to the element body. Further, when barium oxide (BaO) was added to the glass, the phenomenon that the glass remarkably floated on the electrode surface was suppressed, and an excellent result in solder wettability was obtained. This is considered to be due to the fact that the ionic radius of Ba ions is large, so that the fluidity is lower than that of Ca or the like. As a result, among the four glass compositions, the zinc borosilicate glass containing Ba showed the best characteristics. In addition, the difference and improvement were not seen by the electrical property (surge tolerance and energy tolerance) in each glass composition.

<Ag粒子の検討>
上述したようにガラス組成の検討の結果、Ba入りのホウケイ酸亜鉛系ガラスにおいて、各信頼性の評価項目で良好な結果が得られたため、緻密性を確保する目的で、他の構成要素であるAg粒子について検討した。表2は、ガラス組成の検討と同様の項目でAg粒子について検討した結果を示している。
<Examination of Ag particles>
As described above, as a result of the examination of the glass composition, in the borosilicate zinc-containing glass containing Ba, good results were obtained for each reliability evaluation item. Therefore, in order to ensure denseness, it is another component. Ag particles were examined. Table 2 shows the results of studying Ag particles using the same items as those for studying the glass composition.

Figure 0005301852
Figure 0005301852

上記検討の結果、Ba入りのホウケイ酸亜鉛ガラスを使用し、かつ、球状のAg粒子(0.5〜6.0μm)を用いることで、すべての評価項目において良好な結果を得ることができた。すなわち、ホウケイ酸亜鉛(ZnO−SiO2−B23−BaO)系ガラスを用い、0.5〜6.0μmの球状Ag粒子を使用することで、ガラスの耐湿性・耐メッキ性が改善され、サージ限界およびエネルギー限界においても特性の向上が確認できた。なお、具体的なホウケイ酸亜鉛(ZnO−SiO2−B23−BaO)系ガラスの組成は、その主成分として酸化亜鉛(ZnO)を25〜45重量%、酸化ケイ素(SiO2)を5〜15重量%、酸化ホウ素(B23)を2〜13重量%、酸化バリウム(BaO)を40〜60重量%の組成比で構成される。また、酸化カルシウム(CaO)、酸化マグネシウム(MgO)、酸化アルミニウム(Al23)、酸化ジルコニウム(ZrO2)、酸化ストロンチウム(SrO)、酸化ナトリウム(Na2O)、酸化リチウム(Li2O)、酸化カリウム(K2O)の中から2種類以上を5重量%以下、含有させてもよい。 As a result of the above studies, good results were obtained in all evaluation items by using Ba-containing zinc borosilicate glass and using spherical Ag particles (0.5 to 6.0 μm). . That is, by using zinc borosilicate (ZnO—SiO 2 —B 2 O 3 —BaO) glass and using spherical Ag particles of 0.5 to 6.0 μm, the moisture resistance and plating resistance of the glass are improved. It was confirmed that the characteristics were improved even at the surge limit and energy limit. The specific composition of zinc borosilicate (ZnO—SiO 2 —B 2 O 3 —BaO) glass is composed of 25 to 45 wt% zinc oxide (ZnO) as its main component and silicon oxide (SiO 2 ). The composition ratio is 5 to 15% by weight, boron oxide (B 2 O 3 ) is 2 to 13% by weight, and barium oxide (BaO) is 40 to 60% by weight. In addition, calcium oxide (CaO), magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), strontium oxide (SrO), sodium oxide (Na 2 O), lithium oxide (Li 2 O) ), 2% or more of potassium oxide (K 2 O) may be contained in an amount of 5% by weight or less.

<固形分比率の検討>
上記の検討により、ガラスの組成とAg粒子の形態により各種信頼性と電気的特性において優位性を確認できたが、安定した信頼性と電気的特性は、組成のみで決まるものではなく、配合比による緻密性により得られる。そこで、上記の検討で得られたガラスとAg粒子を組み合わせた固形分比率について各特性評価を行った結果を表3に示す。
<Examination of solid content ratio>
As a result of the above examination, we were able to confirm the superiority in various reliability and electrical characteristics depending on the composition of glass and the form of Ag particles, but stable reliability and electrical characteristics are not determined only by the composition, but the mixing ratio It is obtained by the denseness by. Therefore, Table 3 shows the results of each characteristic evaluation on the solid content ratio obtained by combining the glass and Ag particles obtained in the above examination.

Figure 0005301852
Figure 0005301852

上記検討の結果、ガラス固形分%が20重量%を越えると、著しい外部電極表面へのガラスの析出により半田濡れ性が大きく劣化することが分かった。それとともに、耐湿負荷寿命と電気的特性も僅かであるが劣化した。なお、ガラス固形分が0重量%の場合はAg電極そのものであるため、いわゆる半田食われを起し、評価に至らなかった。   As a result of the above examination, it was found that when the glass solid content% exceeds 20% by weight, the solder wettability is greatly deteriorated due to the remarkable glass deposition on the surface of the external electrode. At the same time, the moisture resistance load life and electrical characteristics were slightly deteriorated. When the glass solid content was 0% by weight, it was an Ag electrode itself, so-called solder erosion occurred, and the evaluation was not achieved.

以上説明したように、積層チップバリスタの外部電極材のガラス組成としてホウケイ酸亜鉛(ZnO−SiO2−B23−BaO)系ガラスと、0.5〜6.0μmの球状Ag粒子とを固形分比率としてガラス/Ag粒子=5〜20/80〜95の範囲とし、樹脂と希釈溶剤を添加してペースト化を行って、外部電極を焼き付け形成することで、外部電極の緻密性が向上し、耐湿性・耐メッキ性を改善できるとともに、サージ耐量およびエネルギー耐量も向上させることができる。また、耐メッキ性の改善により、イオンマイグレーションによる絶縁劣化を抑え、耐湿寿命が向上する。 As described above, zinc borosilicate (ZnO—SiO 2 —B 2 O 3 —BaO) glass and spherical Ag particles of 0.5 to 6.0 μm are used as the glass composition of the external electrode material of the multilayer chip varistor. The solid content ratio is in the range of glass / Ag particles = 5-20 / 80-95, the resin and diluent solvent are added to form a paste, and the external electrode is baked and formed, thereby improving the density of the external electrode. In addition, moisture resistance and plating resistance can be improved, and surge resistance and energy resistance can be improved. In addition, by improving the plating resistance, insulation deterioration due to ion migration is suppressed, and the moisture resistance life is improved.

本発明の実施の形態例に係る酸化亜鉛系の積層チップバリスタの製造工程を示すフローチャートである。It is a flowchart which shows the manufacturing process of the zinc oxide type multilayer chip varistor which concerns on the embodiment of this invention.

Claims (3)

酸化亜鉛を主成分とする積層チップバリスタであって、
外部電極材のガラス組成としてホウケイ酸亜鉛系ガラス(ZnO−SiO2−B23−BaO)と、0.5乃至6.0μmの球状Ag粒子とを含んでなり、前記ホウケイ酸亜鉛系ガラスは、酸化亜鉛(ZnO)を25乃至45重量%、酸化ケイ素(SiO2)を5乃至15重量%、酸化バリウム(BaO)を40乃至60重量%含むとともに結晶質であることを特徴とする積層チップバリスタ。
A laminated chip varistor mainly composed of zinc oxide,
Zinc borosilicate glass (ZnO—SiO 2 —B 2 O 3 —BaO) as a glass composition of the external electrode material and spherical Ag particles of 0.5 to 6.0 μm, the zinc borosilicate glass Is a crystalline layer containing 25 to 45% by weight of zinc oxide (ZnO), 5 to 15% by weight of silicon oxide (SiO 2 ), and 40 to 60% by weight of barium oxide (BaO). Chip varistor.
前記外部電極材は、5乃至20重量%の前記ホウケイ酸亜鉛系ガラスと、80乃至95重量%の前記球状Ag粒子とからなることを特徴とする請求項1に記載の積層チップバリスタ。 2. The multilayer chip varistor according to claim 1, wherein the external electrode material comprises 5 to 20 wt% of the zinc borosilicate glass and 80 to 95 wt% of the spherical Ag particles. さらに、酸化カルシウム(CaO)、酸化マグネシウム(MgO)、酸化アルミニウム(Al23)、酸化ジルコニウム(ZrO2)、酸化ストロンチウム(SrO)、酸化ナトリウム(Na2O)、酸化リチウム(Li2O)、酸化カリウム(K2O)の中から2種類以上を5重量%以下、含有することを特徴とする請求項2に記載の積層チップバリスタ。 Further, calcium oxide (CaO), magnesium oxide (MgO), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), strontium oxide (SrO), sodium oxide (Na 2 O), lithium oxide (Li 2 O) The multilayer chip varistor according to claim 2, further comprising 2% or more of potassium oxide (K 2 O) in an amount of 5% by weight or less.
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