JP2006269985A - Multilayer chip varistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer chip varistor in which leakage current can be reduced while ensuring good varistor characteristics. <P>SOLUTION: The multilayer chip varistor 1 comprises a multilayer body 3 having a varistor layer 11 exhibiting voltage nonlinear characteristics and internal electrodes 13, 14, and an external electrode 5 formed on the multilayer body 3 and being connected with the internal electrodes 13, 14. The internal electrodes 13, 14 are provided to sandwich the varistor layer 11, the external electrode 5 is provided to be connected with the internal electrodes 13, 14, respectively, and holes 13a, 14a penetrating in the layer direction of the multilayer body 3 are formed in the internal electrodes 13, 14. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a multilayer chip varistor.

A varistor is known which is a voltage non-linear resistor element including an external terminal electrode sandwiched between voltage non-linear resistor layers with an internal electrode and electrically connected to the internal electrode (see, for example, Patent Document 1 below). .
JP 2002-246207 A

  In the varistor described in Patent Document 1, it is known that a leakage current is generated. The leakage current is caused by the internal electrodes facing each other. However, in the varistor, the internal electrodes must be disposed facing each other. Therefore, the leakage current cannot be eliminated by disposing the internal electrodes facing each other. In addition, even if the internal electrodes are not arranged opposite to each other, the leakage current may be reduced if the overlapping degree of the opposed portions is reduced. In that case, however, desired varistor characteristics (for example, electrostatic capacity and surge resistance) ) May not be obtained.

  Accordingly, an object of the present invention is to provide a multilayer chip varistor capable of reducing leakage current while ensuring good varistor characteristics.

  The multilayer chip varistor of the present invention is a multilayer chip varistor comprising a multilayer body having a varistor layer and internal electrodes that exhibit voltage nonlinear characteristics, and an external electrode formed in the multilayer body and connected to the internal electrodes. The internal electrode is provided so as to sandwich the varistor layer, the external electrode is provided to be connected to the internal electrode, and at least one of the internal electrodes has a hole that penetrates in the stacking direction of the laminate. Is formed.

  According to the present invention, since the hole is formed in the internal electrode connected to the external electrode, the actual area of the internal electrode can be reduced without changing the area surrounded by the outer periphery of the internal electrode. Accordingly, since the electric field diffuses, the change in capacitance can be reduced, and the leakage current proportional to the actual area of the internal electrode can be reduced.

  In the present invention, it is also preferable that the hole is formed at least in a region where the internal electrodes overlap. Since the hole is formed in the region where the internal electrodes overlap, the leakage current can be reduced more effectively.

  In the present invention, it is also preferable that the ratio of the area of the region where the hole is not formed to the area where the outer periphery surrounds the internal electrode in which the hole is formed is 45% or more and less than 90%. . When the coverage, which is the ratio of the area of the region where the hole is not formed, to the area of the region surrounded by the outer periphery of the internal electrode is within 45 to 90%, the change in capacitance is suppressed and the leakage current is reduced. The balance with the decrease can be suitably maintained.

  According to the present invention, since the electric field diffuses, the change in capacitance can be reduced, and the leakage current proportional to the actual area of the electrode layer can be reduced. Therefore, it is possible to provide a multilayer chip varistor that can reduce leakage current while ensuring good varistor characteristics.

  The teachings of the present invention can be readily understood by considering the following detailed description with reference to the accompanying drawings shown for illustration only. Subsequently, embodiments of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals, and redundant description is omitted.

  A multilayer chip varistor according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram showing a cross-sectional configuration along the stacking direction of the multilayer chip varistor 1 in the present embodiment. FIG. 2 is a diagram showing a cross-sectional configuration of the multilayer chip varistor 1 in a direction crossing the stacking direction.

  As shown in FIG. 1, the multilayer chip varistor 1 includes a multilayer body 3 and a pair of external electrodes 5 that are respectively formed on opposite end surfaces of the multilayer body 3. The laminate 3 includes a varistor part 7 and a pair of outer layer parts 9 arranged so as to sandwich the varistor part 7, and is configured by laminating the varistor part 7 and the pair of outer layer parts 9. Yes. The laminate 3 has a rectangular parallelepiped shape, and is set to have a length of 2.0 mm, a width of 1.2 mm, and a height of 1.2 mm. The multilayer chip varistor 1 of this embodiment is a so-called 2012 type multilayer chip varistor.

  The varistor portion 7 includes a varistor layer 11 that exhibits varistor characteristics, and a pair of internal electrodes 13 and 14 that are disposed so as to sandwich the varistor layer 11. In the varistor portion 7, the varistor layers 11 and the internal electrodes 13 and 14 are alternately stacked. A region 11 a overlapping the pair of internal electrodes 13 and 14 in the varistor layer 11 functions as a region that develops varistor characteristics.

  The varistor layer 11 contains ZnO (zinc oxide) as a main component, and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K) as subcomponents. , Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and the like, and element bodies containing these oxides. In the present embodiment, the varistor layer 11 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, the region 11a of the varistor layer 11 that overlaps the pair of internal electrodes 13 and 14 has a region that is composed mainly of ZnO and is composed of an element body containing Pr.

  Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. Although the content rate of ZnO in the varistor layer 11 is not particularly limited, it is generally 99.8 to 69.8% by mass when the total material constituting the varistor layer 11 is 100% by mass. The thickness of the varistor layer 11 is about 10 to 100 μm.

The pair of internal electrodes 13, 14 are provided substantially in parallel so that one end of each of the internal electrodes 13, 14 is alternately exposed on the end surface facing the stacked body 3. The internal electrodes 13 and 14 are electrically connected to the external electrode 5 at each one end. The internal electrodes 13 and 14 include a conductive material. The conductive material contained in the internal electrodes 13 and 14 preferably contains Pd. In the present embodiment, the internal electrodes 13 and 14 are made of Pd or an Ag—Pd alloy. The internal electrodes 13 and 14 have a thickness of about 0.5 to 5 μm. The width of the internal electrodes 13 and 14 is about 300 to 1000 μm. The area of the portion L where the internal electrodes 13 and 14 overlap each other (the overlapping area of the internal electrodes 13 and 14) is ² to 50 mm ^{2 when} viewed from the stacking direction of the stacked body 3 (the thickness direction of the varistor layer 11). .

  As shown in FIG. 2, each of the internal electrodes 13 and 14 is formed with a hole 13 a and a hole 14 a penetrating in the stacking direction of the stacked body 3. In the present embodiment, the holes 13a and 14a are formed in both the internal electrodes 13 and 14, but may be formed in only one of them. In the present embodiment, the holes 13a and 14a are formed over the entire internal electrodes 13 and 14, but the internal electrodes 13 and 14 are formed only in a region where the internal electrodes 13 and 14 overlap, that is, a region corresponding to L. Also good.

  The internal electrodes 13 and 14 are formed so that the ratio (coverage) of the area where the holes 13a and 14a are not formed to the area surrounded by the outer periphery thereof is 45% or more and less than 90%. The coverage is more preferably 60% or more and less than 90%.

  Here, the relationship between the coverage and the leakage current is shown in FIG. The relationship shown in FIG. 3 is represented by a leakage current when a DC voltage of 5 V is applied to a multilayer chip varistor with a changed coverage. Since the element resistance value of the multilayer chip varistor is preferably 5 MΩ or less, the leakage current is preferably 1 μA or less when a DC voltage of 5 V is applied. Therefore, from the relationship shown in FIG. 3, the coverage is preferably less than 90%.

  Next, FIG. 4 shows the relationship between the coverage rate and the capacitance change rate. The relationship shown in FIG. 4 indicates the rate of change in capacitance with respect to the change in coverage by measuring the capacitance at 1 MHz for each multilayer chip varistor with a changed coverage. As shown in FIG. 4, when the coverage is less than 45%, the capacitance change rate becomes −10% or less. Therefore, the coverage is preferably 45% or more.

  Then, the relationship between a coverage and a surge withstand change rate is shown in FIG. The relationship shown in FIG. 5 shows the rate of change in surge resistance with respect to the change in coverage by measuring the surge resistance for each of the multilayer chip varistors with varying coverage. As shown in FIG. 5, when the coverage is less than 60%, the surge withstand change rate is −10% or less, and therefore, the coverage is more preferably 60% or more.

From the relationship between the above-described coverage, leakage current, capacitance change rate, and surge withstand change rate, the coverage is preferably 45% or more and less than 90%, more preferably 60% or more and less than 90%. preferable. The above-mentioned coverage is as follows. The multilayer chip varistor is maintained in a 5% H ₂ atmosphere for 5 hours, and Pd in the internal electrode absorbs hydrogen to generate internal stress. Is measured by image analysis.

  Returning to FIG. 1 and FIG. 2, the outer layer portion 9 will be described. Similar to the varistor layer 11, the outer layer portion 9 contains ZnO as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, and alkali metals as subcomponents. It consists of elemental bodies including simple metals such as elements (K, Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and oxides thereof. In the present embodiment, the outer layer portion 9 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, the outer layer portion 9 has a region composed of an element body containing Pr as a main component and containing Pr. The thickness of the outer layer portion 9 is about 20 to 1200 μm.

  The external electrode 5 is provided so as to cover both end faces of the multilayer body 3. The external electrode 5 is made of a metal material that can be electrically connected to a metal such as Pd constituting the internal electrodes 13 and 14 in an excellent manner. For example, Ag is suitable as a material for the external electrode because it has good electrical connectivity with the internal electrodes 13 and 14 made of Pd and has good adhesion to the end face of the laminate 3. . The thickness of the external electrode 5 is about 10 to 50 μm.

  On the surface of the external electrode 5, a Ni plating layer (not shown) having a thickness of about 0.5 to 2 μm and a Sn plating layer (not shown) having a thickness of about 2 to 6 μm are provided so as to cover the external electrode. It is formed in order. These plating layers are formed mainly for the purpose of improving solder heat resistance and solder wettability when the multilayer chip varistor 1 is mounted on a substrate or the like by solder reflow.

  The plating layer formed on the surface of the external electrode 5 is not necessarily limited to the combination of materials described above as long as the purpose of improving solder heat resistance and solder wettability is achieved. Other materials that can form the plating layer include, for example, Sn—Pb alloy and the like, and may be used in combination with the above-described Ni or Sn.

  Subsequently, a method for manufacturing the multilayer chip varistor 1 of the present embodiment will be described with reference to FIGS. 1, 6 and 7. FIG. FIG. 6 is a diagram for explaining each step of the manufacturing method of the multilayer chip varistor 1 of the present embodiment. FIG. 7 is a view for explaining a method of manufacturing the multilayer chip varistor 1 of the present embodiment.

  First, ZnO which is a main component constituting the varistor layer 11 and the outer layer part 9, and a small amount of additives such as Pr, Co, Cr, Ca, Si, K and Al metals or oxides so as to have a predetermined ratio. After each weighing, each component is mixed to adjust the varistor material (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  This slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 15 to 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S103).

  Next, paste-like Pd, which is a material for the internal electrodes 13 and 14, is applied on the green sheet in a predetermined pattern by a printing method such as screen printing, and then the conductive paste is dried to have a predetermined pattern. The electrode layer which has is formed (step S105). Note that 10-30% of the varistor material used in step S101 is added to the paste-like Pd used in step S105. In accordance with this addition ratio, the internal electrodes 13 and 14 are formed with island-shaped portions made of a varistor material, resulting in holes 13a and 14a that are substantially free of Pd.

  Note that the number, shape, dimensions, and the like of the holes 13a and 14a can be controlled by changing the particle size and amount of the varistor material added in step S105. The method of forming the holes 13a and 14a is not limited to this, and holes having a desired number, shape, size, and the like may be formed in advance on a screen printing plate for screen printing.

  Next, the green sheet on which the electrode layer is formed and the green sheet on which the electrode layer is not formed are stacked in a predetermined order to form a sheet laminate (step S107). The sheet laminate thus obtained is cut into a desired size to obtain a green chip (step S109). In the obtained green chip, as shown in FIG. 7, a plurality of green sheets S1 on which no electrode layers EL are formed, a green sheet S2 on which electrode layers EL are formed, and a plurality on which electrode layers EL are not formed. These sheets S1 to S3 are stacked in the order of a green sheet S1, a green sheet S3 on which an electrode layer EL is formed, and a plurality of green sheets S1 on which no electrode layer EL is formed. Note that the green sheet S1 on which the electrode layer EL is not necessarily formed is not necessarily laminated between the green sheet S2 and the green sheet S3.

  Next, the green chip was subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and further fired at 1000 to 1400 ° C. for about 0.5 to 8 hours. (Step S111), and the laminate 3 is obtained. By this firing, the green sheets S1 and S3 between the electrode layers EL in the green chip become the varistor layer 11. The electrode layer EL becomes the internal electrodes 13 and 14. The laminated body 3 thus obtained may be subjected to a smoothing process on the surface of the element by putting it in a polishing container together with an abrasive or the like before performing the next step.

  Next, an external electrode paste mainly containing Ag is applied to both ends of the laminate 3 so as to be in contact with each of the pair of internal electrodes 13, and then the paste is heated (baked) at about 550 to 850 ° C. ) Processing is performed to form a pair of external electrodes 5 made of Ag (step S115). Then, a Ni plating layer and a Sn plating layer are sequentially laminated on the outer surface of the external electrode 5 by electrolytic plating or the like. Thus, the multilayer chip varistor 1 is obtained.

  According to this embodiment, since the holes 13a and 14a are formed in the internal electrodes 13 and 14 connected to the external electrode 5, the internal electrodes can be formed without changing the area surrounded by the outer periphery of the internal electrodes 13 and 14. The actual area of 13, 14 can be reduced. Therefore, since the electric field diffuses, the change in capacitance can be reduced, and the leakage current proportional to the actual area of the internal electrodes 13 and 14 can be reduced.

  Further, since the varistor material enters the holes 13a and 14a formed in the internal electrodes 13 and 14, respectively, peeling on the internal electrode surface can be effectively suppressed by a so-called anchor effect.

  In the present embodiment, the holes 13a and 14a formed in the internal electrodes 13 and 14 are irregular holes. However, the shape may be any of circular holes, mesh holes, and groove holes. It is possible to adopt without.

It is a figure which shows the cross-sectional structure of the multilayer chip | tip varistor which is embodiment of this invention. It is a figure which shows the cross-sectional structure of the multilayer chip | tip varistor which is embodiment of this invention. It is a figure which shows the relationship between the coverage and the leakage current in the multilayer chip varistor which is embodiment of this invention. It is a figure which shows the relationship between the coverage and the electrostatic capacitance change rate in the multilayer chip varistor which is embodiment of this invention. It is a figure which shows the relationship between the coverage in the multilayer chip varistor which is embodiment of this invention, and surge withstand capability change rate. It is a figure for demonstrating each process of the manufacturing method of the multilayer chip varistor which is embodiment of this invention. It is a figure for demonstrating the manufacturing method of the multilayer chip varistor which is embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer chip varistor, 3 ... Laminated body, 5 ... External electrode, 7 ... Varistor part, 9 ... Outer layer part, 11 ... Varistor layer, 13, 14 ... Internal electrode, 13a, 14a ... Hole part.

Claims (3)

A multilayer chip varistor comprising: a laminated body having a varistor layer that exhibits voltage nonlinear characteristics and an internal electrode; and an external electrode that is formed in the laminated body and connected to the internal electrode,
The internal electrode is provided so as to sandwich the varistor layer,
The external electrode is provided to be connected to the internal electrode,
At least one of the internal electrodes is formed with a hole penetrating in the stacking direction of the stacked body. 2. The multilayer chip varistor according to claim 1, wherein the hole is formed at least in a region where the internal electrodes overlap. The internal electrode in which the hole is formed is characterized in that the ratio of the area of the region where the hole is not formed to the area of the region surrounded by the outer periphery is 45% or more and less than 90%, The multilayer chip varistor according to claim 1 or 2.

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