JP5304772B2 - Chip varistor and method of manufacturing chip varistor - Google Patents

Description

  The present invention relates to a chip varistor and a method for manufacturing a chip varistor.

  As a chip varistor, a varistor element having a varistor layer and an internal electrode arranged so as to sandwich the varistor layer, a terminal electrode arranged to be connected to an internal electrode corresponding to an end of the varistor element, There is known a multilayer chip varistor provided with (for example, see Patent Document 1). In the multilayer chip varistor, a region sandwiched between internal electrodes in the varistor layer functions as a region that develops a voltage nonlinear characteristic (hereinafter also referred to as “varistor characteristic”).

JP 2002-246207 A

  However, the multilayer chip varistor described in Patent Document 1 has the following problems because it includes an internal electrode.

  In a multilayer chip varistor, when a surge voltage such as ESD (Electrostatic Discharge) is applied, the electric field distribution in the portion where the internal electrodes overlap with each other is concentrated at the end of the portion where the internal electrodes overlap each other. When the electric field distribution of the portion where the internal electrodes overlap with each other is concentrated at the end, the ESD tolerance (hereinafter referred to as “ESD tolerance”) is drastically reduced.

  A laminated chip varistor is generally formed by forming an electrode pattern serving as an internal electrode on a varistor green sheet serving as a varistor layer, and laminating a varistor green sheet formed with an electrode pattern serving as an internal electrode to obtain a laminate, The laminate is obtained by cutting and firing, and then forming a terminal electrode. For this reason, in the multilayer chip varistor, the area of the portion where the internal electrodes overlap with each other is caused by factors such as the accuracy of electrode pattern formation on the varistor green sheet, misalignment of the varistor green sheet, or misalignment of the laminate. There is. When the area of the portion where the internal electrodes overlap each other varies, the capacitance generated by the portion where the internal electrodes overlap each other varies.

  As described above, since the multilayer chip varistor includes the internal electrode, it is difficult to suppress the variation in capacitance while maintaining good ESD tolerance.

  An object of the present invention is to provide a chip varistor and a method for manufacturing a chip varistor that can suppress variation in capacitance while maintaining good ESD tolerance without providing an internal electrode. is there.

  The chip varistor according to the present invention is composed of a sintered body mainly composed of ZnO, and has a varistor part that exhibits voltage nonlinear characteristics, and a first main surface that is disposed across the varistor part and connected to the varistor part. A plurality of conductive portions each having a second main surface facing the first main surface, and a plurality of terminal electrodes connected to the second main surface of the plurality of conductive portions.

  In the chip varistor according to the present invention, the varistor part is sandwiched and connected between the conductive parts, and the varistor part functions as a region that exhibits varistor characteristics. That is, the chip varistor of the present invention exhibits varistor characteristics without providing an internal electrode, unlike the multilayer chip varistor described above. For this reason, even when a surge voltage such as ESD is applied, a portion where the electric field distribution is concentrated does not occur in the varistor part, and the ESD tolerance does not decrease.

  In the present invention, since the chip varistor does not include the internal electrode, there is no variation in capacitance caused by the internal electrode. For this reason, it can suppress that dispersion | variation arises in an electrostatic capacitance.

  The conductive part may contain ZnO as a main component. In this case, since the varistor part and the conductive part are made of a sintered body containing ZnO as a main component, the connection strength at the interface between the varistor part and the conductive part becomes strong. As a result, the connection between the varistor part and the conductive part becomes good, and the occurrence of peeling between the varistor part and the conductive part can be suppressed.

  Furthermore, the varistor portion contains at least one element selected from the group consisting of rare earth metals and Bi as subcomponents, and at least one of the plurality of conductive portions substantially includes rare earth metals and Bi as subcomponents. You may consist of the sintered compact which is not contained in. In this case, since the sintered body constituting the conductive portion does not substantially contain rare earth metal and Bi, the varistor characteristics are hardly exhibited, and the sintered body has a relatively high conductivity. Therefore, the function as an electrode is not hindered in the conductive part.

  The conductive part may be made of a composite material of a metal and a metal oxide. In this case, since the heat in the chip varistor is easily radiated through the conductive portion, a chip varistor with excellent heat dissipation can be obtained. Since the varistor part and the conductive part contain a metal oxide, the connection strength at the interface between the varistor part and the conductive part becomes strong. As a result, the connection between the varistor part and the conductive part becomes good, and the occurrence of peeling between the varistor part and the conductive part can be suppressed.

  The method for manufacturing a chip varistor according to the present invention is such that the conductor green layer is formed such that the varistor green layer serving as a varistor part that has ZnO as a main component and exhibits voltage nonlinearity is sandwiched between the conductor green layers serving as the conductive parts. And a step of preparing a laminated body in which the varistor green layer is laminated, a step of cutting the laminated body to obtain a plurality of green body bodies, and firing a plurality of green body bodies so that the varistor part is a conductive part. A step of obtaining a plurality of element bodies sandwiched, and a step of forming terminal electrodes on both end sides in a direction in which the conductive part sandwiches the varistor part in each of the plurality of element bodies. .

  According to the chip varistor manufacturing method of the present invention, it is possible to easily provide a chip varistor that does not have an internal electrode and can suppress variation in capacitance while maintaining good ESD tolerance. Can be manufactured.

  According to the present invention, it is possible to provide a chip varistor and a method of manufacturing a chip varistor that can suppress variation in capacitance while maintaining good ESD tolerance without providing an internal electrode. it can.

It is a perspective view which shows the chip varistor concerning this embodiment. It is a figure explaining the section composition of the chip varistor concerning this embodiment. It is a figure for demonstrating the manufacturing process of the chip varistor which concerns on this embodiment. It is a figure for demonstrating the manufacturing process of the chip varistor which concerns on this embodiment. It is a perspective view which shows the chip varistor which concerns on the modification of this embodiment. It is a figure explaining the section composition of the chip varistor concerning the modification of this embodiment. It is typical sectional drawing which shows the conduction path in the composite part of the chip varistor concerning this embodiment. It is a figure for demonstrating the manufacturing process of the chip varistor which concerns on the modification of this embodiment. It is a figure for demonstrating the manufacturing process of the chip varistor which concerns on the modification of this embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  First, the configuration of the chip varistor 1 according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a perspective view showing a chip varistor according to the present embodiment. FIG. 2 is a diagram illustrating a cross-sectional configuration of the chip varistor according to the present embodiment.

  As shown in FIG. 1, the chip varistor 1 includes a substantially rectangular parallelepiped element body 3 and a pair of terminal electrodes 5 formed at both ends of the element body 3. The chip varistor 1 is a chip varistor of a very small size (so-called 0402 size) having a length in the Y direction of 0.4 mm, a height in the Z direction of 0.2 mm, and a width in the X direction of 0.2 mm, for example. .

  The element body 3 includes a varistor portion 7 and a plurality of (in this embodiment, two) conductive portions 9. The element body 3 has, as outer surfaces, square end faces 3a and 3b facing each other and four side faces 3c to 3f orthogonal to the end faces 3a and 3b. The four side surfaces 3c to 3f extend so as to connect the end surfaces 3a and 3b.

  As shown in FIGS. 1 and 2, the varistor portion 7 is a rectangular parallelepiped-shaped portion positioned substantially at the center of the element body 3 and is made of a sintered body (semiconductor ceramic) that exhibits varistor characteristics. The varistor portion 7 includes a pair of main surfaces 7a and 7b facing in the thickness direction (Y direction in the figure). The thickness of the varistor part 7 is set to about 5 to 200 μm, for example.

  The varistor part 7 contains ZnO (zinc oxide) as a main component, and Co, rare earth metal elements, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K) as subcomponents. , Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and the like, and oxides thereof. In this embodiment, the varistor part 7 contains Co, Pr, Cr, Ca, K, and Al as subcomponents. The ZnO content in the varistor part 7 is not particularly limited, but is usually 99.8 to 69.0% by mass when the total material constituting the varistor part 7 is 100% by mass.

  The rare earth metal element (for example, Pr) acts as a substance that exhibits varistor characteristics. The content of the rare earth metal element in the varistor part 7 is set to about 0.01 to 10 atomic%, for example.

  As shown in FIGS. 1 and 2, the conductive portion 9 is a substantially rectangular parallelepiped portion located at a position close to both ends of the element body 3, and the varistor portion 7 is sandwiched between the varistor portions 7. Located on both sides. The conductive portion 9 has a main surface 9a connected to the varistor portion 7 (main surfaces 7a and 7b), and a main surface 9b facing the main surface 9a. In the present embodiment, substantially the entire main surfaces 7 a and 7 b of the varistor portion 7 are in contact with and connected to the main surface 9 a of the conductive portion 9. The main surface 9 a of the conductive portion 9 has substantially the same shape as the main surfaces 7 a and 7 b of the varistor portion 7. The main surface 9 b of the conductive portion 9 constitutes end surfaces 3 a and 3 b of the element body 3. The main surface 9 a of the conductive portion 9 functions as an electrode surface for the varistor portion 7.

  The conductive portion 9 is made of a sintered body containing ZnO as a main component. The specific resistance of ZnO is 1 to 10 Ω · cm and has a relatively high conductivity. Therefore, the conductive portion 9 functions as an electrode. In order to adjust the specific resistance, the conductive portion 9 includes Co, IIIb group elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, Rb, Cs), and alkali as subcomponents. A simple metal such as an earth metal element (Mg, Ca, Sr, Ba) or an oxide thereof may be included. Although content of ZnO in the electroconductive part 9 is not specifically limited, When the whole material which comprises the electroconductive part 9 is 100 mass%, it is 100-69.0 mass%, for example.

  If the conductive portion 9 substantially contains a rare earth metal, the conductive portion 9 may exhibit varistor characteristics. For this reason, it is preferable that the electroconductive part 9 does not contain a rare earth metal substantially. The conductive part 9 does not substantially contain a rare earth metal, and thus hardly exhibits varistor characteristics. Therefore, the conductive portion 9 has a low electrical resistance and a relatively high conductivity. Here, the “substantially free” state refers to a state in which rare earth metal is not intentionally contained as a raw material when the material constituting the conductive portion 9 is prepared. For example, when these elements are included unintentionally due to diffusion from the varistor portion 7 to the conductive portion 9, it corresponds to a “substantially not contained” state.

  The terminal electrode 5 is formed in multiple layers so as to cover the end faces 3 a and 3 b (main surface 9 b of the conductive portion 9) of the element body 3. The terminal electrode 5 has a first electrode layer 5a, a second electrode layer 5b, and a third electrode layer 5c. The first electrode layer 5a includes a conductive powder and glass frit which are directly connected to the conductive portion 9 of the element body 3 and mainly contain Ag or the like. The second electrode layer 5b is formed so as to cover the first electrode layer 5a and contains Ni as a main component. The third electrode layer 5c is formed so as to cover the second electrode layer 5b and contains Sn as a main component.

  Next, an example of a manufacturing process of the chip varistor 1 having the above-described configuration will be described with reference to FIGS. 3 and 4 are diagrams for explaining a manufacturing process of the chip varistor according to the present embodiment.

  First, after weighing ZnO which is a main component constituting the varistor part 7 and trace additives such as Co, Pr, Cr, Ca, K, and Al metals or oxides so as to have a predetermined ratio, respectively. The varistor material is prepared by mixing each component. Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grind | pulverizes using a ball mill etc., and obtains a slurry. This slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a predetermined thickness (for example, about 30 μm). The film thus obtained is peeled from the film to obtain a first green sheet.

  Moreover, an organic binder, an organic solvent, an organic plasticizer, etc. are added to ZnO which comprises the electroconductive part 9, and it mixes and grind | pulverizes using a ball mill etc., and obtains a slurry. In addition to ZnO, when the subcomponent is contained, ZnO and the additive constituting the subcomponent are weighed so as to have a predetermined ratio, and then each component is mixed to be used for the conductive portion 9. Adjust the material. An organic binder, an organic solvent, an organic plasticizer, or the like is added to the material for the conductive portion 9 and mixed and pulverized using a ball mill or the like to obtain a slurry. This slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a predetermined thickness (for example, about 30 μm). The film thus obtained is peeled from the film to obtain a second green sheet.

  Next, a predetermined number of first green sheets and second green sheets are stacked, and a varistor green layer made of the first green sheet and a conductor green layer made of the second green sheet are Laminate so as to be sandwiched between conductive green layers. Thereafter, pressure is applied to the stacked green sheets to press the green sheets together. The thickness of the varistor green layer is adjusted by the number of first green sheets. The thickness of the conductor green layer is adjusted by the number of second green sheets. The number of first green sheets may be at least one.

  As described above, as shown in FIG. 3, a laminated body LB in which the varistor green layer L1 and the conductor green layer L2 are laminated is prepared.

  Next, after drying the stacked body LB, as shown in FIG. 4, the stacked body LB is cut into units of chips to obtain a plurality of green bodies GC (element body 3 before firing). The laminated body LB is cut by, for example, a dicing saw.

  Next, the plurality of green element bodies GC are subjected to heat treatment under predetermined conditions (for example, 180 to 400 ° C. and 0.5 to 24 hours) to perform binder removal, and further, predetermined conditions ( For example, baking is performed at 1000 to 1400 ° C. and 0.5 to 8 hours. By this firing, the varistor green layer L1 made of the first green sheet becomes the varistor part 7, the conductor green layer L2 made of the second green sheet becomes the conductive part 9, and the varistor part 7 is sandwiched between the conductive parts 9 The element body 3 is obtained. The varistor green layer L1 and the conductor green layer L2 are integrally fired. After firing, the element body 3 may be subjected to barrel polishing as necessary. The barrel polishing may be performed before firing, that is, after cutting the stacked body LB.

  Next, a conductive paste is applied so as to cover both end faces 3a and 3b of the element body 3, and the conductive paste is baked onto the element body 3 by performing heat treatment to form the first electrode layer 5a. Then, the 2nd and 3rd electrode layers 5b and 5c are formed by performing electroplating processes, such as Ni plating and Sn plating, so that the 1st electrode layer 5a may be covered. As a result, the terminal electrodes 5 are formed on both end sides of the element body 3. The terminal electrode 5 is formed on both ends of the element body 3 in the direction in which the conductive portion 9 sandwiches the varistor portion 7. As the conductive paste, for example, a metal powder mixed with glass frit and an organic vehicle can be used. As the metal powder, for example, a material mainly composed of Cu, Ag, or an Ag—Pd alloy can be used.

  By these processes, the chip varistor 1 is obtained. The following processing may be added as necessary.

  In the additional treatment, alkali metal (for example, Li, Na, etc.) is diffused from the exposed surface (side surfaces 3c to 3f) of the element body 3. Here, first, an alkali metal compound is attached to the surface (side surfaces 3c to 3f) of the element body 3 on which the terminal electrodes 5 are formed. A sealed rotating pot can be used for adhesion of the alkali metal compound. Although it does not specifically limit as an alkali metal compound, It is a compound which an alkali metal can diffuse from the surface of the element | base_body 3 by heat processing, and an alkali metal oxide, hydroxide, chloride, nitrate, borate, carbonic acid Salts and oxalates are used.

  And the element | base_body 3 to which this alkali metal compound has adhered is heat-processed by predetermined temperature and time with an electric furnace. As a result, the alkali metal diffuses from the surface of the element body 3 (side surfaces 3c to 3f) to the inside from the alkali metal compound. A preferable heat treatment temperature is 700 to 1000 ° C., and the heat treatment atmosphere is air. The heat treatment time (holding time) is preferably 10 minutes to 4 hours. Ag or Cu may be diffused instead of the alkali metal.

  In the element body 3 (varistor portion 7 and conductive portion 9), the portion where the alkali metal is diffused can achieve high resistance and low capacitance. Since the end surfaces 3a and 3b (main surface 9b of the conductive portion 9) of the element body 3 are covered with the terminal electrode 5, the alkali metal does not diffuse from the end surfaces 3a and 3b. Therefore, the alkali metal does not hinder the electrical connection between the terminal electrode 5 and the conductive portion 9.

  As described above, in the present embodiment, the varistor part 7 is sandwiched and connected between the conductive parts 9, and the varistor part 7 functions as a region that develops varistor characteristics. That is, unlike the so-called multilayer chip varistor, the chip varistor 1 exhibits varistor characteristics without having an internal electrode. For this reason, in the chip varistor 1, even when a surge voltage such as ESD is applied, a portion where the electric field distribution is concentrated does not occur in the varistor portion 7, and the ESD tolerance is not lowered.

  In this embodiment, since the chip varistor 1 does not include an internal electrode, there is no variation in capacitance caused by the internal electrode. For this reason, it can suppress that dispersion | variation arises in an electrostatic capacitance.

  In this embodiment, since the varistor part 7 and the conductive part 9 are made of a sintered body containing ZnO as a main component, the connection strength at the interface between the varistor part 7 and the conductive part 9 becomes strong. As a result, the connection between the varistor part 7 and the conductive part 9 becomes good, and the occurrence of peeling between the varistor part 7 and the conductive part 9 can be suppressed.

  In the present embodiment, the conductive part 9 is made of a sintered body containing ZnO as a main component and substantially free of rare earth metal contained in the varistor part 7 as a subcomponent. Since the conductive portion 9 (sintered body) does not substantially contain a rare earth metal, the varistor characteristic is hardly exhibited and the conductive portion 9 has a relatively high conductivity. Therefore, in the conductive part 9, the function as an electrode is not hindered.

  Subsequently, the configuration of the chip varistor 1 according to a modification of the present embodiment will be described with reference to FIGS. 5 and 6. FIG. 5 is a perspective view showing a chip varistor according to a modification of the present embodiment. FIG. 6 is a diagram for explaining a cross-sectional configuration of a chip varistor according to a modification of the present embodiment.

  As shown in FIG. 5, the chip varistor 1 according to the modification also includes a substantially rectangular parallelepiped element body 3 and a pair of terminal electrodes 5 formed at both ends of the element body 3. The element body 3 includes a varistor part 7 and a plurality (two in this embodiment) of composite parts 11.

  As shown in FIGS. 5 and 6, the composite portion 11 is a substantially rectangular parallelepiped portion located at a position near both ends of the element body 3, and the varistor portion 7 is sandwiched between the varistor portions 7. Located on both sides. The composite part 11 has a main surface 11a connected to the varistor part 7 (main surfaces 7a, 7b), and a main surface 11b facing the main surface 11a. In the present embodiment, substantially the entire main surfaces 7 a and 7 b of the varistor portion 7 are in contact with and connected to the main surface 11 a of the composite portion 11. The main surface 11 a of the composite part 11 has substantially the same shape as the main surfaces 7 a and 7 b of the varistor part 7. The main surface 11 b of the composite part 11 constitutes end faces 3 a and 3 b of the element body 3. The main surface 11 a of the composite part 11 functions as an electrode surface for the varistor part 7.

  The composite part 11 is made of a composite material of an Ag—Pd alloy and ZnO. In the composite material constituting the composite part 11, the Ag—Pd alloy is dispersed in ZnO. As shown in FIG. 7, the terminal electrode 5 and the varistor part 7 are made of Ag—Pd alloy. A conduction path 11c that connects the two is formed. In FIG. 7, only one conduction path 11 c is shown for ease of explanation, but a large number of conduction paths 11 c are formed in each composite portion 11. That is, the composite part 11 functions as a conductive part.

The content of ZnO in the composite part 11 is, for example, 10 to 80% by mass when the entire material constituting the composite part 11 is 100% by mass. The content of the Ag—Pd alloy in the composite part 11 is, for example, 20 to 90% by mass when the total material constituting the composite part 11 is 100% by mass. The composite part 11 may include any of Ag, Au, Pd, Pt, and the like as the contained metal instead of the Ag—Pd alloy. The metal oxide contained in the composite part 11 is preferably ZnO which is the same as the metal oxide contained in the varistor part 7, but instead of ZnO, a metal oxide such as CoO, NiO, or TiO ₂ is used. May be.

  Next, an example of a manufacturing process of the chip varistor 1 according to this modification will be described with reference to FIGS. 8 and 9 are diagrams for explaining a manufacturing process of a chip varistor according to a modification of the present embodiment.

  First, as in the embodiment described above, a first green sheet is obtained. Moreover, after weighing each of ZnO and Ag—Pd alloy constituting the composite part 11 so as to have a predetermined ratio, each component is mixed to adjust the material for the composite part 11. Thereafter, an organic binder, an organic solvent, an organic plasticizer, and the like are added to the material for the composite portion 11 and mixed and pulverized using a ball mill or the like to obtain a slurry. This slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a predetermined thickness (for example, about 30 μm). The film thus obtained is peeled from the film to obtain a second green sheet.

  Next, a predetermined number of first green sheets and second green sheets are stacked, and a varistor green layer made of the first green sheet and a composite green layer made of the second green sheet are Laminate so as to be sandwiched between composite green layers. Thereafter, pressure is applied to the stacked green sheets to press the green sheets together. The thickness of the composite green layer is adjusted by the number of second green sheets in the same manner as the conductor green layer.

  As described above, as shown in FIG. 8, a laminate LB in which the varistor green layer L1 and the composite green layer L3 are laminated is prepared.

  Next, after drying the laminated body LB, as shown in FIG. 9, the laminate LB is cut into chip units to obtain a plurality of green element bodies GC (element body 3 before firing).

  Next, the plurality of green element bodies GC are subjected to heat treatment under predetermined conditions (for example, 180 to 400 ° C. and 0.5 to 24 hours) to perform binder removal, and further, predetermined conditions ( For example, baking is performed at 1000 to 1400 ° C. and 0.5 to 8 hours. By this firing, the varistor green layer L1 made of the first green sheet becomes the varistor part 7, the composite green layer L3 made of the second green sheet becomes the composite part 11, and the varistor part 7 is sandwiched between the composite parts 11. The element body 3 is obtained. The varistor green layer L1 and the composite green layer L3 are integrally fired.

  Next, similarly to the above-described embodiment, the terminal electrode 5 is formed on the element body 3 (composite portion 11), and an alkali metal (for example, Li, Na, etc.) is formed from the exposed surface (side surfaces 3c to 3f) of the element body 3. To diffuse.

  Through these processes, the chip varistor 1 according to the modification is obtained.

  As described above, also in this modification, the varistor part 7 is sandwiched and connected between the composite parts 11, and the varistor part 7 functions as a region that develops varistor characteristics. That is, unlike the so-called multilayer chip varistor, the chip varistor 1 exhibits varistor characteristics without having an internal electrode. For this reason, in the chip varistor 1, even when a surge voltage such as ESD is applied, a portion where the electric field distribution is concentrated does not occur in the varistor portion, and the ESD tolerance is not lowered.

  Also in this modified example, since the chip varistor 1 does not include the internal electrode, it is possible to suppress the variation in capacitance.

  In this modification, since the composite part 11 is made of a composite material of an Ag—Pd alloy and ZnO, the heat in the chip varistor 1 is easily radiated through the composite part, so that the chip varistor 1 having excellent heat dissipation is provided. Can be obtained.

  In this modification, since the varistor part 7 and the composite part 11 contain ZnO, the connection strength at the interface between the varistor part 7 and the composite part 11 becomes strong. For this reason, the connection between the varistor part 7 and the composite part 11 becomes good, and the occurrence of peeling between the varistor part 7 and the composite part 11 can be suppressed.

  The chip varistor 1 according to the present embodiment and the modification is mounted by soldering so that the facing direction of the conductive portion 9 is parallel to a mounting surface such as an external substrate. Since the varistor part 7 is located in the approximate center of the element body 3 when viewed in the opposing direction of the conductive part 9, it is difficult for the solder to reach the varistor part 7 during soldering. As a result, the chip varistor 1 can prevent the function of the varistor part 7 from being disturbed by the solder attaching to the varistor part 7 during solder mounting.

  The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  In the present embodiment and the modification, the pair of conductive parts (conductive part 9 or composite part 11) arranged so as to sandwich the varistor part 7 have the same configuration, but is not limited thereto. For example, one conductive part may be the conductive part 9 and the other conductive part may be the composite part 11.

  The varistor part 7 may contain Bi instead of the rare earth metal. In this case, as described above, the conductive portion 9 preferably does not contain Bi. The varistor part 7 may contain a rare earth metal and Bi. In this case, it is preferable that the conductive part 9 does not contain a rare earth metal and Bi.

  DESCRIPTION OF SYMBOLS 1 ... Chip varistor, 3 ... Element body, 3a, 3b ... End surface, 5 ... Terminal electrode, 7 ... Varistor part, 7a, 7b ... Main surface, 9 ... Conductive part, 9a, 9b ... Main surface, 11 ... Composite part, 11a, 11b ... main surface, 11c ... conduction path, GC ... green body, L1 ... varistor green layer, L2 ... conductor green layer, L3 ... composite green layer, LB ... laminate.

Claims (1)

A varistor portion that is formed of a sintered body formed by laminating and firing a plurality of green sheets containing ZnO as a main component and also containing subcomponents, and expressing voltage nonlinear characteristics;
A plurality of green sheets containing ZnO as a main component and subcomponents are stacked and sintered and fired at the same time as the varistor part, and are arranged with the varistor part interposed therebetween and connected to the varistor part. A plurality of conductive portions each having a first main surface and a second main surface facing the first main surface;
A plurality of terminal electrodes connected to the second main surface of the plurality of conductive portions ,
The varistor part includes a rare earth metal element, Co, a group IIIb element, Cr, an alkali metal element, and an alkaline earth metal element as the auxiliary component,
The chip varistor is characterized in that the plurality of conductive parts do not substantially contain a rare earth metal element as the subcomponent and contain the same subcomponent as the varistor part except for the rare earth metal element .

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