JP4475249B2 - Varistor element - Google Patents

Description

  The present invention relates to a varistor element.

As this type of varistor element, a varistor element having a varistor layer that exhibits voltage nonlinear characteristics, and a pair of internal electrodes arranged so as to sandwich the varistor layer, and positioned at both ends of the varistor element In addition, a device including a pair of terminal electrodes each connected to a corresponding internal electrode among a plurality of internal electrodes is known (see, for example, Patent Document 1).
JP 2002-246207 A

  In recent years, with the miniaturization of electronic devices such as DSC (Digital Still Camera), DVC (Digital Video Camera), PDA (Personal Digital Assistant), notebook personal computer or mobile phone, etc., for high-density mounting of electronic devices such as varistor devices. The demand is getting stricter. In order to satisfy this requirement for high-density mounting, it is considered that the electronic element package is a ball grid array package (hereinafter simply referred to as a BGA package). The BGA package has a large number of solder bumps arranged in parallel on the back surface thereof. The BGA package is mounted on the mounting substrate by reflowing each solder bump in a state of being superimposed on the corresponding pad of the mounting substrate.

By the way, when the varistor element is configured to correspond to the BGA package, the solder bumps and terminal electrodes are located on the back side facing the mounting substrate, so that it is difficult to identify the mounting direction of the varistor element. If the varistor element is mounted with its mounting direction being incorrect, it will not function properly.

  It is an object of the present invention to provide a varistor element that can be mounted appropriately and easily even when configured to correspond to a BGA package.

  The varistor element according to the present invention includes a varistor element body having first and second main surfaces facing each other, and first and second varistor elements disposed in the varistor element body so that at least some of the varistor elements face each other. An internal electrode pair having an internal electrode, an internal conductor disposed in the varistor element body, and the first main surface of the internal electrode pair are formed on the first main surface so as to be electrically connected to each other. A connection terminal, a first terminal electrode formed on the second main surface to be electrically connected to the second internal electrode, and a second main surface to be electrically connected to the internal conductor And a second terminal electrode formed on the substrate.

  In the varistor element according to the present invention, since the first and second terminal electrodes are formed on the second main surface, the second main surface is made to face a mounting component (for example, an electronic component or a mounting substrate). In this state, the varistor element can be mounted, and a configuration corresponding to the BGA package is realized. In the varistor element according to the present invention, the connection conductor is formed on the first main surface so as to electrically connect the first internal electrode and the internal conductor in the internal electrode pair. An area functioning as a varistor exists at the corresponding position. Therefore, the connection conductor functions as a mark for identifying the mounting direction of the varistor element, and the varistor element can be mounted appropriately and easily. Further, according to the present invention, it is not necessary to newly provide a mark for identifying the mounting direction of the varistor element, and the manufacturing cost of the varistor element is not increased.

  Moreover, it is preferable that the varistor element body has a square shape when viewed from a direction perpendicular to the first and second main surfaces. This is particularly effective because it is difficult to identify the mounting direction of the varistor element based on the outer shape of the varistor element body.

  The first and second terminal electrodes are two-dimensionally arranged so as to be n rows and n columns (n is an even number of 2 or more), and are arranged alternately in the row direction and the column direction. It is preferable that

  In addition, both the first internal electrode and one end of the internal conductor are drawn out to the first main surface, and each part drawn out to the first main surface is physically and electrically connected to the connection conductor, respectively. 2 internal electrodes are drawn out to the second main surface, a portion drawn out to the second main surface is physically and electrically connected to the first terminal electrode, and the other end of the internal conductor is connected to the second main surface. It is preferable that a portion drawn out to the surface and drawn to the second main surface is physically and electrically connected to the second terminal electrode.

  The varistor element body is a laminated body in which a plurality of varistor layers each formed with first and second internal electrodes and internal conductors are laminated, and the first and second main surfaces are formed of varistor layers. It is preferable to extend in the direction along the stacking direction and in the direction intersecting the first and second internal electrodes and the internal conductor.

  The varistor element according to the present invention includes a varistor element body having first and second main surfaces facing each other, and first and first varistor elements disposed in the varistor element body so that at least some of the varistor elements face each other. A pair of internal electrodes having two internal electrodes, a pair of internal conductors arranged in the varistor body, and a first internal electrode and an internal conductor in the internal electrode pair so as to be electrically connected to each other. A connection conductor formed on the main surface, a first terminal electrode formed on the second main surface so as to be electrically connected to the second internal electrode, and an electric connection to the internal conductor And the second terminal electrode formed on the second main surface, the first and second terminal electrodes are two-dimensionally arranged in 2 rows and 2 columns, and in the row direction and the column direction It is characterized by being arranged alternately.

  According to the present invention, it is possible to provide a varistor element that can be mounted appropriately and easily even when a configuration corresponding to a BGA package is adopted.

  Preferred embodiments of the present invention will be described with reference to the drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and a duplicate description is omitted. The present embodiment is an example in which the present invention is applied to a multilayer chip varistor.

(Configuration of multilayer chip varistor)
With reference to FIGS. 1-6, the structure of the multilayer chip varistor 1 which concerns on this embodiment is demonstrated. FIG. 1 is a perspective view of the multilayer chip varistor according to the present embodiment as viewed from the connection conductor side. FIG. 2 is a perspective view of the multilayer chip varistor according to the present embodiment as viewed from the terminal electrode side. 3 is a cross-sectional view taken along line III-III in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 5 is a cross-sectional view taken along line VV in FIG.

  As shown in FIGS. 1 to 5, the multilayer chip varistor 1 includes a varistor element body 11, a plurality (two in this embodiment) of connection conductors 41, and a plurality (four in this embodiment). Terminal electrode 50 is provided.

  The varistor element body 11 is a plate-like body having a substantially square longitudinal section. The varistor element body 11 has a first main surface 13 and a second main surface 15 that face each other. In the present embodiment, the first main surface 13 and the second main surface 15 are both square. That is, the varistor element body 11 has a square shape when viewed from a direction perpendicular to the first main surface 13 and the second main surface 15. The varistor element body 11 can have, for example, a vertical width of about 1 mm, a horizontal width of about 1 mm, and a thickness of about 0.5 mm.

  The varistor element body 11 is configured as a stacked body in which a plurality of varistor layers that exhibit voltage nonlinearity (hereinafter referred to as “varistor characteristics”) are stacked. The actual multilayer chip varistor 1 is integrated to such an extent that the boundaries between the plurality of varistor layers are not visible. The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents.

  In the present embodiment, Pr is used as the rare earth metal element. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and there is little variation in characteristics during mass production.

  In the present embodiment, Ca is used as the alkaline earth metal element. Ca is a material for controlling the sinterability of the ZnO-based varistor material and improving the moisture resistance. The reason for using Ca is to improve voltage nonlinearity.

  Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8 mass%-69.0 mass% normally. The thickness of the varistor layer can be, for example, about 5 μm to 60 μm.

  The varistor element body 11 is provided with a plurality of (four layers in this embodiment) conductor layers 20A to 20D. At least one varistor layer is arranged between the conductor layer 20A and the conductor layer 20B, and at least one varistor layer is arranged between the conductor layer 20C and the conductor layer 20D. It is arranged in.

  As shown in FIGS. 3 to 5, each of the conductor layer 20 </ b> A and the conductor layer 20 </ b> C includes one first internal electrode 21 and one internal conductor 25. In the conductor layer 20A and the conductor layer 20C, the first inner electrode 21 and the inner conductor 25 have a predetermined distance from a side surface parallel to the stacking direction of the varistor layer (hereinafter simply referred to as “stacking direction”). Are arranged with a predetermined interval so as to be electrically insulated from each other.

  On the other hand, each of the conductor layer 20B and the conductor layer 20D includes one second internal electrode 23 and one internal conductor 25, as shown in FIGS. In the conductor layer 20B and the conductor layer 20D, the second inner electrode 23 and the inner conductor 27 have a predetermined interval from the side surfaces parallel to the stacking direction, respectively, and have a predetermined interval so as to be electrically insulated from each other. It is arranged.

  The first inner electrode 21 of the conductor layer 20A, the second inner electrode 23 of the conductor layer 20B, and the inner conductors 25 of the conductor layers 20C and 20D are arranged on the varistor layer so as to overlap when viewed from the stacking direction. Is arranged. Further, the inner conductors 25 of the conductor layers 20A and 20B, the first inner electrode 21 of the conductor layer 20C, and the second inner electrode 23 of the conductor layer 20D are arranged on the varistor layer so as to overlap when viewed from the stacking direction. Is arranged. Therefore, an internal electrode pair 31 and an internal conductor pair 32 to be described later are positioned side by side in the stacking direction in the varistor element body 11, and are positioned in a direction substantially perpendicular to the stacking direction.

  Each first internal electrode 21 has a substantially rectangular shape. Each first internal electrode 21 is drawn out to the first main surface 13 so that one end thereof faces the first main surface 13. The first internal electrode 21 in the conductor layer 20A has at least a part thereof facing the second internal electrode 23 in the conductor layer 20B across the varistor layer, and the first internal electrode 21 in the conductor layer 20C is At least a part of the varistor layer faces the second internal electrode 23 in the conductor layer 20D.

  Each second internal electrode 23 has a substantially rectangular shape. Each second internal electrode 23 is drawn out to the second main surface 15 so that one end thereof faces the second main surface 15. At least part of the second internal electrode 23 in the conductor layer 20B faces the first internal electrode 21 in the conductor layer 20A across the varistor layer, and the second internal electrode 23 in the conductor layer 20D is At least a part of the varistor layer is opposed to the first internal electrode 21 in the conductor layer 20C.

  As described above, the first varistor conductor 21 and the second internal electrode 23 are arranged in the varistor element body 11 so that at least some of them face each other. Thereby, in the multilayer chip varistor 1, a plurality of internal electrode pairs 31 including the first and second internal electrodes 21 and 23 disposed in the varistor element body 11 so that at least some of them are opposed to each other are provided. (Two in this embodiment) will be provided. Therefore, the region where the first internal electrode 21 and the second internal electrode 23 overlap in the varistor layer functions as a region that develops varistor characteristics.

  Each inner conductor 25 has a substantially rectangular shape. Each inner conductor 25 is drawn out to the first main surface 13 so that one end thereof faces the first main surface 13, and the second main surface so that the other end faces the second main surface 15. 15 is drawn. In the present embodiment, the varistor elements 11 are arranged in the varistor element body 11 so that the inner conductors 25 in the conductor layers 20A and 20B face each other, and the varistors are made so that the inner conductors 25 in the conductor layers 20C and 20D face each other. It is arranged in the element body 11. Thereby, in the multilayer chip varistor 1, a plurality (two in the present embodiment) of a pair of internal conductors 25 (internal conductor pairs 32) disposed in the varistor element body 11 are provided.

  The first and second internal electrodes 21 and 23 and the internal conductor 25 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st and 2nd internal electrodes 21 and 23 and the internal conductor 25, It is preferable to consist of Pd or an Ag-Pd alloy. The thicknesses of the first and second internal electrodes 21 and 23 and the internal conductor 25 can be set to about 0.5 μm to 5 μm, for example.

  Here, the first main surface 13 and the second main surface 15 are in a direction along the stacking direction (a parallel direction in the present embodiment), and the first and second inner electrodes 21 and 23 and the inner conductor 25. Extends in the direction intersecting (in the present embodiment, the direction orthogonal). The stacking direction is a direction parallel to the opposing direction of the first internal electrode 21 and the second internal electrode 23 (the opposing direction of the internal conductors 25), and the first and second internal electrodes 21, 23 are parallel to each other. In addition, the direction is orthogonal to the inner conductor 25.

  As shown in FIGS. 3 and 5, each connection conductor 41 is connected to the internal electrode pair 31 among the internal electrode pair 31 and the internal electrode pair 32 arranged in the stacking direction in the varistor element body 11. Each of the internal conductors 25 included in the included first internal electrode 21 and internal electrode pair 32 is formed on the first main surface 13 so as to cover each part drawn out to the first main surface 13. . Each portion of the first inner electrode 21 and each inner conductor 25 drawn to the first main surface 13 is physically and electrically connected to the corresponding connection conductor 41. Thereby, each connection conductor 41 will electrically connect the 1st internal electrode 21 and each internal conductor 25 which are located in a line with the lamination direction.

  The connection conductor 41 has a substantially square shape (in the present embodiment, a substantially rectangular shape). In the connection conductor 41, for example, the length of the long side can be about 0.8 mm, the length of the short side can be about 0.4 mm, and the thickness can be about 2 μm. The connection conductor 41 extends in a direction substantially parallel to the stacking direction.

  The connection conductor 41 includes Pt. As will be described later, the connection conductor 41 is formed by baking a conductive paste. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used.

  As shown in FIGS. 2 and 4, the terminal electrodes 50 are two-dimensionally arranged in n rows and n columns (parameter n is an even number of 2 or more) on the second major surface 15. In the present embodiment, the terminal electrodes 50 are two-dimensionally arrayed in 2 rows and 2 columns. The terminal electrode 50 has a substantially square shape (in the present embodiment, a substantially square shape). In the terminal electrode 50, for example, the length of each side can be set to about 0.4 mm, and the thickness can be set to about 2 μm.

  The terminal electrode 50 contains Pt. The terminal electrode 50 is formed by baking a conductive paste as will be described later. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used. A solder bump 53 is formed on each terminal electrode 50.

  In the present embodiment, the terminal electrode 50 has two first terminal electrodes 51 and two second terminal electrodes.

  As shown in FIGS. 3 and 5, each first terminal electrode 51 has a second second electrode so as to cover a portion drawn out to the second main surface 15 of the corresponding second inner electrode 23. Each is formed on the main surface 15. The portion of the second internal electrode 23 that is drawn to the second main surface 15 is physically and electrically connected to the corresponding first terminal electrode 51. As a result, the first terminal electrode 51 is electrically connected to the corresponding second internal electrode 23.

  On the other hand, as shown in FIGS. 3 and 5, each second terminal electrode 52 covers a portion led out to the second main surface 15 of each internal conductor 25 included in the corresponding internal conductor pair 32. And formed on the second main surface 15. A portion of the inner conductor 25 that is drawn out to the second main surface 15 is physically and electrically connected to the corresponding second terminal electrode 52. Thus, the second terminal electrode 52 is electrically connected to each internal conductor 25 included in the corresponding internal conductor pair 32.

  Here, as described above, the internal electrode pair 31 and the internal conductor pair 32 are positioned side by side in the stacking direction in the varistor element body 11 and aligned in a direction substantially perpendicular to the stacking direction. Therefore, the second terminal electrically connected to the first terminal electrode 51 electrically connected to the second internal electrode 23 included in the internal electrode pair 31 and each internal conductor 25 included in the internal conductor pair 32. The terminal electrodes 52 are also formed on the second main surface 15 so as to be positioned side by side in the stacking direction and aligned in a direction substantially perpendicular to the stacking direction. That is, the first and second terminal electrodes 51 and 52 are arranged so as to alternate in the row direction and the column direction.

  In the multilayer chip varistor 1 having the above-described configuration, as shown in FIG. 6, two sets of varistors B that connect the first terminal electrode 51 and the second terminal electrode 52 are included. Each varistor B is constituted by a first internal electrode 21, a second internal electrode 23, and a region where the first and second internal electrodes 21 and 23 overlap in the varistor layer. The connection conductor 41 extends in a direction substantially parallel to the stacking direction, and the first and second terminal electrodes 51 and 52 electrically connected to the varistor B are juxtaposed in the stacking direction. Each varistor B exists between the pair of first and second terminal electrodes 51 and 52 that are juxtaposed in the long side direction of the connection conductor 41.

(Manufacturing process of multilayer chip varistor)
Next, a manufacturing process of the multilayer chip varistor 1 having the above-described configuration will be described with reference to FIGS. FIG. 7 is a flowchart for explaining a manufacturing process of the multilayer chip varistor according to the present embodiment. FIG. 8 is a view for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment. In FIG. 7, step is abbreviated as S.

  First, ZnO, which is the main component constituting the varistor layer, and Pr, Co, Cr, Ca, Si, K and Al metals or trace additives such as oxides thereof are weighed so as to have a predetermined ratio. After that, the varistor material is adjusted by mixing each component (step 101). Thereafter, an organic binder, an organic solvent, an organic plasticizer, and the like are added to the varistor material, and mixed and pulverized for about 20 hours using a ball mill or the like to obtain a slurry.

  This slurry is applied on a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step 103).

  Subsequently, a plurality of green sheets (a number corresponding to the number of divided chips to be described later) in which a conductor portion corresponding to the first internal electrode 21 and a conductor portion corresponding to the internal conductor 25 are formed are formed (step 105). . Similarly, a plurality of green sheets (a number corresponding to the number of divided chips described later) in which a conductor portion corresponding to the second internal electrode 23 and a conductor portion corresponding to the internal conductor 25 are formed are formed (step 105). ). For the conductor portions corresponding to the first and second internal electrodes 21 and 23 and the internal conductor 25, a conductive paste in which a metal powder mainly composed of Pd particles, an organic binder, and an organic solvent is mixed is used for a printing method such as screen printing. It is formed by printing on a green sheet and drying.

  Subsequently, the green sheets on which the conductor portions are formed and the green sheets on which the conductor portions are not formed are laminated in a predetermined order to form a sheet laminate (step 107). The sheet laminate obtained in this way is cut into chips, for example, to obtain a plurality of divided green bodies LS1 (see FIG. 8) (step 109). The obtained green body LS1 corresponds to the green sheets GS11, GS12 on which the conductor portion EL1 corresponding to the first internal electrode 21 and the conductor portion EL3 corresponding to the internal conductor 25 are formed, and the second internal electrode 23. Green sheets GS21 and GS22 on which conductor portions EL3 corresponding to the conductor portions EL2 and the inner conductor 25 are formed and green sheets GS3 on which the conductor portions EL1 to EL3 are not formed are sequentially stacked. The green sheets GS3 on which the conductor portions EL1 to EL3 are not formed may be stacked in plural at each location as necessary.

  The conductor portion EL1 formed on the green sheet GS11, the conductor portion EL2 formed on the green sheet GS21, and the conductor portion EL3 formed on each of the green sheets GS12 and GS22 overlap when viewed from the stacking direction of the green sheets. Are arranged as follows. Similarly, the conductor part EL3 formed on each of the green sheets GS11 and GS21, the conductor part EL1 formed on the green sheet GS12, and the conductor part EL2 formed on each of the green sheets GS22 are viewed from the green sheet stacking direction. It is arranged to overlap.

  Subsequently, the green body LS1 is subjected to heat treatment at 180 ° C. to 400 ° C. for about 0.5 hours to 24 hours to remove the binder, and then further, 850 ° C. to 1400 ° C., for 0.5 hours to 8 hours. Baking is performed for about an hour (step 111), and the varistor element body 11 is obtained. By this firing, each green sheet GS11, GS12, GS21, GS22, GS3 in the green body LS1 becomes a varistor layer, the conductor portion EL1 becomes the first internal electrode 21, the conductor portion EL2 becomes the second internal electrode 23, and the conductor The portion EL3 becomes the inner conductor 25.

  Subsequently, the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) are formed on the outer surface of the varistor element body 11 (step 113). Here, a conductive paste is printed on the first main surface 13 of the varistor element body 11 so as to be in contact with the corresponding first internal electrode 21 by a screen printing method, and then dried, thereby connecting conductors 41. A conductor portion corresponding to is formed. Further, a conductive paste is printed on the second main surface 15 of the varistor element body 11 by a screen printing method so as to be in contact with the second internal electrode 23 included in the corresponding internal electrode pair 31, and then dried. Thus, the first terminal electrode 51 is formed. Furthermore, the conductive paste is printed on the second main surface 15 of the varistor element body 11 so as to be in contact with each internal conductor 25 included in the corresponding internal conductor pair 32, and then dried. Then, the second terminal electrode 52 is formed.

  Then, the formed conductor portion (conductive paste) is baked at 500 ° C. to 850 ° C., and the varistor element body 11 in which the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) are formed is obtained. obtain. The conductive paste for forming the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) is also the same as that for forming the first and second inner electrodes 21 and 23 and the inner conductor 25 described above. Similar to the conductive paste, a metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent can be used. The glass frit used for the conductive paste for forming the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) is made of at least one of B, Bi, Si, Sr, Ba, Pr, Zn and the like. It is preferable to contain more than one species.

  Through the process described above, the multilayer chip varistor 1 is obtained. In addition, you may diffuse an alkali metal (for example, Li, Na, etc.) from the surface of the varistor element | base_body 11 after baking. The solder bump 53 can be formed by using a known forming method.

  In addition, about the formation method of a sheet | seat laminated body, you may use the manufacturing method of the aggregate substrate described in the specification of Japanese Patent Application No. 2005-201963 already applied by the present applicant. In this case, the conductive material for forming the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) is obtained without dividing and baking the sheet laminate (collected substrate) into a plurality of green bodies LS1. A paste can be applied.

  As described above, in the present embodiment, the plurality of first and second terminal electrodes 51 and 52 are formed on the second main surface 15 of the varistor element body 11. Therefore, the multilayer chip varistor 1 can be mounted with the second main surface 15 facing a mounting component (for example, an electronic component or a mounting substrate), and a configuration corresponding to the BGA package is realized. It will be. Further, in the present embodiment, the connection conductor 41 is a first internal included in the internal electrode pair 31 among the internal electrode pair 31 and the internal conductor pair 32 that are arranged in the stacking direction in the varistor element 11. It is formed on the first main surface 13 so as to electrically connect the electrode 21 and each internal conductor 25 included in the internal conductor pair 32. Therefore, the varistor element body 11 has a region functioning as the varistor B at a position corresponding to the connection conductor 41. Therefore, the connection conductor 41 is a mark for identifying the mounting direction of the multilayer chip varistor 1. Thus, the multilayer chip varistor 1 can be mounted appropriately and easily.

  In the present embodiment, the varistor element body 11 has a square shape when viewed from the direction perpendicular to the first and second main surfaces 13 and 15. In this case, since it is difficult to identify the mounting direction of the multilayer chip varistor 1 based on the outer shape of the varistor element body 11, the connection conductor 41 functioning as a mark is formed on the first main surface 13. And is particularly effective.

  In the present embodiment, since the connection conductor 41 functions as a mark, there is no need to newly provide a mark for identifying the mounting direction of the multilayer chip varistor 1 on the varistor element body 11, and the multilayer chip varistor 1. The production cost is not increased.

  In the present embodiment, the varistor element body 11 includes Pr and Ca, and the conductive paste for forming the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) includes Pt. Then, a conductive paste for forming the connection conductor 41 and the terminal electrode 50 (first and second terminal electrodes 51 and 52) is applied on the varistor element body 11 and baked, whereby the connection conductor 41 and the terminal electrode 50 are formed. (First and second terminal electrodes 51 and 52) are formed. Therefore, the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 50 (first and second terminal electrodes 51 and 52) can be improved.

  The effect of improving the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 50 (first and second terminal electrodes 51 and 52) is due to the following phenomenon that occurs when the conductive paste is baked. It is thought to be caused. When the conductive paste is baked on the varistor element body 11, Pr and Ca contained in the varistor element body 11 move near the surface of the varistor element body 11, that is, near the interface between the varistor element body 11 and the conductive paste. And Pr and Ca which moved to the interface vicinity of the varistor element | base_body 11 and an electrically conductive paste, and Pt contained in an electrically conductive paste mutually diffuse. When Pr, Ca, and Pt are interdiffused, Pr and Ca are near the interface (including the interface) between the varistor element body 11, the connection conductor 41, and the terminal electrode 50 (first and second terminal electrodes 51, 52). A compound with Pt and a compound with Ca and Pt may be formed. The anchor effect is generated by these compounds, and the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 50 (first and second terminal electrodes 51 and 52) is improved.

  The terminal electrode 50 (first and second terminal electrodes 51 and 52) containing Pt is suitable mainly when the multilayer chip varistor 1 is mounted on an external substrate or the like by solder reflow. The attachment can be improved.

(Modification)
Next, the configuration of the multilayer chip varistor 1 according to a modification of the present embodiment will be described with reference to FIGS. FIG. 9 is a perspective view showing a multilayer chip varistor according to a modification of the present embodiment. 10 is a cross-sectional view taken along line XX of FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 12 is a cross-sectional view taken along line XII-XII in FIG.

  In the multilayer chip varistor 1 according to the modified example, as shown in FIGS. 9 to 12, the connection conductors 41 are arranged in a direction substantially perpendicular to the lamination direction in the varistor element 11 (that is, a direction substantially parallel to the varistor layer). Of the internal electrode pair 31 and the internal conductor pair 32 arranged side by side, the first internal electrode 21 included in the internal electrode pair 31 and each internal conductor 25 included in the internal conductor pair 32 are electrically connected. In this way, the first main surface 13 is formed. The connection conductor 41 extends in a direction substantially perpendicular to the stacking direction. Therefore, as shown in FIG. 13, each varistor B exists between the pair of first and second terminal electrodes 51, 52 that are juxtaposed in the long side direction of the connection conductor 41. .

  As mentioned above, although preferred embodiment and the modification of this invention were demonstrated in detail, this invention is not limited to above-described embodiment and modification. For example, the number of internal electrode pairs and internal conductor pairs is not limited to two each. That is, as long as the internal electrode pair 31 and the internal conductor pair 32 form a set, the number may be one each, or three or more.

  Further, since the connection conductor 41 and the second terminal electrode 52 need only be electrically connected by the internal conductor 25, other than the internal conductor pair 32 including the single internal conductor 25 as in the present embodiment and the modification example. In addition, the connection conductor 41 and the second terminal electrode 52 may be electrically connected by one internal conductor 25, and the connection conductor 41 and the second terminal electrode 52 may be electrically connected by three or more internal conductors 25. You may connect to.

  Further, the connection conductor 41 and the first terminal electrode 51 may be electrically connected by two or more internal electrode pairs 31. That is, in the multilayer chip varistor 1 according to the present embodiment and the modification, each varistor B is configured such that the varistor layer is sandwiched between one first internal electrode 21 and the second internal electrode 23. The varistor B may have a configuration in which the varistor layer is sandwiched between the plurality of first internal electrodes 21 and the plurality of second internal electrodes 23.

  Further, the internal electrode pairs 31 and the internal conductor pairs 32 may be positioned side by side in the stacking direction or in a direction substantially perpendicular to the stacking direction in the varistor element body 11. That is, the first terminal electrodes 51 and the second terminal electrodes 52 may be adjacent to each other in the row direction or the column direction.

It is a perspective view when the multilayer chip varistor concerning this embodiment is seen from the connection conductor side. It is a perspective view when the multilayer chip varistor concerning this embodiment is seen from the terminal electrode side. It is the III-III sectional view taken on the line of FIG. It is the IV-IV sectional view taken on the line of FIG. It is the VV sectional view taken on the line of FIG. It is a figure for demonstrating the equivalent circuit of the multilayer chip varistor concerning this embodiment. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor concerning this embodiment. It is a perspective view which shows the multilayer chip varistor which concerns on the modification of this embodiment. FIG. 10 is a sectional view taken along line XX in FIG. 9. It is the XI-XI sectional view taken on the line of FIG. It is the XII-XII sectional view taken on the line of FIG. It is a figure for demonstrating the equivalent circuit of the multilayer chip varistor which concerns on the modification of this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer chip varistor, 11 ... Varistor element body, 13 ... 1st main surface, 15 ... 2nd main surface, 21 ... 1st internal electrode, 23 ... 2nd internal electrode, 25 ... Internal conductor, DESCRIPTION OF SYMBOLS 31 ... Internal electrode pair, 32 ... Internal conductor pair, 41 ... Connection conductor, 50 ... Terminal electrode, 51 ... 1st terminal electrode, 52 ... 2nd terminal electrode, 53 ... Solder pump, B ... Varistor.

Claims (5)

A varistor element body having first and second principal surfaces facing each other;
At least a part each other disposed on the varistor element body so as to face each other, first and second internal electrodes extending in the opposing direction of the first and second main surfaces,
An inner conductor disposed in the varistor element and extending in the opposing direction of the first and second main surfaces ;
A connection conductor formed prior Symbol first main surface,
And first and second terminal electrodes formed on the fore Symbol second major surface,
One end of the first internal electrode and one end of the internal conductor are both drawn out to the first main surface, and each part drawn out to the first main surface is physically and electrically connected to the connection conductor, respectively. Connected,
The second internal electrode is drawn out to the second main surface, and a portion drawn out to the second main surface is physically and electrically connected to the first terminal electrode;
The other end of the inner conductor is drawn out to the second main surface, and a portion drawn out to the second main surface is physically and electrically connected to the second terminal electrode;
The end portion on the second main surface side of the first internal electrode is located in the varistor element body and is not connected to the first and second terminal electrodes and the connection conductor,
An end of the second internal electrode on the first main surface side is located in the varistor element body and is not connected to the first and second terminal electrodes and the connection conductor. Varistor element.   2. The varistor element according to claim 1, wherein the varistor element body has a square shape when viewed from a direction perpendicular to the first and second main surfaces. The first and second terminal electrodes are two-dimensionally arranged so as to be n rows and n columns (n is an even number of 2 or more), and are alternately arranged in the row direction and the column direction. varistor element according to claim 1 or 2, characterized in that is. The varistor element body is a laminated body in which a plurality of varistor layers each formed with the first and second internal electrodes and the internal conductor are laminated,
The first and second main surfaces extend in a direction along a stacking direction of the varistor layer and in a direction intersecting the first and second internal electrodes and the internal conductor. Item 4. A varistor element according to any one of Items 1 to 3 . A varistor element body having first and second principal surfaces facing each other;
At least a part each other disposed on the varistor element body so as to face each other, the first to fourth internal electrodes extending in the opposing direction of the first and second main surfaces,
First and second inner conductors disposed in the varistor element and extending in the opposing direction of the first and second main surfaces ;
First and second connection conductor formed prior Symbol first main surface,
And a first to fourth terminal electrodes formed before Symbol second major surface,
One end of the first internal electrode and one end of the first internal conductor are both drawn out to the first main surface, and each portion drawn out to the first main surface is physically connected to the first connection conductor. Connected electrically and electrically,
The second internal electrode is drawn out to the second main surface, and a portion drawn out to the second main surface is physically and electrically connected to the first terminal electrode;
The other end of the first inner conductor is drawn out to the second main surface, and the portion drawn out to the second main surface is physically and electrically connected to the second terminal electrode;
An end of the first internal electrode on the second main surface side is located in the varistor element body and is connected to the first to fourth terminal electrodes and the first and second connection conductors. Not
An end of the second internal electrode on the first main surface side is located in the varistor element body and is connected to the first to fourth terminal electrodes and the first and second connection conductors. Not
One end of the third internal electrode and one end of the second internal conductor are both drawn out to the first main surface, and each part drawn out to the first main surface is physically connected to the second connection conductor. Connected electrically and electrically,
The fourth internal electrode is drawn out to the second main surface, and a portion drawn out to the second main surface is physically and electrically connected to the third terminal electrode;
The other end of the second inner conductor is drawn out to the second main surface, and a portion drawn out to the second main surface is physically and electrically connected to the fourth terminal electrode;
An end of the third internal electrode on the second main surface side is located in the varistor element body and is connected to the first to fourth terminal electrodes and the first and second connection conductors. Not
The end portion on the first main surface side of the fourth internal electrode is located in the varistor element body, and is connected to the first to fourth terminal electrodes and the first and second connection conductors. Not
The varistor element, wherein the first to fourth terminal electrodes are two-dimensionally arranged in 2 rows and 2 columns and alternately arranged in a row direction and a column direction.

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