JP4952175B2 - Barista - Google Patents

Description

  The present invention relates to a varistor, and more particularly, to a varistor including a sintered body mainly composed of ZnO and exhibiting voltage nonlinear characteristics.

As this type of varistor, a sintered body mainly composed of ZnO and exhibiting a voltage non-linear characteristic, a pair of internal electrodes disposed in the sintered body so as to face each other at a predetermined interval, and sintered A device including a pair of external electrodes arranged on the outer surface of the body and electrically connected to a corresponding internal electrode among a plurality of internal electrodes is known (see, for example, Patent Document 1).
JP 2002-246207 A

  It is an object of the present invention to provide a varistor capable of obtaining desired varistor characteristics by suppressing occurrence of voltage non-linear characteristics (hereinafter referred to as varistor characteristics) except in a region between a plurality of internal electrodes. And

  In recent years, with the miniaturization of electronic devices such as DSC (Digital Still Camera), DVC (Digital Video Camera), PDA (Personal Digital Assistant), notebook personal computers or mobile phones, there is a demand for high-density mounting of electronic components such as varistors. Is getting tougher. In order to satisfy the demand for high-density mounting, it is considered that the electronic component package is a ball grid array package (hereinafter simply referred to as a BGA package). The BGA package has a large number of solder bumps arranged in parallel on the back surface thereof. The BGA package is mounted on the mounting substrate by reflowing each solder bump in a state of being superimposed on the corresponding pad of the mounting substrate.

  As a configuration in which the varistor is made to correspond to the BGA package, a configuration in which a plurality of external electrodes are arranged on the same outer surface of a sintered body mainly composed of ZnO can be considered. Therefore, the present inventors made a parister in which a plurality of external electrodes are arranged on the same outer surface of a sintered body containing ZnO as a main component, and investigated its electrical characteristics. As a result, the present inventors have found that not only a region between a plurality of internal electrodes but also a plurality of external electrodes in a parister in which a plurality of external electrodes are arranged on the same outer surface of a sintered body mainly composed of ZnO. A new fact has been found that varistor characteristics also occur in the region between the electrodes. The present inventors have also found a new fact that the varistor characteristics generated in the region between the plurality of external electrodes are related to the interval between the plurality of external electrodes and the interval between the plurality of internal electrodes.

  The phenomenon that varistor characteristics occur between a plurality of external electrodes is considered to be due to the following reason. When a potential difference occurs between the plurality of external electrodes, an electric field is generated between the plurality of external electrodes. Since the electric lines of force in this electric field pass through the vicinity of the outer surface of the sintered body where the external electrodes are formed, varistor characteristics occur in the region between the plurality of external electrodes in the sintered body.

  The vicinity of the outer surface of the sintered body is more susceptible to the firing atmosphere and heat than the inside of the sintered body, and variations in oxygen diffusion and ZnO crystal growth are likely to occur. Further, in the vicinity of the outer surface of the sintered body, ZnO crystal growth is promoted by heat and oxygen diffusion, and the varistor voltage tends to be lower than in the inside of the sintered body. For this reason, the varistor characteristics generated in the region between the plurality of external electrodes in the sintered body have variations and cannot be ignored for the varistor characteristics generated in the region between the plurality of internal electrodes in the sintered body. The varistor characteristics will be affected.

  Usually, in the multilayer chip varistor, each external electrode is disposed at the end of the sintered body, so that the interval between the external electrodes is relatively large. For this reason, the varistor characteristics generated in the region between the plurality of external electrodes in the sintered body are hardly generated, and even if the varistor characteristics occur, the varistor characteristics generated in the region between the plurality of internal electrodes in the sintered body are ignored. it can.

  However, as described above, due to the demand for miniaturization of electronic components, when the varistor is configured to be compatible with the BGA package, the interval between the plurality of external electrodes arranged on the same outer surface becomes extremely small. End up. For this reason, the influence of the varistor characteristics generated in the region between the plurality of external electrodes in the sintered body becomes larger.

  According to the results of the research conducted by the inventors, when the interval between the plurality of external electrodes on the same outer surface is four times or less than the interval between the plurality of internal electrodes, The influence of the varistor characteristics generated in the region between the external electrodes becomes noticeable. That is, when the interval between the plurality of external electrodes on the same outer surface is larger than four times the interval between the plurality of internal electrodes, the varistor characteristic is hardly generated in the region between the plurality of external electrodes in the sintered body. Become. Further, even if varistor characteristics occur in the region between the plurality of external electrodes in the sintered body, the varistor characteristics can be ignored with respect to the varistor characteristics generated in the region between the plurality of internal electrodes in the sintered body.

Based on this fact, the varistor according to the present invention is composed of a sintered body mainly composed of ZnO and exhibiting voltage non-linear characteristics, and a plurality of the varistors arranged in the sintered body so as to face each other at a predetermined interval. An internal electrode and a plurality of external electrodes arranged so as to be adjacent to one outer surface of the sintered body, and a distance (D _e ) between the plurality of external electrodes on the one outer surface is a plurality of For a given spacing (D _i ) between internal electrodes,
0 <D _e ≦ 4D _i
A region having a varistor voltage higher than the varistor voltage in the region between the plurality of internal electrodes in the sintered body is formed from one outer surface side at least between the plurality of external electrodes in the sintered body. It is characterized by being.

In the varistor according to the present invention, the varistor voltage in the region between the plurality of external electrodes in the sintered body is higher than the varistor voltage in the region between the plurality of internal electrodes in the sintered body. Thereby, the interval between the plurality of external electrodes on one outer surface is narrow, and the interval (D _e ) and the predetermined interval (D _i ) between the plurality of internal electrodes are
0 <D _e ≦ 4D _i
Even when the above relationship is satisfied, varistor characteristics are less likely to occur in the region between the plurality of external electrodes in the sintered body. Further, even if varistor characteristics occur in the region between the plurality of external electrodes in the sintered body, the varistor characteristics can be ignored with respect to the varistor characteristics generated in the region between the plurality of internal electrodes in the sintered body. As a result, the occurrence of varistor characteristics outside the region between the plurality of internal electrodes is suppressed, and desired varistor characteristics can be obtained.

  Preferably, a region having a varistor voltage higher than a varistor voltage in a region between the plurality of internal electrodes in the sintered body is formed by diffusing alkali metal from one outer surface side. In this case, the region between the plurality of external electrodes in the sintered body is substantially electrically insulated. Thereby, the varistor voltage of the area | region between the some external electrodes in a sintered compact can be easily made higher than the varistor voltage of the area | region between the some internal electrodes in a sintered compact.

The varistor according to the present invention includes a sintered body mainly composed of ZnO and exhibiting voltage non-linear characteristics, and a plurality of internal electrodes arranged in the sintered body so as to face each other at a predetermined interval. A plurality of external electrodes arranged adjacent to one outer surface of the sintered body, and a distance (D _e ) between the plurality of external electrodes on the one outer surface is between the plurality of internal electrodes. For a given interval (D _i )
0 <D _e ≦ 4D _i
The sintered body is characterized in that an alkali metal is diffused from the one outer surface side in at least one outer surface.

  In the varistor according to the present invention, since the alkali metal is diffused from one outer surface side to the sintered body, the region between the plurality of external electrodes in the sintered body is substantially electrically insulated. . For this reason, the varistor voltage in the region between the plurality of external electrodes in the sintered body is higher than the varistor voltage in the region between the plurality of internal electrodes in the sintered body. As a result, as described above, the occurrence of varistor characteristics outside the region between the plurality of internal electrodes is suppressed, and desired varistor characteristics can be obtained.

  Preferably, the alkali metal is Li. Li has a relatively small ionic radius and is liable to be dissolved in ZnO crystals. For this reason, the area | region between the some external electrodes in a sintered compact can be made into the state electrically insulated substantially.

  Preferably, the sintered body contains a rare earth metal as an auxiliary component for developing varistor characteristics. When the rare earth metal is included, the sintered body becomes a densified structure. For this reason, the alkali metal hardly diffuses from the one outer surface of the sintered body to a deep portion, and does not reach the region between the plurality of internal electrodes in the sintered body. As a result, it is possible to prevent the diffused alkali metal from affecting the varistor characteristics generated in the region between the plurality of internal electrodes in the sintered body. More preferably, the rare earth metal is Pr.

  According to the present invention, it is possible to provide a varistor capable of suppressing desired varistor characteristics from being generated outside the region between the plurality of internal electrodes and obtaining desired varistor characteristics.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

(First embodiment)
The configuration of the multilayer chip varistor 1 according to the first embodiment will be described with reference to FIGS. FIG. 1 is a perspective view showing the multilayer chip varistor according to the first embodiment as viewed from the first main surface side of the varistor element body. FIG. 2 is a perspective view showing the multilayer chip varistor according to the first embodiment, as viewed from the second main surface side of the varistor element body. FIG. 3 is a diagram for explaining a cross-sectional configuration along the line III-III in FIG. 1. FIG. 4 is a diagram for explaining a cross-sectional configuration along the line IV-IV in FIG. 3. FIG. 5 is a diagram for explaining a cross-sectional configuration along the line V-V in FIG. 4.

  As shown in FIGS. 1 to 5, the multilayer chip varistor 1 includes a varistor element body 11 and a plurality of external electrodes. The plurality of external electrodes include a plurality (two in the present embodiment) of connection conductors 41 and a plurality (four in the present embodiment) of terminal electrodes 51.

  The varistor element body 11 has a substantially rectangular plate shape. For example, the varistor element body 11 is set to have a length of about 1 mm, a width of about 1 mm, and a thickness of about 0.5 mm. The varistor element body 11 has a first main surface 13 and a second main surface 15 that face each other. The first main surface 13 and the second main surface 15 have a square shape. That is, the varistor element body 11 has a square shape when viewed from a direction perpendicular to the first main surface 13 and the second main surface 15.

  The varistor element body 11 is a sintered body that exhibits varistor characteristics, and is configured as a laminated body in which a plurality of varistor layers are laminated. In the actual multilayer chip varistor 1, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized. The varistor layer contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K, K) as subcomponents. Rb, Cs) and simple earth metals such as alkaline earth metal elements (Mg, Ca, Sr, Ba) and element bodies containing these oxides. In the present embodiment, the varistor layer contains Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small.

  In the present embodiment, Ca is used as the alkaline earth metal element. Ca becomes a material for controlling the sinterability of the ZnO-based varistor material and improving the moisture resistance. The reason for using Ca is to improve voltage nonlinearity.

  Although content of ZnO in a varistor layer is not specifically limited, When the whole material which comprises a varistor layer is 100 mass%, it is 99.8-69.0 mass% normally. The thickness of the varistor layer is, for example, about 5 to 60 μm.

  In the varistor element body 11, alkali metal is diffused from the outer surface side, and high resistance in the vicinity of the outer surface of the varistor element body 11 is achieved. When the alkali metal is diffused from the outer surface side of the varistor element body 11, the diffused alkali metal is dissolved in the ZnO crystal. As a result, ZnO, which exhibits properties as an n-type semiconductor, has donors reduced by alkali metal and increases electrical resistance. It is also considered that the electrical resistance is increased by the presence of an alkali metal at the grain boundary of ZnO. In this embodiment, Li is used as the alkali metal diffused in the varistor element body 11.

  In the varistor element body 11, a plurality of (in this embodiment, two layers) first internal electrode layers 21 and second internal electrode layers 31 are disposed. The first internal electrode layer 21 and the second internal electrode layer 31 are arranged so that at least one varistor layer is interposed between them.

  Each first internal electrode layer 21 includes a plurality of (in the present embodiment, two) first internal electrodes 23 as shown in FIGS. 3 to 5. Each first internal electrode 23 has a substantially rectangular shape. One first internal electrode 23 is opposed to one second internal electrode 33, which will be described later, with at least a part thereof sandwiching the varistor layer. The first internal electrodes 23 included in the same first internal electrode layer 21 have a predetermined interval from a side surface parallel to the stacking direction of the varistor layers (hereinafter simply referred to as “stacking direction”) and are electrically connected to each other. Are located at predetermined intervals so as to be electrically insulated. Each first internal electrode 23 is drawn out to the first main surface 13 so that one end thereof faces the first main surface 13.

  As shown in FIGS. 3 to 5, each second internal electrode layer 31 includes a plurality (two in the present embodiment) of second internal electrodes 33. Each second internal electrode 33 has a substantially rectangular shape. One second internal electrode 33 faces at least a part of the first internal electrode 23 across the varistor layer. Similar to the first internal electrode 23, the second internal electrodes 33 included in the same second internal electrode layer 31 have a predetermined interval from the side surface parallel to the stacking direction and are electrically insulated from each other. In this way, they are located at predetermined intervals. Each second internal electrode 33 is drawn out to the second main surface 15 so that one end thereof faces the second main surface 15.

As described above, the first internal electrode 23 and the second internal electrode 33 are arranged in the varistor element body 11 so that at least some of them are opposed to each other with a predetermined distance _Di1. Yes. Thereby, in the multilayer chip varistor 1, a plurality of (internal) pairs of internal electrodes including the first and second internal electrodes 23 and 33 disposed in the varistor element body 11 so that at least some of them are opposed to each other are provided. In the embodiment, four) are provided. The predetermined interval D _i1 is set in consideration of the varistor voltage and the like, but is set to 20 to 60 μm, for example, in the present embodiment.

  The first internal electrode 23 and the second internal electrode 33 include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the 1st internal electrode 23 and the 2nd internal electrode 33, It is preferable to consist of Pd, an Ag-Pd alloy, or Ag. The thickness of the first internal electrode 23 and the second internal electrode 33 is, for example, about 0.5 to 5 μm.

  The first main surface 13 and the second main surface 15 extend in a direction parallel to the stacking direction and perpendicular to the first and second inner electrodes 23 and 33. The stacking direction is a direction parallel to the facing direction of the first internal electrode 23 and the second internal electrode 33, and is a direction perpendicular to the first and second internal electrodes 23 and 33.

  As shown in FIGS. 3 and 5, each of the connection conductors 41 includes the first inner electrode 23 included in the two internal electrode pairs positioned in the stacking direction among the four internal electrode pairs. It arrange | positions on the 1st main surface 13 so that the part pulled out by 1 main surface 13 may be covered. A portion of the first internal electrode 23 drawn out to the first main surface 13 is physically and electrically connected to the corresponding connection conductor 41. As a result, the connection conductor 41 electrically connects the first internal electrodes 23 included in the two internal electrode pairs positioned side by side in the stacking direction.

  Each connection conductor 41 has a substantially rectangular shape (in this embodiment, a substantially rectangular shape). For example, the connecting conductor 41 has a long side length of about 0.8 mm, a short side length of about 0.4 mm, and a thickness of about 2 μm. The long side direction of the connection conductor 41 is parallel to the stacking direction.

  The connection conductor 41 includes Pt. The connection conductor 41 is formed by baking a conductive paste as will be described later. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used.

  As shown in FIGS. 2 and 4, each terminal electrode 51 is provided on the second main surface 15 in correspondence with each second internal electrode 33, and has n rows and n columns (parameter n is equal to n). 2 is an even number of 2 or more). In the present embodiment, the terminal electrodes 51 are two-dimensionally arranged in 2 rows and 2 columns. The terminal electrode 51 has a substantially rectangular shape (in the present embodiment, a substantially square shape). In the terminal electrode 51, for example, the length of each side is set to about 0.4 mm, and the thickness is set to about 2 μm.

  As shown in FIGS. 3 and 5, each terminal electrode 51 is formed on the second main surface 15 so as to cover a portion drawn out to the second main surface 15 of the corresponding second internal electrode 33. Has been placed. The portion of the second internal electrode 33 that is drawn out to the second main surface 15 is physically and electrically connected to the corresponding terminal electrode 51. As a result, the terminal electrode 51 is electrically connected to the corresponding second internal electrode 33.

  The terminal electrode 51 contains Pt. The terminal electrode 51 is formed by baking a conductive paste as will be described later. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used. Each terminal electrode 51 is provided with a solder bump 53.

The distance D _e1 between the two adjacent terminal electrodes 51 on the second main surface 15 is set to the above-described predetermined distance D _i1 .
0 <D _e1 ≦ 4D _i1
Is set to satisfy the relationship. The intervals D _e1 do not have to be the same, and may be different as long as they are within a range that satisfies the above relationship.

The distance D _e2 between the two connection conductors 41 on the first main surface 13 is set to the above-described predetermined distance D _i1 .
0 <D _e2 ≦ 4D _i1
Is set to satisfy the relationship.

  As described above, the first internal electrode 23 and the second internal electrode 33 are positioned so that at least some of them face each other and overlap each other when viewed from the stacking direction. Therefore, a region that overlaps the first internal electrode 23 and the second internal electrode 33 in the varistor layer, that is, a region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11 is a varistor. It functions as a region that develops characteristics.

  In the multilayer chip varistor 1 having the above-described configuration, as shown in FIG. 6, two sets of two varistors B connected in series are included. Each varistor B is composed of a first internal electrode 23, a second internal electrode 33, and a region overlapping the first and second internal electrodes 23, 33 in the varistor layer.

  As described above, the long side direction of the connection conductor 41 is substantially parallel to the stacking direction, that is, the connection conductor 41 is arranged to extend in the stacking direction. One terminal electrode 51 and the other terminal electrode 51 of two varistors B connected in series are juxtaposed in the stacking direction. Therefore, two varistors B connected in series exist between the pair of terminal electrodes 51 that are juxtaposed in the long side direction of the connection conductor 41.

  Subsequently, a manufacturing process of the multilayer chip varistor 1 having the above-described configuration will be described with reference to FIGS. FIG. 7 is a flowchart for explaining the manufacturing process of the multilayer chip varistor according to the first embodiment. FIG. 8 is a view for explaining the manufacturing process of the multilayer chip varistor according to the first embodiment.

  First, after weighing ZnO, which is a main component constituting the varistor layer, and trace additives such as Pr, Co, Cr, Ca, Si, K, and Al metals or oxides so as to have a predetermined ratio. The varistor material is adjusted by mixing the components (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S103).

  Next, a plurality of electrode portions (numbers corresponding to the number of divided chips described later) corresponding to the first internal electrodes 23 are formed on the green sheet (step S105). Similarly, a plurality of electrode portions corresponding to the second internal electrode 33 (a number corresponding to the number of divided chips described later) are formed on different green sheets (step S105). The electrode portions corresponding to the first and second internal electrodes 23 and 33 are printed by a printing method such as screen printing with a conductive paste in which a metal powder mainly composed of Pd particles, an organic binder, and an organic solvent is mixed. It is formed by drying.

  Next, a sheet laminate is formed by stacking each green sheet on which electrode portions are formed and a green sheet on which electrode portions are not formed in a predetermined order (step S107). The sheet laminate thus obtained is cut into, for example, chips, to obtain a plurality of divided green bodies LS1 (see FIG. 8) (step S109). In the obtained green body LS1, a green sheet GS1 in which an electrode portion EL1 corresponding to the first internal electrode 23 is formed, a green sheet GS2 in which an electrode portion EL2 corresponding to the second internal electrode 33 is formed, A green sheet GS3 on which the electrode portions EL1 and EL2 are not formed is sequentially laminated. In addition, you may laminate | stack the green sheet GS3 in which electrode part EL1, EL2 is not formed in each part as needed.

  Next, the green body LS1 is subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and then further fired at 850 to 1400 ° C. for about 0.5 to 8 hours. (Step S111) to obtain the varistor element body 11. By this firing, the green sheets GS1 to GS3 in the green body LS1 become varistor layers. The electrode portion EL <b> 1 becomes the first internal electrode 23. The electrode portion EL <b> 2 becomes the second internal electrode 33.

  Next, Li is diffused from the outer surface of the varistor element body 11 (step S113). Here, first, a Li compound is attached to the surface of the obtained varistor element body 11. A sealed rotating pot can be used for adhesion of the Li compound. Although it does not specifically limit as a Li compound, Li is a compound in which Li can be diffused from the outer surface of the varistor element body 11 by heat treatment, and Li oxide, hydroxide, chloride, nitrate, borate, Carbonates and oxalates are used.

  Then, the varistor element body 11 to which the Li compound is adhered is heat-treated in an electric furnace at a predetermined temperature and time. As a result, Li diffuses from the outer surface of the varistor element body 11 into the varistor element body 11 from the Li compound. A preferable heat treatment temperature is 700 to 1100 ° C., and the heat treatment atmosphere is air. The heat treatment time (holding time) is preferably 10 minutes to 4 hours.

  Next, the connection conductor 41 and the terminal electrode 51 are formed on the outer surface of the varistor element body 11 (step S115). Here, a conductive paste is printed on the first main surface 13 of the varistor element body 11 so as to be in contact with the corresponding first internal electrode 23 by a screen printing method, and then dried, thereby connecting conductors 41. A conductor portion corresponding to is formed. In addition, the conductive paste is printed on the second main surface 15 of the varistor element body 11 so as to be in contact with the corresponding second internal electrode 33 by a screen printing method, and then dried, whereby the terminal electrode 51 is formed. Corresponding electrode portions are formed. Then, the formed electrode portion (conductive paste) is baked at 500 to 1100 ° C. according to the material of the electrode (metal powder) to obtain the varistor element body 11 in which the connection conductor 41 and the terminal electrode 51 are formed. As described above, the conductive paste for the connection conductor 41 and the terminal electrode 51 may be a mixture of a metal powder containing Pt particles as a main component and a glass frit, an organic binder, and an organic solvent. The glass frit used for the conductive paste for the connection conductor 41 and the terminal electrode 51 contains at least one or more of B, Bi, Al, Si, Sr, Ba, Pr, Zn and the like.

  Through the process described above, the multilayer chip varistor 1 is obtained. In addition, about the formation method of the solder bump 53, the existing formation method can be utilized and description here is abbreviate | omitted.

  As a method for forming the sheet laminate, a method for manufacturing an aggregate substrate described in the specification of Japanese Patent Application No. 2005-201963, which is a prior application of the present application, may be used. In this case, the conductive paste for the connection conductor 41 and the terminal electrode 51 can be applied without dividing and baking the sheet laminate (aggregate substrate) into a plurality of green bodies LS2.

  As described above, according to the first embodiment, since the plurality of terminal electrodes 51 are arranged on the second main surface 15 of the varistor element body 11, the second main surface 15 is mounted on a mounting component (for example, The multilayer chip varistor 1 can be mounted in a state of being opposed to an electronic component, a mounting substrate, etc., and a configuration corresponding to the BGA package is realized. Since the connection conductor 41 is disposed on the first main surface 15 so as to electrically connect the first internal electrodes 23 included in the two internal electrode pairs positioned side by side in the stacking direction, In the element body 11, a region functioning as the varistor B exists at a position corresponding to the connection conductor 41. Therefore, the connection conductor 41 functions as a mark for identifying the mounting direction of the multilayer chip varistor 1, and the multilayer chip varistor 1 can be mounted appropriately and easily.

  When the varistor element body 11 is square when viewed from the direction perpendicular to the first and second main surfaces 13 and 15, the mounting direction of the multilayer chip varistor 1 is based on the outer shape of the varistor element body 11. Is particularly effective because it is difficult to identify.

  Further, according to the present embodiment, it is not necessary to newly provide a mark for identifying the mounting direction of the multilayer chip varistor 1 on the varistor element body 11, and the manufacturing cost of the multilayer chip varistor 1 does not increase.

  By the way, in the multilayer chip varistor 1, since Li is diffused from the outer surface of the varistor element body 11, as shown in FIG. 9, the region 11a in the vicinity of the outer surface of the varistor element body 11 is diffused. , The electrical resistance is extremely high, and it is in a substantially electrically insulated state. That is, the region between two adjacent terminal electrodes 51 in the varistor element body 11 is substantially electrically insulated, and varistor characteristics are unlikely to occur in the region. Therefore, the varistor voltage in the region between two adjacent terminal electrodes 51 in the varistor element body 11 is larger than the varistor voltage in the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. Is also extremely high.

  In addition, a region between the two connection conductors 41 in the varistor element body 11 is substantially electrically insulated, and varistor characteristics hardly occur in the region. For this reason, the varistor voltage in the region between the two connection conductors 41 in the varistor element body 11 is much higher than the varistor voltage in the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. Get higher.

As described above, the distance _De1 between the two adjacent terminal electrodes 51 on the second main surface 15 is narrow, and the predetermined distance between the distance and the first internal electrode 23 and the second internal electrode 33 is obtained. _Di1 is
0 <D _e1 ≦ 4D _i1
The distance D _e2 between the two connection conductors 41 on the first main surface 13 and the predetermined distance D _i1 are
0 <D _e2 ≦ 4D _i1
Even when the above relationship is satisfied, varistor characteristics are less likely to occur in a region between two adjacent terminal electrodes 51 in the varistor element body 11 and a region between two connection conductors 41 in the varistor element body 11. Even if varistor characteristics occur in the region between the two adjacent terminal electrodes 51 in the varistor element body 11 and in the region between the two connection conductors 41 in the varistor element body 11, the varistor characteristics are different in the varistor element body 11. The varistor characteristics generated in the region between the first internal electrode 23 and the second internal electrode 33 can be ignored. As a result, the varistor characteristics are suppressed from occurring in a region other than the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11, and the multilayer chip varistor 1 is desired. Varistor characteristics can be obtained.

  Attention is paid to one terminal electrode 51 and the other terminal electrode 51 of two varistors B connected in series. Varistor characteristics generated in a region between two adjacent terminal electrodes 51 in the varistor element body 11 have variations. For this reason, when Li is not diffused in the varistor element body 11, the varistor characteristics of the varistor B also vary due to the influence of this variation. However, as Li is diffused in the varistor element body 11, as described above, it is difficult for varistor characteristics to occur in the region between the two adjacent terminal electrodes 51 in the varistor element body 11, so that variations do not easily occur. . Therefore, the varistor characteristics of the varistor B do not vary.

  When a surge voltage such as ESD (Electrostatic Discharge) is applied to one set of two varistors B connected in series among two sets of varistors B connected in series, one set A potential difference also occurs between the terminal electrodes 51 of the two varistors B connected in series and the terminal electrodes 51 of the two varistors B connected in series in the other set. For this reason, an electric field is generated between these terminal electrodes 51. Similarly, an electric field is generated between the connection conductors 41.

  Attention is paid to the terminal electrodes 51 of two varistors B connected in series in one set and the terminal electrodes 51 of two varistors B connected in series in the other set. Varistor characteristics generated in a region between two adjacent terminal electrodes 51 in the varistor element body 11 have variations, and in a region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. The resulting varistor characteristics cannot be ignored. For this reason, when Li is not diffused in the varistor element body 11, a varistor characteristic occurs in the region between the two terminal electrodes 51 in the varistor element body 11, and two varistors connected in series in one set. Crosstalk occurs between B and the two varistors B connected in series in the other set. However, since Li is diffused into the varistor element body 11, as described above, the varistor characteristics hardly occur in the region between the two terminal electrodes 51 in the varistor element body 11. It does not occur.

  Attention is paid to the connection conductors 41. Varistor characteristics generated in the region between the two connection conductors 41 in the varistor element body 11 have variations, and varistors generated in the area between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. It cannot be ignored for characteristics. For this reason, when Li is not diffused in the varistor element body 11, a varistor characteristic occurs in a region between the two connection conductors 41 in the varistor element body 11, and the two varistors B connected in series in one set Crosstalk occurs between two varistors B connected in series in the other set. However, when Li is diffused into the varistor element body 11, as described above, the varistor characteristic is unlikely to occur in the region between the two connection conductors 41 in the varistor element body 11, and thus the crosstalk occurs. There is no.

  As a result, the varistor B (multilayer chip varistor 1) can obtain desired varistor characteristics.

  In the first embodiment, as described above, since varistor characteristics are unlikely to occur in the region between the two adjacent terminal electrodes 51 in the varistor element body 11 and the region between the two connection conductors 41 in the varistor element body 11, The tolerance of the die chip varistor 1 against ESD, so-called ESD tolerance, is also increased. In addition, since the electric resistance of the region 11 a in which Li in the vicinity of the outer surface of the varistor element body 11 is diffused is extremely high, the leakage current between two adjacent terminal electrodes 51 in the varistor element body 11 and the two in the varistor element body 11. Leakage current between the two connection conductors 41 is less likely to occur, and the leakage current of the multilayer chip varistor 1 is reduced.

  In the first embodiment, the region having a varistor voltage higher than the varistor voltage in the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11 is the outer surface (first main surface). 13 and the second main surface 15) are formed by diffusing Li from the side. As a result, the varistor voltage in the region between the two adjacent terminal electrodes 51 in the varistor element body 11 and the varistor voltage in the region between the two connection conductors 41 in the varistor element body 11 are changed to the first varistor element body 11. The varistor voltage in the region between the internal electrode 23 and the second internal electrode 33 can be easily increased.

  In the first embodiment, Li is diffused into the varistor element body 11 as an alkali metal. Li has a relatively small ionic radius and is liable to be dissolved in ZnO crystals. For this reason, the area | region between the two adjacent terminal electrodes 51 in the varistor element | base_body 11 can be reliably made into the state electrically insulated.

  In the first embodiment, the varistor element body 11 includes a rare earth metal, particularly Pr, as an auxiliary component for expressing varistor characteristics. When the rare earth metal is included, the varistor element body 11 becomes a dense structure. For this reason, Li hardly diffuses from the outer surface of the varistor element body 11 to a deep part, and does not reach the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. . As a result, it is possible to prevent the diffused Li from affecting the varistor characteristics generated in the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. .

  Further, in the first embodiment, the varistor element body 11 includes Pr and Ca, and the conductive paste for the connection conductor 41 and the terminal electrode 51 includes Pt. The connection conductor 41 and the terminal are provided on the varistor element body 11. The connection conductor 41 and the terminal electrode 51 are formed by applying and baking a conductive paste for the electrode 51. Thereby, the joint strength of the varistor element body 11, the connection conductor 41, and the terminal electrode 51 can be improved.

  The effect of improving the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 51 is considered to be caused by the following phenomenon when baking the conductive paste. When the conductive paste is baked on the varistor element body 11, Pr and Ca contained in the varistor element body 11 move near the surface of the varistor element body 11, that is, near the interface between the varistor element body 11 and the conductive paste. And Pr and Ca which moved to the interface vicinity of the varistor element | base_body 11 and an electrically conductive paste, and Pt contained in an electrically conductive paste mutually diffuse. When Pr, Ca, and Pt are interdiffused, a compound of Pr and Pt and a compound of Ca and Pt are formed in the vicinity (including the interface) between the varistor element body 11, the connection conductor 41, and the terminal electrode 51. May be. These compounds cause an anchor effect, and the bonding strength between the varistor element body 11, the connection conductor 41, and the terminal electrode 51 is improved.

  The terminal electrode 51 containing Pt is suitable mainly when the multilayer chip varistor 1 is mounted on an external substrate or the like by solder reflow, and can improve solder erosion resistance and solderability.

(Second Embodiment)
Next, the configuration of the multilayer chip varistor 2 according to the second embodiment will be described with reference to FIGS. FIG. 10 is a perspective view showing the multilayer chip varistor according to the second embodiment as viewed from the first main surface side of the varistor element body. FIG. 11 is a perspective view showing the multilayer chip varistor according to the second embodiment as viewed from the second main surface side of the varistor element body. FIG. 12 is a diagram for explaining a cross-sectional configuration along the line XII-XII in FIG. 10. 13 is a cross-sectional view for explaining a cross-sectional configuration along the line XIII-XIII in FIG. FIG. 14 is a cross-sectional view for explaining a cross-sectional configuration along the line XIV-XIV in FIG.

  As shown in FIGS. 10 to 14, the multilayer chip varistor 2 includes a varistor element body 11, a plurality (two in this embodiment) of connection conductors 41, and a plurality of (four in this embodiment). Terminal electrode 51 is provided. In the varistor element body 11, Li is diffused from the outer surface side.

  The varistor element body 11 is provided with a plurality (four layers in this embodiment) of conductor layers 120A to 120D. At least one varistor layer is disposed between the conductor layer 120A and the conductor layer 120B, and at least one varistor layer is disposed between the conductor layer 120C and the conductor layer 120D. It is arranged in.

  As shown in FIGS. 12 to 14, the conductor layer 120 </ b> A and the conductor layer 120 </ b> C each include one first internal electrode 121 and one internal conductor 125. In the conductor layer 120A and the conductor layer 120C, the first inner electrode 121 and the inner conductor 125 have a predetermined interval from the side surfaces parallel to the stacking direction, respectively, and have a predetermined interval so as to be electrically insulated from each other. It is arranged.

  On the other hand, each of the conductor layer 120B and the conductor layer 120D includes one second internal electrode 123 and one internal conductor 125, as shown in FIGS. In the conductor layer 120B and the conductor layer 120D, the second internal electrode 123 and the internal conductor 125 have a predetermined interval from the side surfaces parallel to the stacking direction, respectively, and have a predetermined interval so as to be electrically insulated from each other. It is arranged.

  The first internal electrode 121 of the conductor layer 120A, the second internal electrode 123 of the conductor layer 120B, and the internal conductors 125 of the conductor layers 120C and 120D are arranged on the varistor layer so as to overlap when viewed from the stacking direction. Is arranged. Also, each of the inner conductors 125 of the conductor layers 120A and 120B, the first inner electrode 121 of the conductor layer 120C, and the second inner electrode 123 of the conductor layer 120D are arranged on the varistor layer so as to overlap when viewed from the stacking direction. Is arranged. Therefore, an internal electrode pair 131 and an internal conductor pair 132, which will be described later, are positioned side by side in the stacking direction in the varistor element body 11, and are positioned in a direction substantially perpendicular to the stacking direction.

  Each first internal electrode 121 has a substantially rectangular shape. Each first internal electrode 121 is drawn out to the first main surface 13 such that one end thereof faces the first main surface 13. The first internal electrode 121 in the conductor layer 120A is at least partially opposed to the second internal electrode 123 in the conductor layer 120B with the varistor layer interposed therebetween. The first internal electrode 121 in the conductor layer 120C is at least partially opposed to the second internal electrode 123 in the conductor layer 120D with the varistor layer interposed therebetween.

  Each second internal electrode 123 has a substantially rectangular shape. Each second internal electrode 123 is drawn out to the second main surface 15 such that one end thereof faces the second main surface 15. The second internal electrode 123 in the conductor layer 120B is at least partially opposed to the first internal electrode 121 in the conductor layer 120A with the varistor layer interposed therebetween, and the second internal electrode 123 in the conductor layer 120D is At least part of the varistor layer is opposed to the first internal electrode 121 in the conductor layer 120C.

As described above, the first internal electrode 121 and the second internal electrode 123 are arranged in the varistor element body 11 so that at least some of them are opposed to each other with a predetermined distance _Di2 . . Thereby, in the multilayer chip varistor 2, a plurality of internal electrode pairs 131 including the first and second internal electrodes 121 and 123 arranged in the varistor element body 11 so that at least some of them are opposed to each other are provided. (Two in this embodiment) will be provided. Therefore, a region where the first internal electrode 121 and the second internal electrode 123 overlap in the varistor layer, that is, a region between the first internal electrode 121 and the second internal electrode 123 in the varistor element body 11. However, it functions as a region that develops varistor characteristics. The predetermined interval (D _i2 ) is set in consideration of the varistor voltage and the like, as with the above-described predetermined interval D _i1 , but is set to 20 to 60 μm, for example, in the present embodiment.

  Each inner conductor 125 has a substantially rectangular shape. Each inner conductor 125 is drawn out to the first main surface 13 so that one end thereof faces the first main surface 13, and the second main surface so that the other end faces the second main surface 15. 15 is drawn. In the present embodiment, the varistor elements 11 are arranged in the varistor element body 11 so that the inner conductors 125 in the conductor layers 120A and 20B face each other, and the varistors so that the inner conductors 125 in the conductor layers 120C and 120D face each other. It is arranged in the element body 11. As a result, the multilayer chip varistor 2 is provided with a plurality (two in this embodiment) of a pair of internal conductors 125 (internal conductor pairs 132) disposed in the varistor element body 11.

  The first and second internal electrodes 121 and 123 and the internal conductor 125 include a conductive material. The conductive material contained in the first and second internal electrodes 121 and 123 and the internal conductor 125 is not particularly limited, but is preferably made of Pd or an Ag—Pd alloy. The thicknesses of the first and second internal electrodes 121 and 123 and the internal conductor 125 can be set to about 0.5 to 5 μm, for example.

  Here, the first main surface 13 and the second main surface 15 are in a direction along the stacking direction (a parallel direction in the present embodiment), and the first and second inner electrodes 121 and 123 and the inner conductor 125. Extends in the direction intersecting (in the present embodiment, the direction orthogonal). The stacking direction is a direction parallel to the opposing direction of the first internal electrode 121 and the second internal electrode 123 (the opposing direction of the internal conductors 125), and the first and second internal electrodes 121 and 123 are parallel to each other. In addition, the direction is orthogonal to the inner conductor 125.

  As shown in FIGS. 12 and 14, each connection conductor 41 is connected to the internal electrode pair 131 among the internal electrode pair 131 and the internal electrode pair 132 arranged in the stacking direction in the varistor element body 11. Each of the internal conductors 125 included in the first internal electrode 121 and the internal electrode pair 132 included is arranged on the first main surface 13 so as to cover each part drawn out to the first main surface 13. . Each portion led out to the first main surface 13 of the first inner electrode 121 and each inner conductor 125 is physically and electrically connected to the corresponding connecting conductor 41. As a result, each connection conductor 41 electrically connects the first internal electrode 121 and each internal conductor 125 positioned side by side in the stacking direction.

  In the present embodiment, the terminal electrode 51 has two first terminal electrodes 151 and two second terminal electrodes 152.

  As shown in FIGS. 12 and 14, each first terminal electrode 151 has a second second electrode so as to cover a portion drawn out to the second main surface 15 of the corresponding second inner electrode 123. Each is arranged on the main surface 15. A portion of the second internal electrode 123 drawn to the second main surface 15 is physically and electrically connected to the corresponding first terminal electrode 151. Thus, the first terminal electrode 151 is electrically connected to the corresponding second internal electrode 123, respectively.

  On the other hand, as shown in FIGS. 12 and 14, each second terminal electrode 152 covers a portion drawn out to the second main surface 15 of each internal conductor 125 included in the corresponding internal conductor pair 132. Further, they are arranged on the second main surface 15 respectively. The portion of the inner conductor 125 that is led out to the second main surface 15 is physically and electrically connected to the corresponding second terminal electrode 152. As a result, the second terminal electrode 152 is electrically connected to each internal conductor 125 included in the corresponding internal conductor pair 132.

The distance D _e3 between the two adjacent terminal electrodes 151 and 152 on the second main surface 15 is set to be _equal to the predetermined distance D _i2 described above.
0 <D _e3 ≦ 4D _i2
Is set to satisfy the relationship. Each interval D _i3 is not necessarily the same as the interval D _i1, and may be different as long as it is within a range satisfying the above relationship.

The distance D _e4 between the two connection conductors 41 on the first main surface 13 is set to the above-described predetermined distance D _i1 .
0 <D _e4 ≦ 4D _i1
Is set to satisfy the relationship.

  Here, as described above, the internal electrode pair 131 and the internal conductor pair 132 are positioned side by side in the stacking direction in the varistor element body 11 and are aligned in a direction substantially perpendicular to the stacking direction. Therefore, the second terminal electrically connected to the first terminal electrode 151 electrically connected to the second internal electrode 123 included in the internal electrode pair 131 and the respective internal conductors 125 included in the internal conductor pair 132. The terminal electrodes 152 are also arranged on the second main surface 15 so as to be positioned side by side in the stacking direction and aligned in a direction substantially perpendicular to the stacking direction. That is, the first and second terminal electrodes 151 and 152 are arranged alternately in the row direction and the column direction.

  In the multilayer chip varistor 2 having the above-described configuration, as shown in FIG. 15, two sets of varistors B that connect the first terminal electrode 151 and the second terminal electrode 152 are included. Each varistor B is composed of a first internal electrode 121, a second internal electrode 123, and a region where the first and second internal electrodes 121 and 123 overlap in the varistor layer. The connection conductor 41 extends in a direction substantially parallel to the stacking direction, and the first and second terminal electrodes 151 and 152 that are electrically connected to the varistor B are juxtaposed in the stacking direction. Each varistor B exists between the pair of first and second terminal electrodes 151 and 152 that are juxtaposed in the long side direction of the connection conductor 41.

  Since the multilayer chip varistor 2 having the above-described configuration can be manufactured in the same procedure as the multilayer chip varistor 1, the description of the manufacturing process of the multilayer chip varistor 2 is omitted.

  As described above, in the second embodiment, the plurality of first and second terminal electrodes 151 and 152 are arranged on the second main surface 15 of the varistor element body 11. Therefore, the multilayer chip varistor 2 can be mounted with the second main surface 15 facing a mounting component (for example, an electronic component or a mounting substrate), and a configuration corresponding to the BGA package is realized. It will be. Further, in the present embodiment, the connection conductor 41 is included in the internal electrode pair 131 among the internal electrode pair 131 and the internal conductor pair 132 arranged in the stacking direction in the varistor element body 11. Arranged on first main surface 13 so as to electrically connect internal electrode 121 and each internal conductor 125 included in internal conductor pair 132. Therefore, the varistor element body 11 has a region functioning as the varistor B at a position corresponding to the connection conductor 41. Therefore, the connection conductor 41 is a mark for identifying the mounting direction of the multilayer chip varistor 2. Thus, the multilayer chip varistor 2 can be mounted appropriately and easily.

  Incidentally, in the multilayer chip varistor 2, as described above, Li is diffused from the outer surface of the varistor element body 11, so that the region near the outer surface of the varistor element body 11 has an extremely high electric resistance and is substantially reduced. Is electrically insulated. That is, a region between two adjacent terminal electrodes 151 and 152 in the varistor element body 11 is substantially electrically insulated, and varistor characteristics are unlikely to occur in the region. For this reason, the varistor voltage in the region between the two adjacent terminal electrodes 151 and 152 in the varistor element body 11 is the varistor in the region between the first internal electrode 121 and the second internal electrode 123 in the varistor element body 11. Extremely higher than voltage. The varistor voltage in the region between the two connection conductors 41 in the varistor element body 11 is also extremely higher than the varistor voltage in the region between the first internal electrode 23 and the second internal electrode 33 in the varistor element body 11. Become.

Thus, narrow spacing _{D e2} between the two terminal electrodes 151 and 152 adjacent the second major surface 15 on a predetermined between said interval and the first internal electrode 121 and the second internal electrode 123 The interval D _i2 of
0 <D _e2 ≦ 4D _i2
The distance D _e2 between the two connection conductors 41 on the first main surface 13 and the predetermined distance D _i1 are
0 <D _e4 ≦ 4D _i1
Even when the above relationship is satisfied, varistor characteristics are unlikely to occur in the region between the two adjacent terminal electrodes 151 and 152 in the varistor element body 11 and the region between the two connection conductors 41 in the varistor element body 11. Even if varistor characteristics occur in the region between the two adjacent terminal electrodes 151 and 152 in the varistor element body 11 and in the region between the two connection conductors 41 in the varistor element body 11, the varistor characteristics are as follows. 11 is negligible for the varistor characteristics generated in the region between the first internal electrode 121 and the second internal electrode 123. As a result, the varistor characteristics are suppressed from occurring in a region other than the region between the first internal electrode 121 and the second internal electrode 123 in the varistor element body 11, and the multilayer chip varistor 2 is desired. Varistor characteristics can be obtained.

(Third embodiment)
Next, the configuration of the multilayer chip varistor 3 according to the third embodiment will be described with reference to FIGS. FIG. 16 is a schematic top view showing the multilayer chip varistor according to the third embodiment. FIG. 17 is a schematic bottom view showing the multilayer chip varistor according to the third embodiment. FIG. 18 is a view for explaining a cross-sectional configuration along the line XVIII-XVIII in FIG. FIG. 19 is a view for explaining a cross-sectional configuration along the line XIX-XIX in FIG. FIG. 20 is a diagram for explaining a cross-sectional configuration along the line XX-XX in FIG.

  As shown in FIGS. 4 to 8, the multilayer chip varistor 3 includes a plurality of varistor elements 11 each having a substantially rectangular plate shape and a plurality of (two) main surfaces arranged on the second main surface 15 of the varistor element body 11. In the present embodiment, 25 external electrodes 225 to 229 and a plurality (20 in the present embodiment) of external electrodes 230a to 230a disposed on the first main surface 13 of the varistor element body 11, respectively. 230d. For example, the varistor element body 11 is set to have a length of about 3 mm, a width of about 3 mm, and a thickness of about 0.5 mm. The external electrodes 225, 226, 228 and 229 function as input / output terminal electrodes of the multilayer chip varistor 3, and the external electrode 227 functions as a ground terminal electrode of the multilayer chip varistor 3. The external electrodes 230a to 230d function as pad electrodes that are electrically connected to resistors 261 and 263 described later. In the varistor element body 11, an alkali metal (Li in this embodiment) is diffused from the outer surface side.

  In the varistor element body 11, a plurality of first to third internal electrode layers 231, 241, 251 are arranged. Each of the first to third internal electrode layers 231, 241, 251 of each layer is used as an internal electrode group, and a plurality of internal electrode groups are arranged along the stacking direction in the varistor element body 11 (five in this embodiment). Has been placed. In each internal electrode group, the first to third internal electrode layers 231, 241, 251 have a first internal electrode layer 231 and a second internal electrode layer so that at least one varistor layer is interposed therebetween. 241 and the third internal electrode layer 251 are arranged in this order. Each internal electrode group is also arranged so that at least one varistor layer is interposed between them. In the actual multilayer chip varistor 3, the plurality of varistor layers are integrated so that the boundary between them cannot be visually recognized.

  As shown in FIG. 18, each first internal electrode layer 231 includes a first internal electrode 233 and a second internal electrode 235. Each of the first and second internal electrodes 233 and 235 has a substantially rectangular shape. The first and second internal electrodes 233 and 235 have a predetermined interval so as to be electrically insulated from each other at a position having a predetermined interval from a side surface parallel to the stacking direction in the varistor element body 11. Each is arranged.

  Each first internal electrode 233 is electrically connected to the external electrode 225 via the lead conductor 237a and electrically connected to the external electrode 230a via the lead conductor 237b. The lead conductors 237a and 237b are formed integrally with the first internal electrode 233. The lead conductor 237 a extends from the first internal electrode 233 so as to face the second main surface 15 of the varistor element body 11. The lead conductor 237 b extends from the first internal electrode 233 so as to face the first main surface 13 of the varistor element body 11.

  Each second internal electrode 235 is electrically connected to the external electrode 229 via the lead conductor 239a and electrically connected to the external electrode 230b via the lead conductor 239b. The lead conductors 239a and 239b are formed integrally with the second internal electrode 235. The lead conductor 239 a extends from the second internal electrode 235 so as to face the second main surface 15 of the varistor element body 11. The lead conductor 239 b extends from the second internal electrode 235 so as to face the first main surface 13 of the varistor element body 11.

  Each second internal electrode layer 241 includes a third internal electrode 243 as shown in FIG. Each third internal electrode 243 has a substantially rectangular shape. The third internal electrode 243 is disposed at a position having a predetermined interval from a side surface parallel to the stacking direction in the varistor element body 11 so as to overlap the first and second internal electrodes 233 and 235 when viewed from the stacking direction. Is done. Each third internal electrode 243 is electrically connected to the external electrode 227 via a lead conductor 247. The lead conductor 247 is formed integrally with the third internal electrode 243, and extends from the third internal electrode 243 so as to face the second main surface 15 of the varistor element body 11.

  Each third internal electrode layer 251 includes a fourth internal electrode 253 and a fifth internal electrode 255 as shown in FIG. Each of the fourth and fifth internal electrodes 253 and 255 has a substantially rectangular shape. The fourth and fifth internal electrodes 253 and 255 overlap with the third internal electrode 243 when viewed from the stacking direction at positions having a predetermined interval from the side surface parallel to the stacking direction in the varistor element body 11 and are electrically connected to each other. Are arranged at predetermined intervals so as to be electrically insulated.

  Each fourth internal electrode 253 is electrically connected to the external electrode 226 via the lead conductor 257a and is electrically connected to the external electrode 230c via the lead conductor 257b. The lead conductors 257a and 257b are formed integrally with the fourth internal electrode 253. The lead conductor 257 a extends from the fourth internal electrode 253 so as to face the second main surface 15 of the varistor element body 11. The lead conductor 257 b extends from the fourth internal electrode 253 so as to face the first main surface 13 of the varistor element body 11.

  Each fifth internal electrode 255 is electrically connected to the external electrode 228 via the lead conductor 259a and electrically connected to the external electrode 230d via the lead conductor 259b. The lead conductors 259a and 259b are formed integrally with the fifth internal electrode 255. The lead conductor 259 a extends from the fifth internal electrode 255 so as to face the second main surface 15 of the varistor element body 11. The lead conductor 259 b extends from the fifth internal electrode 255 so as to face the first main surface 13 of the varistor element body 11.

  The first to fifth internal electrodes 233, 235, 243, 253, and 255 contain Pd or an Ag—Pd alloy. The lead conductors 237a, 237b, 239a, 239b, 247, 257a, 257b, 259a, and 259b also contain Pd or an Ag—Pd alloy.

  The external electrodes 225 to 229 are two-dimensionally arranged on the second main surface 15 in M rows and N columns (each of the parameters M and N is an integer of 2 or more). In the present embodiment, the external electrodes 225 to 229 are two-dimensionally arranged in 5 rows and 5 columns. The external electrodes 225 to 229 have a rectangular shape (in this embodiment, a square shape). In the external electrodes 225 to 229, for example, the length of each side is set to about 300 μm, and the thickness is set to about 2 μm.

  The external electrodes 225 to 229 are disposed on the outer surface of the varistor element body 11 and contain Pt. The external electrodes 225 to 229 are formed by baking a conductive paste. As the conductive paste, a mixture of metal powder containing Pt particles as a main component and glass frit, an organic binder, and an organic solvent is used.

  The external electrode 230 a and the external electrode 230 b are arranged on the first main surface 13 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers and parallel to the first main surface 13. The external electrode 230c and the external electrode 230d are arranged on the first main surface 13 with a predetermined interval in a direction perpendicular to the stacking direction of the varistor layers and parallel to the first main surface 13. The predetermined interval between the external electrode 230a and the external electrode 230b and the predetermined interval between the external electrode 230c and the external electrode 230d are set to be the same. The external electrodes 230a to 230d have a rectangular shape (in this embodiment, a rectangular shape). The external electrodes 230a and 230b have, for example, a long side length of about 1000 μm, a short side length of about 150 μm, and a thickness of about 2 μm. The external electrodes 230c and 230d have, for example, a long side length of about 500 μm, a short side length of about 150 μm, and a thickness of about 2 μm.

  As with the external electrodes 225 to 229, the external electrodes 230a to 230d are formed by baking a conductive paste. As this conductive paste, a mixture of a metal powder mainly composed of Pt particles and a glass frit, an organic binder, and an organic solvent is used.

A resistor 261 is disposed on the first main surface 13 so as to be spanned between the external electrode 230a and the external electrode 230b, and has a resistance so as to be spanned between the external electrode 230c and the external electrode 230d. A body 263 is arranged. The resistors 261 and 263 are formed by applying a Ru-based, Sn-based or La-based resistor paste. As the Ru-based resistance paste, a mixture of RuO ₂ and glass such as Al ₂ O ₃ —B ₂ O ₂ —SiO ₂ can be used. As the Sn-based resistance paste, a mixture of SnO ₂ and glass such as Al ₂ O ₃ —B ₂ O ₃ —SiO ₂ can be used. As the La-based resistance paste, a mixture of LaB ₆ and glass such as Al ₂ O ₃ —B ₂ O ₃ —SiO ₂ can be used.

  One end of the resistor 261 is electrically connected to the first internal electrode 233 through the external electrode 230a and the lead conductor 237b. The other end of the resistor 261 is electrically connected to the second internal electrode 235 through the external electrode 230b and the lead conductor 239b. One end of the resistor 263 is electrically connected to the fourth internal electrode 253 through the external electrode 230c and the lead conductor 257b. The other end of the resistor 263 is electrically connected to the fifth internal electrode 255 through the external electrode 230d and the lead conductor 259b.

As described above, the third internal electrode 243 is disposed so as to overlap the first and second internal electrodes 233 and 235 when viewed from the stacking direction. That is, as described above, the third internal electrode 243 and the first and second internal electrodes 233 and 235 are arranged such that at least some of them are opposed to each other with a predetermined distance _Di3. It is arranged in the body 11. Therefore, the region between the first internal electrode 233 and the third internal electrode 243 in the varistor layer functions as a region that develops varistor characteristics, and the second internal electrode 235 and the third internal electrode 243 in the varistor layer. The region between the two functions as a region expressing the varistor characteristics.

As described above, the third internal electrode 243 is disposed so as to overlap the fourth and fifth internal electrodes 253 and 255 when viewed from the stacking direction. That is, the third inner electrode 243 and the fourth and fifth internal electrodes 253 and 255, as described above, as to each other at least partially face each other at a predetermined distance D _i3, varistor element It is arranged in the body 11. Therefore, the region between the fourth internal electrode 253 and the third internal electrode 243 in the varistor layer functions as a region that develops varistor characteristics, and the fifth internal electrode 255 and the third internal electrode 243 in the varistor layer. The region between the two functions as a region expressing the varistor characteristics.

A distance D _e5 between two adjacent external electrodes 225 to 229 on the second main surface 15 is set to be equal to the predetermined distance D _i3 described above.
0 <D _e5 ≦ 4D _i3
Is set to satisfy the relationship. The intervals D _e5 do not have to be the same, and may be different as long as they are within a range that satisfies the above relationship.

The distance D _e6 between the two external electrodes 230a and 230c adjacent to each other in the stacking direction on the first main surface 13 is the above-described predetermined distance D _i3 .
0 <D _e6 ≦ 4D _i3
Is set to satisfy the relationship. The distance D _e6 between the two external electrodes 230b and 230d adjacent to each other in the stacking direction on the first main surface 13 is also larger than the predetermined distance D _i3 described above.
0 <D _e6 ≦ 4D _i3
Is set to satisfy the relationship. The intervals D _e6 do not have to be the same, and may be different as long as they are within a range that satisfies the above relationship.

  In the multilayer chip varistor 3 having the above-described configuration, as shown in FIG. 21, the resistor R, the varistor B1, and the varistor B2 are connected in a π-type. The resistor R is configured by the resistor 261 or the resistor 263. The varistor B1 is formed by the first internal electrode 233, the third internal electrode 243, and the region overlapping the first and third internal electrodes 233, 243 in the varistor layer, or the fourth internal electrode 253 and the third internal electrode 253. The internal electrode 243 and a region overlying the fourth and third internal electrodes 253 and 243 in the varistor layer are configured. The varistor B2 is formed by the second internal electrode 235, the third internal electrode 243, and the region overlapping the second and third internal electrodes 235, 243 in the varistor layer, or the fifth internal electrode 255 and the third internal electrode. The internal electrode 243 and a region overlapping the fifth and third internal electrodes 255 and 243 in the varistor layer.

  Since the multilayer chip varistor 3 having the above-described configuration can be manufactured in substantially the same procedure as the multilayer chip varistors 1 and 2, description of the manufacturing process of the multilayer chip varistor 3 is omitted. In the case of the multilayer chip varistor 3, a step of forming the resistors 261 and 263 is added after the step of forming the external electrodes 225 to 229 and 230a to 230d.

  As described above, according to the third embodiment, the external electrodes 225, 226, 228, and 229 that function as input / output terminal electrodes and the external electrode 227 that functions as a ground terminal electrode are both included in the second varistor element body 11. The main surface 15 is disposed. Therefore, the multilayer chip varistor 3 can be mounted with the second main surface 15 facing a mounting component (for example, an electronic component or a mounting substrate), and a configuration corresponding to the BGA package is realized. It will be.

  By the way, in the multilayer chip varistor 3, as described above, Li is diffused from the outer surface of the varistor element body 11. Is electrically insulated. That is, a region between two adjacent external electrodes 225 to 229 in the varistor element body 11 is substantially electrically insulated, and varistor characteristics hardly occur in the region. For this reason, the varistor voltage in the region between the two adjacent external electrodes 225 to 229 in the varistor element body 11 is different between the third internal electrode 243 and the first and second internal electrodes 233 and 235 in the varistor element body 11. The varistor voltage in the region between them and the varistor voltage in the region between the third internal electrode 243 and the fourth and fifth internal electrodes 253 and 255 in the varistor element body 11 are extremely higher.

  The varistor voltage in the region between the two external electrodes 230a and 230c adjacent to each other in the stacking direction in the varistor element body 11 is also the same between the third internal electrode 243 and the first and second internal electrodes 233 and 235 in the varistor element body 11. The varistor voltage in the region between them and the varistor voltage in the region between the third internal electrode 243 and the fourth and fifth internal electrodes 253 and 255 in the varistor element body 11 are extremely higher. The varistor voltage in the region between the two external electrodes 230b and 230d adjacent to each other in the stacking direction in the varistor element body 11 is also the same between the third internal electrode 243 and the first and second internal electrodes 233 and 235 in the varistor element body 11. The varistor voltage in the region between them and the varistor voltage in the region between the third internal electrode 243 and the fourth and fifth internal electrodes 253 and 255 in the varistor element body 11 are extremely higher.

Thus, narrow spacing _{D e5} between the two external electrodes 225 to 229 adjacent to the second major surface 15 on,
0 <D _e5 ≦ 4D _i3
Consisting satisfy the relation, two external electrodes 230a that adjoin in the stacking direction on the first major surface 13, two external electrodes 230b adjacent in the stacking direction in the interval _{D e6} and on the first major surface 13 between 230c, The distance D _e6 between 230d is narrow,
0 <D _e6 ≦ 4D _i3
Even if the relationship is satisfied, a region between two adjacent external electrodes 225 to 229 in the varistor element body 11, a region between two external electrodes 230a and 230c adjacent in the stacking direction in the varistor element body 11, and In the region between the two external electrodes 230b and 230d adjacent to each other in the stacking direction in the varistor element body 11, varistor characteristics are hardly generated. Even if varistor characteristics occur in these regions of the varistor element body 11, the varistor characteristics are between the third internal electrode 243 and the first and second internal electrodes 233 and 235 in the varistor element body 11. The varistor characteristics occurring in this region and the varistor characteristics occurring in the region between the third internal electrode 243 and the fourth and fifth internal electrodes 253 and 255 in the varistor element body 11 can be ignored.

  As a result, the region between the third internal electrode 243 and the first and second internal electrodes 233 and 235 in the varistor element body 11, and the third internal electrode 243 and the fourth and The occurrence of varistor characteristics outside the region between the fifth internal electrodes 253 and 255 is suppressed, and the multilayer chip varistor 3 can obtain desired varistor characteristics.

  The preferred embodiments of the present invention have been described above. However, the present invention is not necessarily limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

  In the present embodiment, Li is used as the alkali metal diffused in the varistor element body 11, but the present invention is not limited to this, and Na, K, Rb, or Cs may be used.

  In the present embodiment, Li is diffused from the entire outer surface of the varistor element body 11. However, the present invention is not limited to this, and external electrodes (connection conductor 41, terminal electrodes 51, 151, 152, and external electrodes 225-) 229, 230a to 230d) may be diffused only from the outer surface (the first main surface 13 and the second main surface 15). Further, Li may be diffused only from a region between two adjacent external electrodes on the outer surface of the varistor element body 11.

  In the present embodiment, the external electrodes (the connection conductor 41, the terminal electrodes 51, 151, and 152, and the external electrodes 225 to 229 and 230a to 230d) are formed by a printing method (coating and baking a conductive paste). Not limited to this. External electrodes (connection conductor 41, terminal electrodes 51, 151, 152, and external electrodes 225 to 229, 230a to 230d) are formed by plating, particularly vacuum plating (vacuum deposition, sputtering, ion plating, etc.). It may be formed.

  In this embodiment, Li is diffused in the varistor element body 11 before forming the external electrodes (the connection conductor 41, the terminal electrodes 51, 151, and 152, and the external electrodes 225 to 229 and 230a to 230d). It is not limited to this. Li may be diffused into the varistor element body 11 after forming the external electrodes (connection conductor 41, terminal electrodes 51, 151, 152, and external electrodes 225 to 229, 230a to 230d).

  In the present embodiment, the external electrodes (connection conductor 41, terminal electrodes 51, 151, 152, and external electrodes 225 to 229, 230a to 230d) are arranged on the pair of main surfaces 13 and 15, respectively. I can't. The present invention can be applied to any varistor provided with a plurality of external electrodes arranged adjacent to one outer surface of a sintered body.

  EXAMPLES Hereinafter, although an Example demonstrates this invention still in detail, this invention is not limited to these Examples.

In this example, a multilayer chip varistor having the same configuration as that of the multilayer chip varistor 1 according to the first embodiment is manufactured, and one terminal electrode 51 and the other terminal electrode 51 of two varistors B connected in series are formed. varistor voltage between (hereinafter, referred to as the varistor voltage V _{1 LINE)} and the terminal electrode of the two varistors B connected in series in the terminal electrode 51 and the other set of two varistors B connected in series in one set The varistor voltage with respect to 51 (hereinafter referred to as varistor voltage _V2line ) was measured. As the varistor voltage V _1line and the varistor voltage V _2line , a varistor voltage V _1mA (unit: V) when a current of 1 mA was passed was measured.

Regarding the varistor material, 99.9% purity ZnO (97.725 mol%), Pr (0.5 mol%), Co (1.5 mol%), Al (0.005 mol%), K ( 0.05 mol%), Cr (0.1 mol%), Ca (0.1 mol%) and Si (0.02 mol%) were added. Regarding the Li diffusion treatment, the obtained varistor element body 11 was mixed with Li ₂ CO ₃ powder (average particle size: 3 μm) in a sealed rotating pot, and 1 μg of Li ₂ CO ₃ powder per piece was mixed. Attached. The amount of Li ₂ CO ₃ powder introduced into the sealed rotating pot was in the range of 0.01 μg to 10 mg per piece. The heat treatment temperature was 900 ° C., and the heat treatment time was 10 minutes.

Example 1
The multilayer chip varistor was designed so that the distance D _i1 between the first internal electrode 23 and the second internal electrode 33 was set to 20 μm and a varistor voltage V _{1 mA of} 27 V was obtained. Interval _{D e2} between spacing _{D e1} and two connecting conductors 41 between the two terminal electrodes 51, 20μm, 40μm, 60μm, 80μm , 90μm, a multilayer chip varistor respectively set to 100 [mu] m, subjected to Li diffusion process Five samples were prepared for each case and when not, and the varistor voltage V _1line and varistor voltage V _{2line of} each sample were measured. The measurement results are shown in FIG.

(Example 2)
The multilayer chip varistor was designed so that the distance D _i1 between the first internal electrode 23 and the second internal electrode 33 was set to 40 μm, and a varistor voltage V _{1 mA of} 54 V was obtained. Interval _{D e2} between spacing _{D e1} and two connecting conductors 41 between the two terminal electrodes 51, 20μm, 40μm, 80μm, 120μm , 160μm, 180μm, a multilayer chip varistor respectively set to 200 [mu] m, Li diffusion process Five samples were prepared for each of the cases in which the varistor was performed and not performed, and the varistor voltage V _1line and varistor voltage V _{2line of} each sample were measured. The measurement results are shown in FIG.

(Example 3)
The multilayer chip varistor was designed so that the distance D _i1 between the first internal electrode 23 and the second internal electrode 33 was set to 60 μm and a varistor voltage V _{1 mA of} 81 V was obtained. Interval _{D e2} between spacing _{D e1} and two connecting conductors 41 between the two terminal electrodes 51, 20μm, 60μm, 120μm, 180μm , 240μm, 270μm, a multilayer chip varistor respectively set to 300 [mu] m, Li diffusion process Five samples were prepared for each of the cases in which the varistor was performed and not performed, and the varistor voltage V _1line and varistor voltage V _{2line of} each sample were measured. The measurement results are shown in FIG.

22 to 24, “-” exceeds the measurable range (up to 200V) of the used measuring instrument (KEITHLEY2400 SourceMeter manufactured by Keithley Instruments, Inc.), and the varistor voltage V _2line can be measured properly. It shows that there was not.

In Examples 1 to 3, the relationship between the distance D _i1 and the distance D _e1 is D _e1 ≦ 4D _i1.
And the relationship between the interval D _i1 and the interval D _e2 is D _e1 ≦ 4D _i2
In the multilayer chip varistor satisfying the above, when the Li diffusion process is not performed, the CV (variation coefficient) is larger than 5%, and the varistor voltage V _1line varies greatly with _respect to each design value. On the other hand, when the Li diffusion process is performed, the CV is 5% or less, and the variation of the varistor voltage V _1line with respect to the design value is extremely small. The reason why the criterion is 5% is that a varistor having an ESD protection level suitable for stable circuit design and practical use can be realized.

In the multilayer chip varistor satisfying the above relationship, the varistor voltage _V2line could be measured when the Li diffusion treatment was not performed. As a result, varistor characteristics are generated in a region between the terminal electrodes 51 of two varistors B connected in series in one set and the terminal electrodes 51 of two varistors B connected in series in the other set. Can understand. On the other hand, when Li diffusion treatment was performed, the varistor voltage V _2line exceeded the measurable range and could not be measured. As a result, varistor characteristics are substantially generated in a region between the terminal electrodes 51 of two varistors B connected in series in one set and the terminal electrodes 51 of two varistors B connected in series in the other set. I can understand that.

In Examples 1 to 3, the relationship between the interval D _i1 and the interval D _e1 is D _e1 > 4D _i1
And the relationship between the distance D _i1 and the distance D _e2 is D _e1 > 4D _i2
In the multilayer chip varistor satisfying the above, CV is smaller than 5% regardless of the presence or absence of the Li diffusion treatment, and the variation of the varistor voltage V _1line with respect to the design value is extremely small. Further, the varistor voltage V _2line also exceeds the measurable range. Therefore, the varistor characteristic is substantially in a region between the terminal electrodes 51 of the two varistors B connected in series in one set and the terminal electrodes 51 of the two varistors B connected in series in the other set. It is thought that it has not occurred.

  From the above, the effectiveness of the present invention was confirmed.

In Example 3, in the multilayer chip varistor having the distance D _e1 of 180 μm and 240 μm, the varistor voltage V _2line exceeded the measurable range even when Li diffusion treatment was not performed. This is because the distance D _e1 is large, so that in the region between the terminal electrodes 51 of two varistors B connected in series in one set and the terminal electrodes 51 of two varistors B connected in series in the other set. Although varistor characteristics have occurred, it is considered that the varistor voltage V _2line was not within the measurable range.

1 is a perspective view showing a multilayer chip varistor according to a first embodiment. 1 is a perspective view showing a multilayer chip varistor according to a first embodiment. It is a figure for demonstrating the cross-sectional structure along the III-III line | wire of FIG. It is a figure for demonstrating the cross-sectional structure along the IV-IV line | wire of FIG. It is a figure for demonstrating the cross-sectional structure along the VV line of FIG. It is a figure for demonstrating the equivalent circuit of the multilayer chip varistor which concerns on 1st Embodiment. It is a flowchart for demonstrating the manufacturing process of the multilayer chip varistor which concerns on 1st Embodiment. It is a figure for demonstrating the manufacturing process of the multilayer chip varistor which concerns on 1st Embodiment. It is a schematic diagram for demonstrating the structure of the multilayer chip varistor concerning 1st Embodiment. It is a perspective view which shows the multilayer chip varistor concerning 2nd Embodiment. It is a perspective view which shows the multilayer chip varistor concerning 2nd Embodiment. It is a figure for demonstrating the cross-sectional structure along the XII-XII line | wire of FIG. It is sectional drawing for demonstrating the cross-sectional structure along the XIII-XIII line | wire of FIG. It is sectional drawing for demonstrating the cross-sectional structure along the XIV-XIV line | wire of FIG. It is a figure for demonstrating the equivalent circuit of the multilayer chip varistor which concerns on 2nd Embodiment. It is a schematic top view which shows the multilayer chip varistor concerning 3rd Embodiment. It is a schematic bottom view which shows the multilayer chip varistor concerning 3rd Embodiment. It is a figure for demonstrating the cross-sectional structure along the XVIII-XVIII line | wire in FIG. It is a figure for demonstrating the cross-sectional structure along the XIX-XIX line | wire in FIG. It is a figure for demonstrating the cross-sectional structure along the XX-XX line in FIG. It is a figure for demonstrating the equivalent circuit of the multilayer chip varistor which concerns on 3rd Embodiment. 6 is a chart showing measurement results of varistor voltage in Example 1. 10 is a chart showing measurement results of varistor voltage in Example 2. 6 is a chart showing measurement results of varistor voltage in Example 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1-3 ... Stack type chip varistor, 11 ... Varistor element | base_body, 11a ... Area | region where Li was diffused, 13 ... 1st main surface, 15 ... 2nd main surface, 23 ... 1st internal electrode, 33 ... 2nd internal electrode, 41 ... connecting conductor, 51 ... terminal electrode, 121 ... 1st internal electrode, 123 ... 2nd internal electrode, 151 ... 1st terminal electrode, 152 ... 2nd terminal electrode, 225- 229, 230a to 230d ... external electrodes, 233 ... first internal electrode, 235 ... second internal electrode, 243 ... third internal electrode, 253 ... fourth internal electrode, 255 ... fifth internal electrode.

Claims (1)

A sintered body mainly composed of ZnO and exhibiting voltage nonlinear characteristics;
A plurality of internal electrodes arranged in the sintered body so as to face each other at a predetermined interval;
A plurality of external electrodes arranged adjacent to one outer surface of the sintered body,
The distance (D _e ) between the plurality of external electrodes on the one outer surface is greater than the predetermined distance (D _i ) between the plurality of internal electrodes.
0 <D _e ≦ 4D _i
Satisfy the relationship
At least between the plurality of external electrodes in the sintered body, a region having a varistor voltage higher than a varistor voltage in a region between the plurality of internal electrodes in the sintered body is formed from the one outer surface side ,
The region having a varistor voltage higher than the varistor voltage of the region between the plurality of internal electrodes in the sintered body is formed by diffusing Li from the one outer surface side,
A varistor , wherein the sintered body contains Pr as a subcomponent for expressing voltage nonlinear characteristics .

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