JP4710654B2 - Manufacturing method of multilayer chip varistor - Google Patents

Description

  The present invention relates to a varistor manufacturing method, and more particularly to a multilayer chip varistor manufacturing method.

Conventionally, a varistor manufacturing method in the field of this technology is disclosed in, for example, Patent Document 1 below. This publication discloses a varistor containing Pr as a varistor material. In the firing step when producing this varistor, firing had to be performed at a firing temperature as high as about 1200 ° C., for example. When firing at such a high temperature, there are various problems such as crystal grain overgrowth and damage to the firing furnace. Therefore, in recent years, research on varistors capable of firing at lower temperatures has been underway.
JP 2002-246207 A

  However, simply lowering the varistor firing temperature from the conventional temperature increases the leakage current (leakage current) flowing between the electrode layers, making it difficult to obtain sufficient varistor characteristics.

  Accordingly, the present invention has been made to solve the above-described problems, and provides a method for manufacturing a multilayer chip varistor capable of fabricating a multilayer chip varistor having sufficient varistor characteristics even when fired at a low temperature. The purpose is to provide.

  A manufacturing method of a multilayer chip varistor according to the present invention includes a step of preparing a varistor material containing Zn, Pr, Co, and Ag, a step of preparing a glass containing Zn, B, and Si, and a powder of the varistor material. A step of forming a sheet containing mixed powder obtained by mixing glass powder, a step of applying an electrode paste containing Pd or Ag-Pd on the sheet, and a plurality of sheets coated with the electrode paste And the step of forming the laminated body and the step of firing the laminated body to form the fired body, and the amounts of Pr and Ag present in the grain boundaries of the fired body are present in the grains of the fired body. More than the amount of Pr and Ag.

  In this method of manufacturing a multilayer chip varistor, a mixed powder obtained by mixing glass powder with varistor material powder is used, so that the firing temperature during firing is reduced. Moreover, in this manufacturing method, in the fired body obtained by firing the laminate, the amount of Pr and Ag present in the grain boundaries of the particles mainly composed of ZnO is the same as that of Pr and Ag present in the grains. Therefore, the resistance at the grain boundary is increased, and a multilayer chip varistor having practically sufficient varistor characteristics can be obtained even at a low firing temperature.

  Moreover, it is preferable that the baking temperature which bakes a laminated body is 850-1100 degreeC. By firing the laminated body at a low firing temperature within this range, it is possible to eliminate various problems caused by firing at a high temperature, and to obtain a multilayer chip varistor having practically sufficient varistor characteristics.

  Moreover, it is preferable that the addition amount of the glass powder in mixed powder is 0.05-7 wt% with respect to the mixed powder except glass powder. When the addition amount of the glass powder is within this range, a reduction in the firing temperature by the glass is manifested, and a situation in which Pr is discharged from the grain boundary can be avoided.

  According to the present invention, there is provided a method for manufacturing a multilayer chip varistor capable of producing a multilayer chip varistor having sufficient varistor characteristics even when firing at a low temperature.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments that are considered to be best for carrying out a method for manufacturing a multilayer chip varistor according to the present invention will be described below in detail with reference to the accompanying drawings. In addition, the same code | symbol is attached | subjected about the same or equivalent element, and the description is abbreviate | omitted when description overlaps.

  First, the configuration of a multilayer chip varistor 1 according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a view showing a cross-sectional configuration of a multilayer chip varistor according to an embodiment of the present invention.

  As shown in FIG. 1, the multilayer chip varistor 1 includes a varistor element body 3 and a pair of external electrodes 5 respectively formed on end faces facing each other in the varistor element body 3. The varistor element body 3 includes a varistor part 7 and a pair of outer layer parts 9 arranged so as to sandwich the varistor part 7, and is configured as a laminated body in which the varistor part 7 and the pair of outer layer parts 9 are laminated. Has been. The varistor element body 3 has a rectangular parallelepiped shape. For example, the length is set to 1.6 mm, the width is set to 0.8 mm, and the height is set to 0.8 mm. That is, the multilayer chip varistor 1 is a so-called 1608 type multilayer chip varistor.

  The varistor portion 7 includes a varistor layer 11 that exhibits varistor characteristics, and a pair of internal electrodes 13 that are disposed so as to sandwich the varistor layer 11. In the varistor part 7, the varistor layers 11 and the internal electrodes 13 are alternately laminated. A region 11 a overlapping the pair of internal electrodes 13 in the varistor layer 11 functions as a region that develops varistor characteristics.

  The varistor layer 11 contains ZnO (zinc oxide) as a main component and also includes rare earth metal elements, Co, IIIb group elements (B, Al, Ga, In), Si, Cr, Mo, Ag, and alkali metal elements as subcomponents. It consists of a simple substance such as (K, Rb, Cs) and an alkaline earth metal element (Mg, Ca, Sr, Ba) or an element containing these oxides. In the present embodiment, the varistor layer 11 includes Pr, Co, Ag, Cr, Ca, Si, K, Al, and the like as subcomponents. Thereby, the region 11a overlapping the pair of internal electrodes 13 in the varistor layer 11 contains ZnO as a main component and contains Pr, Co, and Ag.

  In the present embodiment, Pr is used as the rare earth metal. Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. The ZnO content in the varistor layer 11 is not particularly limited, but is usually 99.8 to 69.0% by mass when the total material constituting the varistor layer 11 is 100% by mass. The thickness of the varistor layer 11 is, for example, about 5 to 60 μm.

  The pair of internal electrodes 13 are provided substantially in parallel so that one end portions of the pair of internal electrodes 13 are alternately exposed on opposite end surfaces of the varistor element body 3. Each internal electrode 13 is electrically connected to the external electrode 5 at each one end. The internal electrode 13 contains Pd as a conductive material. The conductive material included in the internal electrode 13 only needs to contain Pd, and may be, for example, an Ag—Pd alloy. The thickness of the internal electrode 13 is, for example, about 0.5 to 5 μm.

  Similar to the varistor layer 11, the outer layer portion 9 contains ZnO as a main component and also includes rare earth metal elements, Co, IIIb group elements (B, Al, Ga, In), Si, Cr, Mo, Ag, as subcomponents. It consists of elemental bodies containing simple metals such as alkali metal elements (K, Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and oxides thereof. In the present embodiment, the outer layer portion 9 includes Pr, Co, Cr, Ag, Ca, Si, K, Al, and the like as subcomponents. As a result, the outer layer portion 9 contains ZnO as a main component and contains Pr, Co, and Ag. The thickness of the outer layer portion 9 is, for example, about 0.10 to 0.38 mm.

  The external electrode 5 is provided so as to cover both end faces of the varistor element body 3. The pair of external electrodes 5 includes a first electrode layer 5a and a second electrode layer 5b. The first electrode layer 5 a is formed on the outer surface of the varistor element body 3. The first electrode layer 5a is formed by firing a conductive paste as will be described later.

  The second electrode layer 5b is formed on the first electrode layer 5a by a plating method. In the present embodiment, the second electrode layer 5b includes a Ni plating layer formed by Ni plating on the first electrode layer 5a and a Sn plating layer formed by Sn plating on the Ni plating layer. It is out. The second electrode layer 5b is formed mainly for the purpose of improving the resistance to solder erosion and soldering when the multilayer chip varistor 1 is mounted on an external substrate or the like by solder reflow.

  The second electrode layer 5b is not necessarily limited to the combination of materials described above as long as the purpose of improving the resistance to solder erosion and soldering is achieved. Other materials that can form the plating layer include, for example, Sn—Pb alloy and the like, and may be used in combination with the above-described Ni or Sn. Further, the plating layer is not necessarily limited to the two-layer structure, and may have a structure of one layer or three or more layers.

  Next, a manufacturing process of the multilayer chip varistor 1 having the above-described configuration will be described with reference to FIGS. FIG. 2 is a flowchart for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment. FIG. 3 is a view for explaining the manufacturing process of the multilayer chip varistor according to the present embodiment.

  First, as a varistor material, Zn, Pr, Co, Cr, Ag, Ca, Si, K, and a trace additive such as an oxide such as Al or a metal are prepared. In addition, glass containing Zn, B and Si is prepared. (Step 10)

  Next, after weighing each of the varistor materials so as to have a predetermined ratio, the materials are mixed and pulverized to prepare varistor material powder. Also, the glass powder is prepared. Then, the varistor material powder and the glass powder are mixed at a predetermined ratio to prepare a mixed powder (step S12).

  Thereafter, an organic binder, an organic solvent, an organic plasticizer, and the like are added to the obtained mixed powder, and mixed and pulverized for about 20 hours using a ball mill or the like to obtain a slurry. The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S14).

  Next, an electrode paste is applied to a region corresponding to the internal electrode 13 on the obtained green sheet. (Step S16). The electrode paste is a conductive paste in which a metal powder containing Pd as a main component, an organic binder, and an organic solvent is mixed, and is printed on a green sheet by a printing method such as screen printing.

  Next, after the electrode paste applied on the green sheet is dried, the green sheets prepared in the same manner are stacked to form a sheet laminate (step S18). Furthermore, the obtained sheet laminated body is cut | disconnected in a chip unit, and the some laminated body LS1 (refer FIG. 3) divided | segmented is obtained (step S20). In the obtained laminate LS1, a plurality of green sheets GS1 in which the electrode portion EL1 is not formed, a green sheet GS2 in which the electrode portion EL1 is formed, a plurality of green sheets GS1 in which the electrode portion EL1 is not formed, and an electrode The green sheets GS1 to S3 are stacked in the order of the green sheet GS3 on which the portion EL1 is formed and the plurality of green sheets GS1 on which the electrode portion EL1 is not formed. Note that it is not always necessary to stack the green sheet GS1 on which the electrode portion EL1 is not formed between the green sheet GS2 and the green sheet GS3.

Next, the laminate LS1 is subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to remove the binder, and then further fired at 850 to 1100 ° C. for about 0.5 to 5 hours. Processing is performed (step S22) to obtain a varistor element body 3 which is a fired body. By this firing, the green sheets GS1 and S3 between the electrode portions EL1 in the multilayer body LS1 become the varistor layers 11, and the electrode portions EL1 become the internal electrodes 13. The above calcination treatment is preferably carried out in an _{O 2} atmosphere at a concentration 20-100%, more preferably it is carried out at a concentration of 50-100%. Thus, since O O ₂ adsorption occurs at grain boundaries near ₂ by performing firing in an atmosphere, the improvement of the varistor characteristics, reduction of the leakage current can be reduced.

  Next, a conductive paste for the external electrode 5 (first electrode layer 5a) is applied to the outer surface of the obtained fired body. Here, the conductive paste is applied to both ends of the multilayer body LS1 so as to be in contact with each of the pair of electrode portions EL1, and dried. Further, heat treatment is performed at 500 to 850 ° C.

  Next, a Ni plating layer and a Sn plating layer are sequentially stacked on the first electrode layer 5a of the external electrode 5 to form a second electrode layer 5b. Thus, the multilayer chip varistor 1 is obtained. Ni plating can be performed by a barrel plating method using a Ni plating bath (for example, a Watt bath). Sn plating can be performed by a barrel plating method using a Sn plating bath (for example, a neutral Sn plating bath). In addition, you may diffuse an alkali metal (for example, Li, Na, etc.) from the surface of the varistor element | base_body 3 after baking.

  As described above, in the method for manufacturing the multilayer chip varistor 1, a mixed powder obtained by mixing glass powder with varistor material powder is used. Thereby, reduction of the baking temperature at the time of baking is achieved. That is, when the glass powder is not mixed with the varistor material powder, the laminate LS1 needs to be fired at a high temperature of about 1200 to 1400 ° C., but when the glass powder is mixed, The laminated body LS1 can be sufficiently fired at a low temperature of 850 to 1100 ° C.

  In addition, when this manufacturing method is used, in the fired body obtained by firing the laminated body LS1, the amounts of Pr and Ag present in the grain boundaries of particles containing ZnO as a main component, as shown in FIG. More than the amount of Pr and Ag present in the grains. As a result, the inventors newly found that sufficient varistor characteristics can be obtained because Pr uniformly existing in the grain boundary increases the resistance value at the grain boundary and Ag promotes uniform dispersion of Pr. It was.

  In addition, by including Ag in the varistor material, the amount of Ag present at the grain boundary is effectively increased, and the varistor characteristics are improved. Furthermore, the inventors have newly found that by including Ag in the varistor material, the generation of pores (holes) is suppressed and the ceramic structure becomes dense, and as a result, the firing temperature can be reduced. It was.

  Therefore, in the method for manufacturing the multilayer chip varistor 1 described above, a multilayer chip varistor having practically sufficient varistor characteristics can be obtained even at a low firing temperature.

  Hereinafter, examples will be shown in order to further clarify the effects of the present invention.

  The inventors of the present invention have three types: a multilayer chip varistor # 1 and # 2 manufactured using the varistor material, and a multilayer chip varistor # 3 manufactured using a varistor material that does not contain Ag in the varistor material. Varistor samples were prepared. The multilayer chip varistor # 1 and the multilayer chip varistor # 2 differ only in the amount of Ag added to the varistor material. The multilayer chip varistor # 1 is 2.5 wt%, and the multilayer chip varistor # 2 is 0.5 wt%. did. In the laminated chip varistors # 1 to # 3, the amount of glass powder added to the mixed powder is 3 wt% with respect to the mixed powder excluding the glass powder.

  The inventors measured the constituent ratios of various oxides in the ZnO grains and in the region of the two-particle boundary for the above-described multilayer chip varistors # 1 to # 3, and obtained results as shown in FIG. . From this result, regarding the laminated chip varistors # 1 and # 2, the composition ratio at the two-particle boundary (grain boundary in the present invention) is 10 times or more in the oxide equivalent amount of Ag and Pr as compared with the ZnO grains. Is different. That is, in these multilayer chip varistors # 1 and # 2, it can be said that the amount of Pr and Ag present in the grain boundary is 10 times or more larger than the amount of Pr and Ag present in the ZnO grain. . Since the Pr and Ag present in the grain boundary increase in this way, the resistance value at the grain boundary increases, the leakage current flowing between the internal electrodes is suppressed, and a multilayer chip varistor having high varistor characteristics is obtained. It is considered to be obtained.

  On the other hand, for the multilayer chip varistor # 3 in which Ag is not contained in the varistor material, the amount of Pr converted to oxide is different from that in the ZnO grains by 10 times or more in the composition ratio at the two-particle boundary. As for the oxide equivalent amount, the composition ratio hardly changed between the ZnO grains and the two-particle boundaries. That is, when Ag is not included in the varistor material, the amount of Ag present at the grain boundary is almost the same as the amount of Ag present within the ZnO grain, and the effect of increasing the resistance value at the grain boundary is not much obtained. It is thought that there is nothing.

  As described above, it has been confirmed that the use of Ag as the varistor material effectively increases the amount of Ag present at the grain boundaries and contributes to the improvement of the varistor characteristics. The addition amount of Ag is not particularly limited, but is preferably about 0.02 to 2.5 wt% of the varistor material. The inventors observed the cross-section of the varistor sample with different amounts of Ag added by SEM, and found that pores (voids) decreased as the amount of Ag added increased. FIG. 6 is a cross-sectional photograph (magnification 3000 times) of a varistor sample fired at 1050 ° C. Compared with the sample to which Ag is not added shown in FIG. 6A, a sample to which 0.2 wt% of Ag shown in FIG. 6B is added, and Ag shown in FIG. It can be seen that the pores are gradually reduced and the ceramic structure is denser with the sample to which% is added. Since the ceramic structure becomes dense in this manner, the firing temperature is reduced as the amount of Ag added increases.

  In order to obtain high varistor characteristics, the varistor firing temperature is preferably 1100 ° C. or lower, and preferably 850 ° C. or higher from the viewpoint that reliable firing can be performed. By firing the varistor at a low firing temperature in this range, various problems such as crystal overgrowth and damage to the firing furnace when firing at a high temperature can be eliminated, and practically sufficient varistor characteristics can be obtained. A varistor having the same can be obtained.

  The addition amount of the glass powder in the mixed powder is not limited to 3 wt% described above, and may be 0.05 to 7 wt% with respect to the mixed powder excluding the glass powder. This is because if the addition amount of the glass is lower than 0.05 wt%, the firing temperature by the glass and Ag is insufficiently lowered, and if the addition amount of the glass exceeds 7 wt%, Pr may be discharged from the grain boundary.

It is a figure explaining the section composition of the lamination type chip varistor concerning the embodiment of the present invention. It is a flowchart for demonstrating the manufacturing process of the multilayer chip | tip varistor of FIG. It is a figure for demonstrating the manufacturing process of the multilayer chip | tip varistor of FIG. FIG. 2 is a diagram showing constituent elements around ZnO particles in the multilayer chip varistor of FIG. 1. It is the figure which showed the measurement result of the component ratio of the various oxides concerning an Example. It is the SEM photograph which showed the cross section of the varistor sample.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Multilayer chip varistor, 3 ... Varistor element | base_body, 5 ... External electrode, 13 ... Internal electrode, LS1 ... Laminated body.

Claims (4)

Preparing a varistor material containing Zn, Pr, Co, Ag;
Preparing a glass containing Zn, B, Si;
Forming a sheet containing mixed powder obtained by mixing the varistor material powder and the glass powder;
Applying an electrode paste containing Pd or Ag-Pd on the sheet;
A step of laminating a plurality of the sheets coated with the electrode paste to form a laminate;
And firing the laminate to form a fired body,
A method for producing a multilayer chip varistor, wherein the amount of Pr and Ag present in the grain boundary of the fired body is greater than the amount of Pr and Ag present in the grain of the fired body.   The manufacturing method of the multilayer chip varistor according to claim 1, wherein a firing temperature for firing the multilayer body is 850 to 1100 ° C.   The multilayer chip varistor according to claim 1 or 2, wherein an addition amount of the glass powder in the mixed powder is 0.05 to 7 wt% with respect to the mixed powder excluding the glass powder. Manufacturing method. The amount of Pr and Ag present in the grain boundary of the fired body is 10 times or more larger than the amount of Pr and Ag present in the grain of the fired body, according to any one of claims 1 to 3. Manufacturing method of multilayer chip varistor.

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