JP3981125B2 - Multilayer chip varistor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer chip varistor and a method for manufacturing the same.

As one type of conventional multilayer chip varistors, for example, as described in Patent Document 1, a laminate having a varistor layer and an internal electrode arranged so as to sandwich the varistor layer, and a surface of the laminate What is known is provided with an external electrode formed and connected to an internal electrode. Patent Document 1 discloses the following varistor manufacturing method. First, a green laminate having a green sheet to be a varistor layer and an electrode layer to be an internal electrode and an electrode layer disposed so as to sandwich the green sheet is formed. Subsequently, the green laminate is fired to obtain a fired body. Then, this fired body is used as the above-described laminate, and external electrodes are formed on the surface.
JP 2002-246207 A

  An object of the present invention is to provide a multilayer chip varistor with little variation in capacitance and a method for manufacturing the same.

  As a result of intensive studies, the inventors have inferred that the variation in capacitance is due to the following reasons.

  Before forming the external electrode, an alkali metal may be diffused into the fired body for the purpose of adjusting the capacitance. Conventionally, when diffusing an alkali metal, a sealed rotating pot containing a plurality of fired bodies and an alkali metal compound is rotated to cause the fired bodies to collide and contact each other. As a result, the alkali metal compound is rubbed and adhered to the surface of the fired body, but the alkali metal compound is less likely to adhere to the corner portion of the fired body than the flat portion. Therefore, in the fired body, there is a possibility that variation occurs in the degree of adhesion of the alkali metal compound at the corners. In such a fired body, variations in capacitance occur. When variation occurs in the capacitance of the fired body, the multilayer chip varistor using the fired body as a laminated body also varies in capacitance.

  The present inventors have further studied based on these findings, found that the above-described problems can be solved by the following invention, and have completed the present invention.

That is, the method for manufacturing a multilayer chip varistor according to the present invention includes a multilayer body having a varistor layer and an internal electrode disposed so as to sandwich the varistor layer, and is formed on the surface of the multilayer body and formed on the internal electrode. A method for manufacturing a multilayer chip varistor comprising external electrodes to be connected, comprising a green sheet as a varistor layer and an electrode layer as an internal electrode, wherein the electrode layer is disposed so as to sandwich the green sheet A first step of forming a laminate, a second step of chamfering the corner portion of the green laminate so that the corner portion has a predetermined radius of curvature, and firing the chamfered green laminate body Then, the third step of obtaining the laminate, the fourth step of diffusing the alkali metal from the surface of the laminate into the laminate, and after diffusing the alkali metal, A fifth step of forming an external electrode on the surface. In the second step, the curvature radius R of the corner portion of the green laminated body and the short side surface perpendicular to the lamination direction in the green laminated body are included. The relationship with the side length W is
0.188 <(R / W) <0.375
It is characterized by chamfering so as to satisfy.

  In the method for manufacturing a multilayer chip varistor according to the present invention, the green laminate is subjected to chamfering so that the R / W is larger than 0.188, and then fired. Thereby, the laminated body in which the chamfering process was performed can be obtained. The resulting laminate is placed in a closed rotating pot in the fourth step, for example, to deposit an alkali metal compound. Since the laminate subjected to the chamfering process rotates smoothly in the sealed rotating pot, the alkali metal compound uniformly adheres to the surface of the laminate. As a result, it is possible to obtain a stacked body with little variation in capacitance. By forming external electrodes on such a laminate, a multilayer chip varistor with little variation in capacitance can be obtained.

  By the way, the manufactured multilayer chip varistor is accommodated in the accommodating recess of the carrier tape. If the corners of the laminated body are excessively rounded, the laminated chip varistor may be tilted in the accommodating recess due to vibration or the like. In this case, when the multilayer chip varistor in the housing recess is taken out at a high speed by suction or the like and mounted on a circuit board or the like, the suction is not successful and there is a possibility that the mounting efficiency is lowered. In the manufacturing method of the multilayer chip varistor according to the present invention, since the R / W of the green multilayer body is set to a value smaller than 0.375, the roundness of the corner portion of the multilayer body becomes appropriate. As a result, a laminate with high positional stability can be obtained. Therefore, it is possible to manufacture a multilayer chip varistor that hardly tilts in the housing recess.

  In the method for manufacturing a multilayer chip varistor according to the present invention, it is preferable that the second step be chamfered at the corners of the multilayer body by barrel polishing. If barrel polishing is used, it is possible to simultaneously chamfer a plurality of laminated bodies. Therefore, it becomes possible to perform chamfering efficiently.

A multilayer chip varistor according to the present invention includes a multilayer body having a varistor layer and an internal electrode disposed so as to sandwich the varistor layer, and an external electrode formed on the surface of the multilayer body and connected to the internal electrode. The alkali metal is diffused on the surface and inside of the laminated body, and the curvature radius R of the corner portion of the laminated body and the length W of the short side of the side surface perpendicular to the laminating direction in the laminated body Relationship
0.188 <(R / W) <0.375
It is characterized by satisfying.

  The multilayer chip varistor of the present invention includes a multilayer body having a varistor layer and internal electrodes. Such a laminate is produced, for example, by firing a green laminate having a green sheet as a varistor layer and an electrode layer as an internal electrode. In this case, since the green laminate is entirely contracted by firing, the laminate was chamfered so that the ratio between the radius of curvature of the corner portion and the length of the short side of the side satisfies the above formula. If a green laminated body is used, a desired laminated body can be obtained. When the R / W is larger than 0.188, the laminate rotates smoothly in the sealed rotating pot when the alkali metal is diffused. Therefore, since an alkali metal compound adheres uniformly, a laminate with little variation in capacitance can be obtained. As a result, a multilayer chip varistor with little variation in capacitance can be obtained. In addition, when the R / W is smaller than 0.375, the laminated body has high positional stability. As a result, it is possible to obtain a multilayer chip varistor that hardly tilts in the receiving recess of the carrier tape.

  According to the present invention, it is possible to provide a multilayer chip varistor with little variation in capacitance and a method for manufacturing the same.

  Hereinafter, preferred embodiments of a multilayer chip varistor according to the present invention will be described in detail with reference to the accompanying drawings. In the description, the same reference numerals are used for the same elements or elements having the same function, and redundant description is omitted.

  First, the configuration of the multilayer chip varistor 1 according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram for explaining a cross-sectional configuration of the multilayer chip varistor according to the present embodiment. FIG. 2 is a perspective view of a multilayer body included in the multilayer chip varistor according to the present embodiment.

  As shown in FIG. 1, the multilayer chip varistor 1 includes a multilayer body L3 and a pair of external electrodes 5 that are respectively formed on opposite end surfaces of the multilayer body L3.

The multilayer body L3 includes a varistor layer 11 that exhibits varistor characteristics, and a pair of internal electrodes 13 that are disposed so as to sandwich the varistor layer 11 therebetween. More specifically, the multilayer body L3 is configured by laminating a varistor part 7 including the varistor layer 11 and the internal electrode 13 and a pair of outer layer parts 9 arranged so as to sandwich the varistor part 7. ing. As shown in FIG. 2, the corner portion 4 of the stacked body L3 has an arc shape and has a predetermined radius of curvature. The radius of curvature _RL of the corner portion 4 of the multilayer body L3 and the length W _L of the short side of the side surface 3a perpendicular to the stacking direction of the multilayer body L3 satisfy the following expression (1).
0.188 <(R _L / W _L ) <0.375 (1)

More specifically, the multilayer chip varistor 1 according to the present embodiment is a so-called 1608 type multilayer chip varistor, and the length W _L of the short side of the side surface 3a in the multilayer body L3 is set to 0.8 mm. If this is the case, the radius of curvature R _L (unit: mm) of the corner portion 4 is expressed by the following formula (2).
150 <R _L <300 (2)

  As shown in FIG. 1, in the varistor part 7, the varistor layers 11 and the internal electrodes 13 are alternately stacked. A region 11 a overlapping the pair of internal electrodes 13 in the varistor layer 11 functions as a region that develops varistor characteristics.

  The varistor layer 11 contains ZnO (zinc oxide) as a main component, and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, alkali metal elements (K) as subcomponents. , Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and the like, and element bodies containing these oxides. In the present embodiment, the varistor layer 11 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, the region 11a of the varistor layer 11 that overlaps the pair of internal electrodes 13 has a region that is composed of ZnO as a main component and that includes Pr.

  Pr is a material for expressing varistor characteristics. The reason for using Pr is that voltage non-linearity is excellent and characteristic variation during mass production is small. The content of ZnO in the varistor layer 11 is not particularly limited, but is usually 99.8 to 69.0% by mass when the total material constituting the varistor layer 11 is 100% by mass. The thickness of the varistor layer 11 is, for example, about 5 to 60 μm.

The pair of internal electrodes 13 are provided substantially in parallel so that the respective one end portions thereof are alternately exposed on the opposing end surfaces of the multilayer body L3. Each internal electrode 13 is electrically connected to the external electrode 5 at each one end. The internal electrode 13 includes a conductive material. The conductive material contained in the internal electrode 13 is not particularly limited, but is preferably made of Pd or an Ag—Pd alloy. The thickness of the internal electrode 13 is, for example, about 0.5 to 5 μm. When the multilayer chip varistor 1 has a low capacitance, the area of the overlapping portion 13a of the internal electrode 13 is usually 0.001 to 0.5 mm ² , preferably 0.002 when viewed from the stacking direction of the stacked body L3. About 0.1 mm ² .

  Similar to the varistor layer 11, the outer layer portion 9 contains ZnO as a main component and also includes rare earth metal elements, Co, group IIIb elements (B, Al, Ga, In), Si, Cr, Mo, and alkali metals as subcomponents. It consists of elemental bodies including simple metals such as elements (K, Rb, Cs) and alkaline earth metal elements (Mg, Ca, Sr, Ba) and oxides thereof. In the present embodiment, the outer layer portion 9 includes Pr, Co, Cr, Ca, Si, K, Al, and the like as subcomponents. As a result, the outer layer portion 9 has a region composed of an element body containing Pr as a main component and containing Pr. The thickness of the outer layer portion 9 is, for example, about 0.30 to 0.38 mm.

  The external electrode 5 is formed on the surface of the multilayer body L3 and is connected to the internal electrode 13. More specifically, the external electrode 5 is provided so as to cover both end faces of the multilayer body L3. The external electrode 5 is preferably made of a metal material that can be electrically connected to a metal such as Pd constituting the internal electrode 13 in an excellent manner. For example, Ag is suitable as a material for the external electrode because it has good electrical connectivity with the internal electrode 13 made of Pd and has good adhesion to the end face of the laminate L3. Such an external electrode 5 is normally about 10 to 50 μm thick.

  On the surface of the external electrode 5, a Ni plating layer (not shown) having a thickness of about 0.5 to 2 μm and a Sn plating layer (not shown) having a thickness of about 2 to 6 μm so as to cover the external electrode 5. Are formed in order. These plating layers are formed mainly for the purpose of improving solder heat resistance and solder wettability when the multilayer chip varistor 1 is mounted on a substrate or the like by solder reflow.

  The plating layer formed on the surface of the external electrode 5 is not necessarily limited to the combination of materials described above as long as the purpose of improving solder heat resistance and solder wettability is achieved. Other materials that can form the plating layer include, for example, Sn—Pb alloy and the like, and may be used in combination with the above-described Ni or Sn. Further, the plating layer is not necessarily limited to the two-layer structure, and may have a structure of one layer or three or more layers.

  Then, with reference to FIGS. 1-4, the manufacturing method of the multilayer chip varistor 1 which has the structure mentioned above is demonstrated. FIG. 3 is a flowchart for explaining the manufacturing method of the multilayer chip varistor according to the present embodiment. FIG. 4 is a view for explaining the method of manufacturing the multilayer chip varistor according to this embodiment.

  First, the green laminated body G3 is formed (step S100). In forming the green laminated body G3, ZnO which is a main component of the varistor layer 11 and the outer layer portion 9, and a trace amount additive such as Pr, Co, Cr, Ca, Si, K and Al metals or oxides are added in a predetermined manner. After weighing each so as to be a ratio, each component is mixed to adjust the varistor material (step S101). Then, an organic binder, an organic solvent, an organic plasticizer, etc. are added to this varistor material, and it mixes and grinds for about 20 hours using a ball mill etc., and obtains a slurry.

  The slurry is applied onto a film made of, for example, polyethylene terephthalate by a known method such as a doctor blade method, and then dried to form a film having a thickness of about 30 μm. The film thus obtained is peeled from the film to obtain a green sheet (step S102).

  Next, on the green sheet, paste-like Pd, which is a material for the internal electrode 13, is applied in a predetermined pattern by a printing method such as screen printing, and then the conductive paste is dried to form a predetermined pattern. An electrode layer is prepared (step S103).

  Next, the green sheet on which the electrode layer is formed and the green sheet on which the electrode layer is not formed are stacked in a predetermined order to form a sheet laminate (step S104). The sheet laminate thus obtained is cut into a desired size to obtain a green laminate G3 (step S105). As shown in FIG. 4, the obtained green laminate 3 includes green sheets S1 to S3 and an electrode layer EL, and the electrode layer EL is disposed so as to sandwich the green sheets S1 and S3. . More specifically, in the green laminate G3, a plurality of green sheets S1 on which no electrode layer EL is formed, a green sheet S2 on which an electrode layer EL is formed, and a plurality of green sheets on which no electrode layer EL is formed. These sheets S1 to S3 are laminated in the order of the sheet S1, the green sheet S3 on which the electrode layer EL is formed, and the plurality of green sheets S1 on which the electrode layer EL is not formed. Note that the green sheet S1 on which the electrode layer EL is not necessarily formed is not necessarily laminated between the green sheet S2 and the green sheet S3.

Subsequently, the green laminate G3 is chamfered using barrel polishing (step S106). By using barrel polishing, it becomes possible to efficiently chamfer a plurality of laminated bodies simultaneously. Barrel polishing is performed by putting water and a plurality of green laminates G3 in a sealed rotating pot made of a material such as polyethylene and rotating the sealed rotating pot. By rotating about 15 minutes to 1 hour sealed rotary pot, the relationship between the length W _G of the short side of the side surface 3a of the curvature of the corner portion 4 radius R _G and the green laminate G3 is, the following equation (2) A green laminate G3 is obtained that fills.
0.188 <(R _G / W _G ) <0.375 (2)

Next, the green laminate G3 subjected to the chamfering process is subjected to heat treatment at 180 to 400 ° C. for about 0.5 to 24 hours to perform binder removal. After removing the binder, the laminate L3 is obtained by further firing at 1000 to 1400 ° C. for about 0.5 to 8 hours (step S107). Laminate L3 obtained is because green laminate G3 is obtained by overall contraction, _R L / _{W L} of the laminate L3 is the same value as _R G / _{W G} of the green laminate G3. By firing, the green sheets S1 and S3 between the electrode layers EL in the green laminate G3 become the varistor layers 11 of the laminate L3. The electrode layer EL becomes the internal electrode 13. The laminated body L3 may be smoothed on the surface of the element by, for example, placing it in a polishing container together with an abrasive or the like before performing the next step.

  Next, an alkali metal (for example, Li, Na, etc.) is diffused from the surface of the multilayer body L3 into the multilayer body L3 (step S108). Here, first, an alkali metal compound is attached to the surface of the laminate L3. A sealed rotating pot can be used for adhesion of the alkali metal compound. Although it does not specifically limit as an alkali metal compound, It is a compound which an alkali metal can diffuse from the surface of the laminated body L3 to the vicinity of the internal electrode 13 by heat processing, and an alkali metal oxide, hydroxide, chloride Nitrate, borate, carbonate, oxalate and the like are used.

  Subsequently, the laminate L3 to which the alkali metal compound is attached is heat-treated in an electric furnace at a predetermined temperature and time. As a result, the alkali metal diffuses from the surface of the multilayer body L3 to the vicinity of the internal electrode 13 from the alkali metal compound. A preferable heat treatment temperature is 700 to 1000 ° C., and the heat treatment atmosphere is air. The heat treatment time (holding time) is preferably 10 minutes to 4 hours.

  Next, an external electrode paste mainly containing Ag is applied to both ends of the laminate L3 so as to be in contact with each of the pair of internal electrodes 13, and then the paste is heated (baked) at about 550 to 850 ° C. ) Process. As a result, a pair of external electrodes 5 made of Ag is formed on the surface of the multilayer body L3 (step S109). A Ni plating layer and a Sn plating layer are sequentially laminated on the outer surface of the external electrode 5 by electrolytic plating or the like. Thus, the multilayer chip varistor 1 is obtained.

As described above, according to the manufacturing method of the present embodiment, after chamfering the corner portion 4 of the green laminate G3, the green laminate G3 is fired to obtain the laminate L3. Since the laminated body L3 having R _L / W _L larger than 0.188 rotates smoothly in the sealed rotating pot, the alkali metal compound adheres uniformly to the surface. Therefore, it is possible to obtain a stacked body L3 with little variation in capacitance. By using such a stacked body L3, it is possible to manufacture the stacked chip varistor 1 with less variation in capacitance.

The multilayer chip varistor 1 is housed in a housing recess of the carrier tape and shipped. If the corners of the laminated body are excessively rounded, the laminated chip varistor may be tilted in the housing recess due to vibrations generated at the time of shipment. In the present invention, since R _L / W _L of the laminate L3 is set to a value smaller than 0.375, a laminate L3 having a moderate roundness in the corner portion 4 and having high positional stability can be obtained. . By using such a laminated body L3, it is possible to manufacture the laminated chip varistor 1 that hardly tilts in the housing recess.

  The preferred embodiments of the present invention have been described above, but the present invention is not necessarily limited to these embodiments. For example, the above-described multilayer chip varistor 1 has a structure in which a pair of internal electrodes 13 sandwich a varistor layer 11, but the varistor of the present invention has a multilayer chip varistor in which a plurality of such structures are stacked. It may be. According to such a laminated varistor, it is possible to further improve electrostatic resistance, further drive at a low voltage, and the like.

  Here, with respect to the multilayer chip varistor 1 of the present embodiment, the following experiment was conducted in order to confirm the effect that the variation in capacitance is reduced.

That is, several types of multilayer chip varistors 1 having different ratios of the radius of curvature R _L of the corner portion 4 of the multilayer body L3 and the length W _L of the short side of the side surface 3a of the multilayer body L3 are prepared, and the capacitance varies. I investigated. Examples 1 to 5 are 1608 type multilayer chip varistors having the same configuration as the multilayer chip varistor 1 of the present embodiment, and were manufactured according to the manufacturing process shown in FIG. Show things. Regarding the alkali metal diffusion treatment, the laminate was mixed with Li ₂ CO ₃ powder as an alkali metal compound in a sealed rotating pot. For the radius of curvature R _L of the corner portion of the laminate L3 and the length W _L of the short side of the side surface 3a of the laminate L3, the values of R _L / W _L are 0.219, 0.250, 0.281, respectively. , 0.313, and 0.344.

  In contrast, in Comparative Examples 1 to 3, the R / W values were set to 0.125, 0.156, and 0.188, respectively. Except for the value of R / W, multilayer chip varistors of Comparative Examples 1 to 3 were obtained in the same manner as in Examples 1 to 5.

Using the multilayer chip varistor thus manufactured, the variation in the capacitance C was measured. In addition, the dispersion _| variation in the electrostatic capacitance C was _{calculated |} required by (sigma) / _Xave * 100 (%). Here, σ is a standard deviation, and X _ave is an average value. The measurement results are shown in FIG.

  In the multilayer chip varistors of Comparative Examples 1 to 3, the variation in the capacitance C was 6.4 to 35.0%. On the other hand, in the multilayer chip varistors of Examples 1 to 5, the variation in the capacitance C is as small as less than 5%.

  From the above, the effectiveness of the present invention that the variation in capacitance is reduced was confirmed.

  Furthermore, in order to confirm the effect that the stacked chip varistor 1 of the present embodiment is less likely to be tilted in the recessed portion of the carrier tape, the following experiment was conducted.

That is, several types of multilayer chip varistors 1 having different values of (the radius of curvature R _L of the corner portion 4 of the multilayer body L3) / (the length W _L of the short side of the side surface 3a of the multilayer body L3) were prepared. Examples 6 to 10 are 1608 type multilayer chip varistors having the same configuration as the multilayer chip varistor 1 of the present embodiment, and each is manufactured under the same conditions as in Examples 1 to 5.

  On the other hand, in Comparative Example 4, the value of (the radius of curvature of the corner portion of the laminate) / (the length of the short side of the side surface of the laminate) is set to 0.375. A laminated chip varistor of Comparative Example 4 was obtained in the same manner as in Examples 6 to 10 except for the value of (curvature radius of the corner portion of the laminated body) / (length of the short side of the laminated body).

  10000 samples of the multilayer chip varistor thus manufactured were prepared and stored in the receiving recesses of the carrier tape. After the accommodation, the carrier tape was subjected to vibration equivalent to that produced at the time of shipment, and the ratio of the laminated chip varistor tilted in the accommodation recess was examined. The result is shown in FIG.

  In Comparative Example 4, about 5% of the multilayer chip varistor was inclined in the housing recess. In Examples 6-10, the laminated chip varistor which inclines in the accommodation recessed part was not seen.

  From the above, the effectiveness of the present invention was confirmed to be less inclined in the receiving recess of the carrier tape.

It is a figure explaining the section composition of the multilayer chip varistor concerning this embodiment. It is a perspective view of the laminated body contained in the multilayer chip varistor concerning this embodiment. It is a flowchart for demonstrating the manufacturing method of the multilayer chip varistor which concerns on this embodiment. It is a figure for demonstrating the manufacturing method of the multilayer chip varistor concerning this embodiment. It is a graph which shows the result of the experiment which investigates the dispersion | variation in the electrostatic capacitance of a multilayer chip varistor. It is a graph which shows the result of the experiment which investigates the ratio of the multilayer chip | tip varistor rotating within the accommodation recessed part of a tape.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Laminated chip varistor, 3a ... Side surface, 4 ... Corner part, 5 ... External electrode, 11 ... Varistor layer, 13 ... Internal electrode, EL ... Electrode layer, G3 ... Green laminated body, L3 ... Laminated body, S1, S2 , S3 ... Green sheet.

Claims (3)

Production of a multilayer chip varistor comprising a laminate having a varistor layer and an internal electrode arranged so as to sandwich the varistor layer, and an external electrode formed on the surface of the laminate and connected to the internal electrode A method,
A first step of forming a green laminate having a green sheet to be the varistor layer and an electrode layer to be the internal electrode, and the electrode layer disposed so as to sandwich the green sheet;
A second step of chamfering the corner portion of the green laminate so that the corner portion has a predetermined radius of curvature;
Firing the green laminate that has been chamfered to obtain the laminate,
A fourth step of diffusing an alkali metal from the surface of the laminate into the laminate;
After diffusing the alkali metal, and forming the external electrode on the surface of the laminate, and
In the second step, the relationship between the radius of curvature R of the corner portion of the green laminate and the length W of the short side of the side surface perpendicular to the lamination direction in the green laminate,
0.188 <(R / W) <0.375
A method of manufacturing a multilayer chip varistor, wherein chamfering is performed to satisfy the above requirements.   2. The method of manufacturing a multilayer chip varistor according to claim 1, wherein in the second step, chamfering is performed on a corner portion of the green multilayer body by barrel polishing. A laminate having a varistor layer and an internal electrode arranged so as to sandwich the varistor layer;
An external electrode formed on the surface of the laminate and connected to the internal electrode;
With
Alkali metal is diffused on the surface and inside of the laminate,
The relationship between the curvature radius R of the corner portion of the laminate and the length W of the short side of the side surface perpendicular to the lamination direction in the laminate,
0.188 <(R / W) <0.375
A multilayer chip varistor characterized by satisfying

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