JP2869897B2 - Varistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a varistor functioning as a voltage non-linear resistor, and in particular, can reduce the manufacturing cost, can reduce the capacitance, and can expand the application. The present invention relates to an inter-electrode distance capable of further improving surge withstand without increasing an electrode area.

[Related Art] Generally, a varistor is a resistor element whose resistance value changes nonlinearly in accordance with an applied voltage, and is used as a surge absorbing element for preventing an abnormal voltage from being applied. As an example of such a varistor, there is a laminated varistor as shown in FIG. 6 (see Japanese Patent Publication No. 58-23921). The multilayer varistor 10 is composed of a ceramic layer 11
And the internal electrodes 12 are alternately laminated and sintered integrally, and external electrodes 14 are formed on the left and right end faces 13a and 13b of the sintered body 13. Further, one end face 12a of the internal electrode 12 that is alternately exposed to the left and right end faces 13a, 13b of the sintered body 13 is connected to the external electrode. In this type of multilayer varistor 10, in order to obtain a surge withstand capability of about 100A, about 10 to 20 internal electrodes 12 are stacked.

However, in the multilayer varistor 10, the internal electrode
Because expensive noble metals such as Ag and Pd are used for 12,
There is a problem that as the number of layers increases, the manufacturing cost increases. Further, when the number of stacked internal electrodes 12 is increased, the capacitance is increased. Therefore, the internal electrodes 12 cannot be used for a high-frequency signal line, and there is a problem that the application is limited.

Accordingly, the applicant of the present application has proposed a varistor having the structure shown in FIGS. 4 and 5 as a varistor capable of solving problems such as an increase in manufacturing cost (see Japanese Patent Application No. 1-313905). This chip varistor 20 has a single-layered internal electrode 22 embedded in a ceramic sintered body 21, and an internal electrode 22 on the outer surface of the sintered body 21.
A surface electrode 23 is formed so as to oppose the ceramic layer 22 with the ceramic layer 21a interposed therebetween. 24 is a glass layer covering the surface electrode 23, 25 is an external electrode, and 21b is a ceramic layer as a dummy. According to the chip varistor 20, the ceramic layer 21a functioning as a voltage non-linear body is
Since it is arranged on the surface portion of, oxygen can be sufficiently supplied at the time of firing, and heat is easily released even if heat is generated by application of current. As a result, only two layers of the internal electrode 22 and the surface electrode 23 can provide a surge withstand capability equivalent to that of the conventional multilayer varistor, thereby reducing the amount of expensive precious metal used and reducing the manufacturing cost. , Can be used for high-frequency signal lines by reducing the capacitance.
Applications can be expanded.

[Problems to be solved by the invention]

By the way, in the chip varistor 20, an improvement in surge withstand is required to obtain more excellent characteristics. It is possible to improve the surge resistance by increasing the area of the electrode, but there is a limit because increasing the electrode area increases the size of the component element.

The present invention has been made in order to respond to the above request,
It is an object of the present invention to provide a varistor capable of reducing the manufacturing cost, reducing the capacitance, and improving the surge resistance without increasing the electrode area.

[Means for solving the problem]

Thus, the present inventors have observed a situation in which the varistor element is destroyed when a surge current having a value greater than the ability value is applied to the varistor element, and the destroyed portion is concentrated on the outer peripheral edge of the internal electrode. I found that. That is,
As shown in FIG. 5, the surge current is concentrated only on the outer peripheral portion A of the internal electrode 22, and it has been conceived that the surge withstand capability can be improved if the surge current can be dispersed, and the present invention has been made.

Therefore, the present invention is a varistor in which an internal electrode is buried inside a ceramic sintered body, and a surface electrode facing the internal electrode and a ceramic layer is formed on the outer surface of the sintered body, It is characterized in that the inter-electrode distance between the outer peripheral edge of the internal electrode and the surface electrode is at least 1.05 times larger than the inter-electrode distance at the center.

Here, the ratio of the interelectrode distance between the internal electrode and the surface electrode (outer peripheral edge / central portion) is set to 1.05 times or more, because the surge resistance cannot be improved below this ratio. If the above ratio exceeds 1.5 times, the surge resistance can be improved, but cracks are likely to occur during delamination or firing. Therefore, the ratio is preferably in the range of 1.05 to 1.5 times.

[Action]

According to the varistor according to the present invention, since the interelectrode distance between the outer peripheral edge of the internal electrode and the surface electrode is wider than the interelectrode distance in the central portion, when a surge current of an actual value or more is applied, the electric flux lines are It is uniformly dispersed over substantially the entire surface of the internal electrode without being concentrated on the outer peripheral edge of the internal electrode. As a result, the surge withstand can be improved without increasing the electrode area.

Moreover, in the varistor of the present invention, the ceramic layer functioning as a voltage non-linear body sandwiched between the internal electrode and the surface electrode is located on the surface portion of the sintered body. In addition, even if heat is generated by applying a current, heat is easily released.
As a result, the desired surge withstand capability can be obtained only with the two layers of the internal electrode and the surface electrode. Therefore, it is possible to reduce the manufacturing cost by reducing the amount of expensive noble metal used, and to reduce the capacitance to reduce the high frequency. It can also be used for signal lines, expanding its applications.

〔Example〕

 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

1 and 3 are views for explaining a varistor according to one embodiment of the present invention.

In the figure, reference numeral 1 denotes a chip-type varistor of this embodiment. This varistor 1 is a rectangular parallelepiped sintered body obtained by integrally sintering a ceramics layer 5a functioning as a voltage non-linear body and a ceramics layer 5b serving as a dummy. 2, a single internal electrode 3 made of Pt is buried inside, and a surface electrode 4 facing the internal electrode 3 is formed on the outer surface of the sintered body 2 with the ceramic layer 5a interposed therebetween. . One end face 3a of the internal electrode 3 is exposed on one side face 2a of the sintered body 2, and the remaining part is sealed in the sintered body 2. Further, one end face 4a of the surface electrode 4 is located on the upper edge of the other side face 2b of the sintered body 2, and the other peripheral edge is located inside the peripheral edge of the sintered body 2. Furthermore, both sides 2 of the above-mentioned sintered body 2
External electrodes 6 made of an Ag / Pd alloy are formed on a and 2b. One end surface 3a of the internal electrode 3 and one end surface 4a of the surface electrode 4 are connected to each of the external electrodes 6. Further, a glass layer 7 for preventing deterioration of the electrode due to high humidity is formed on the upper surface of the surface electrode 4 of the sintered body 2.

The interelectrode distance t between the outer peripheral edge 8a of the internal electrode 3 and the surface electrode 4 is determined by the distance between the central portion 8b of the internal electrode 3 and
And the ratio of the distance t / t 'between the two electrodes is set to be 1.05 times or more. Thus, the outer peripheral edge 8a of the internal electrode 3 has a structure curved inward.

Next, a method for manufacturing the chip type varistor 1 of the present embodiment will be described.

First, ZnO (95.0 mol%), CoO (1.0 mol%), MnO (1.0 m
ol%), Sb ₂ O ₃ (2.0 mol%), and Cr ₂ O ₃ (1.0 mol%), respectively, and B ₂ O ₃ , SiO ₂ , PbO, Z
A raw material is prepared by adding 10 wt% of glass powder composed of nO.
An organic binder and an alcohol are added to and mixed with the ceramic raw material to obtain a slurry. A green sheet having a predetermined thickness is formed from the slurry by a doctor blade method,
This green sheet is cut into a rectangular shape having a predetermined size to form a large number of ceramic sheets. This allows
A ceramic layer 5a functioning as a voltage non-linear body and a ceramic layer 5b serving as a dummy are formed.

Next, as shown in FIG. 3, the uppermost ceramics layer 5a
The surface electrode 4 is formed by printing a paste obtained by mixing Pt with a vehicle on the upper surface of the substrate. In this case, one end face 4a of the surface electrode 4 is formed so as to be located at the edge of the ceramic layer 5a, and the other end face is located inside the ceramic layer 5a. Subsequently, the paste is printed on the upper surface of the ceramic layer 5b located below the ceramic layer 5a to form the internal electrodes 3. Also in this case, the inner electrode 3 is formed such that one end face 3a is located at the edge of the ceramic layer 5b and the remaining end face is located inside the ceramic layer 5b.

Then, on the outer peripheral edge 8a of the upper surface of the internal electrode 3 of the ceramic layer 5b, a ceramic paste 10 obtained by mixing a vehicle with the same material as the ceramic sheet prepared in the above step is printed. As a result, the upper surface of the ceramic layer 5b is exposed only at the central portion 8b of the internal electrode 3.

Here, the thickness of the ceramic paste 10 is such that the distance t between the outer peripheral edge 8a of the internal electrode 3 and the surface electrode 4 is equal to the distance between the center 8b of the internal electrode 3 and the surface electrode 4. It is set appropriately so as to be at least 1.05 times t '. The ceramic paste 10 may be formed by stacking ceramic sheets each having an opening formed in the center in advance.

Next, the surface electrode 4 of the ceramics layer 5a and the internal electrode 3 face each other with the ceramics layer 5a interposed therebetween.
4 so that one end faces 3a and 4a are alternately located on the edges of the ceramic layers 5a and 5b, and two dummy ceramic layers 5
The layers b and 5b are stacked, and the layers are pressed under pressure by a press to form a laminate. As a result, the outer peripheral edge 8a of the internal electrode 3 is curved inward, and the interelectrode distance t between the outer peripheral edge 8a and the surface electrode 4 is increased.
Is larger than the interelectrode distance t 'between the central portion 8b of the internal electrode 3 and the surface electrode 4.

Next, the laminate is heated and fired at 1200 ° C. in the air to obtain a sintered body 2. Then, a glass paste is applied to the surface of the surface electrode 4 of the sintered body 2 and baked at 600 ° C. to form a glass layer 7.

Finally, a paste composed mainly of Ag and added with Pd is applied to the left and right side surfaces 2a, 2b of the sintered body 2, and then baked to form the external electrodes 6. Thus, the chip-type varistor 1 of this embodiment is manufactured. As described above, according to the chip-type varistor 1 of this embodiment,
Distance t between the outer peripheral edge 8a of the internal electrode 3 and the surface electrode 4
Is larger than the distance t 'between the electrodes at the center of the two electrodes 3 and 4, so that the surge current is uniformly dispersed. As a result, the surge withstand capability can be improved without increasing the electrode area.

Further, in this embodiment, the ceramics layer 5a sandwiched between the internal electrode 3 and the surface electrode 4 is located on the surface of the sintered body 2, so that sufficient oxygen can be supplied at the time of the above-mentioned firing, and furthermore, the current is reduced. It becomes easy to dissipate heat when flowing and generate heat, and as a result, a desired surge resistance can be obtained only by the two layers of the internal electrode 3 and the surface electrode 4. Therefore, the amount of expensive noble metal used is reduced and the manufacturing cost is reduced. It can be used for high-frequency signal lines by reducing the capacitance.
Applications can be expanded.

Next, an experiment performed to confirm the effect of improving the surge withstand capability of the chip type varistor according to the present embodiment will be described.

In this experiment, a number of example samples were prepared by the manufacturing method of the above example, and the ratio of the distance between electrodes (t / t 'shown in FIG. 1) of each example sample was changed to 1.05, 1.2, and 1.5 times. Then, a surge current of 8/20 μs having various peak values was applied thereto, and the surge withstand capability was measured. Further, for comparison, the same measurement was performed on comparative samples in which the ratio was 1 (the distance between the electrodes was the same) and 1.02 times.

The table shows the results. As is clear from the table, when the ratio of the distance between the electrodes is 1, that is, when the distance is the same (column 1), breakage occurs at a peak value of 120 A. Was concentrated on When the ratio of the distance between the electrodes is 1.02 times (column 2), the surge withstand
Although slightly improved to 130A, a satisfactory value was not obtained. On the other hand, when the ratio of the distance between the electrodes exceeds 1.05 times (columns 3 to 5), breakdown occurs at 200 to 210 A in all cases, and the surge withstand capability can be greatly improved. Also,
The locations of the destruction are dispersed without being concentrated, and it can be seen that the surge withstand capability can be improved by setting the ratio of the distance between the electrodes to 1.05 times or more. In addition, when the above ratio is 1.5 times or more, the surge resistance can be improved, but delamination and cracks during firing tend to occur. For this reason, the range of 1.05 to 1.5 times is desirable.

In the above embodiment, the structure in which one layer of internal electrode is embedded in the sintered body has been described as an example. However, the present invention embeds two layers of internal electrodes in the sintered body, and The present invention can also be applied to a structure in which a surface electrode is formed on one surface facing the electrode and on the ground surface. In this case, the distance between the electrodes at the outer peripheral edge of each internal electrode is wider than the distance between the electrodes at the center. By doing so, the same effect as in the above embodiment can be obtained.

〔The invention's effect〕

As described above, according to the varistor according to the present invention, the inter-electrode distance between the outer peripheral edge of the internal electrode embedded in the sintered body and the surface electrode is increased to 1.05 times or more the inter-electrode distance at the center, This has the effect of improving surge withstand without increasing the electrode area. Further, in the present invention, since the ceramics layer sandwiched between the internal electrode and the surface electrode is located on the surface portion of the sintered body, sufficient oxygen can be supplied at the time of firing, and heat radiation at the time of heat generation can be easily performed. This has the effect of reducing the amount of noble metal used and thus reducing the manufacturing cost, as well as expanding the application by reducing the capacitance.

[Brief description of the drawings]

1 to 3 are views for explaining a chip type varistor according to an embodiment of the present invention. FIG. 1 is a sectional view taken along the line II of FIG. 2, FIG. FIG. 3 is an exploded perspective view, FIGS. 4 and 5 are cross-sectional views and a cross-sectional plan view, respectively, showing a chip varistor for explaining a process of establishing the present invention, and FIG. 6 is a conventional laminated varistor. It is sectional drawing. In the figure, 1 is a chip type varistor, 2 is a sintered body, 3 is an internal electrode, 4 is a surface electrode, 5a is a ceramics layer, t is the distance between the outer peripheral edge of the internal electrode and the surface electrode, and t 'is This is the distance between the electrodes at the center of both electrodes.

Continuation of the front page (56) References JP-A 50-131544 (JP, U) JP-A 62-126801 (JP, U) JP-A 3-116001 (JP, U) (58) Fields surveyed (Int) .Cl. ⁶ , DB name) H01C 7/02-7/22

Claims (1)

(57) [Claims] 1. A varistor comprising: an internal electrode embedded in a ceramic sintered body; and a surface electrode formed on an outer surface of the sintered body and facing the internal electrode with a ceramic layer interposed therebetween. A varistor wherein the distance between the outer peripheral edge of the internal electrode and the surface electrode is 1.05 times or more larger than the distance between the electrodes at the center of both electrodes.