JPH10199752A - Multilayer ceramic electronic part - Google Patents

Multilayer ceramic electronic part

Info

Publication number
JPH10199752A
JPH10199752A JP430297A JP430297A JPH10199752A JP H10199752 A JPH10199752 A JP H10199752A JP 430297 A JP430297 A JP 430297A JP 430297 A JP430297 A JP 430297A JP H10199752 A JPH10199752 A JP H10199752A
Authority
JP
Japan
Prior art keywords
electrodes
multilayer ceramic
ceramic electronic
ceramic
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP430297A
Other languages
Japanese (ja)
Inventor
Yoichi Ogose
洋一 生越
Iwao Ueno
巌 上野
Yasuo Wakahata
康男 若畑
Kaori Okamoto
香織 岡本
昭宏 ▲高▼見
Akihiro Takami
Kimio Kobayashi
喜美男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP430297A priority Critical patent/JPH10199752A/en
Publication of JPH10199752A publication Critical patent/JPH10199752A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To remove a distortion in thermal contraction ratio owing to a difference of thermal expansion coefficient between ceramics and an external electrode and prevent a generation of cracks by a method wherein the external electrodes are formed only at both end surfaces to which an internal electrode of a lamination is exposed. SOLUTION: Internal electrodes 6 are alternately provided so as to expose to an end surface of a ceramic layer 5. A lamination 7 is constituted by this plurality of ceramic layers 5 and internal electrodes 6. External electrodes 8 are provided only on both end surfaces to which the internal electrodes 6 of this lamination 7 are alternately exposed, whereby a distortion due to a difference of thermal contraction ratio is removed in a manufacturing process. Thereby, multilayer ceramic electronic parts which can be sufficiently endured if a heat cycle is applied thereto are manufactured without generating cracks in a ceramic layer.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は各種電子機器に利用
される積層形セラミックコンデンサや積層形バリスタな
どの積層形セラミック電子部品に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer ceramic electronic component such as a multilayer ceramic capacitor and a multilayer varistor used in various electronic devices.

【0002】[0002]

【従来の技術】一般に、電子部品分野においては軽薄短
小化や高性能化の要請が強く、その対策として一般的に
は積層構造のものが多く採用されてきている。
2. Description of the Related Art Generally, in the field of electronic parts, there is a strong demand for lighter, thinner, smaller, and higher performance, and as a countermeasure, generally, those having a laminated structure are often used.

【0003】従来の積層形セラミックコンデンサに代表
される積層形セラミック電子部品としては図6、図7に
示すように構成されていた。すなわち、複数のセラミッ
ク層1の間に内部電極2を交互に対向する端面に表出す
るように設け、この内部電極2が表出する両端面および
この両端面に隣接する4面の一部に外部電極3を形成し
て構成されている。
A multilayer ceramic electronic component represented by a conventional multilayer ceramic capacitor has been configured as shown in FIGS. That is, the internal electrodes 2 are provided so as to be alternately exposed between the plurality of ceramic layers 1 on the opposite end faces. The external electrode 3 is formed.

【0004】このような構成で、その製造方法は、セラ
ミック生シート上に電極ペーストを交互に対向する端縁
に至るように印刷して内部電極2としたものを複数枚積
層し、少なくとも最上層に電極の形成されないセラミッ
ク生シートを積層したものを加圧成形し、これを所定の
寸法に切断して電子部品素体とし、この電子部品素体の
両端に外部電極3を塗布してから焼成して積層形セラミ
ック電子部品としていた。
With such a configuration, the manufacturing method is such that a plurality of internal electrodes 2 are formed by printing an electrode paste on a ceramic raw sheet alternately so as to reach opposite edges, and at least the uppermost layer is formed. A ceramic green sheet having no electrodes formed thereon is pressed and molded into a predetermined size to form an electronic component body. External electrodes 3 are applied to both ends of the electronic component body, and then fired. To form a multilayer ceramic electronic component.

【0005】[0005]

【発明が解決しようとする課題】上記従来の構成および
製造方法においては、焼成時の最高温度から冷却してい
く際に、外部電極3とセラミック層1の熱膨張係数の違
いにより収縮率の違いが発生し、図7に示すようにセラ
ミック層1にクラック4が発生し、電気特性にばらつき
が発生してしまうといった問題があった。このクラック
4の発生は、電子部品素体の両端面に隣接する4面にま
で外部電極3が形成されており、上述の収縮率の違いに
よる歪みが外部電極3の端部に集中することにより、外
部電極3の端部を結ぶ線上に発生するものと考えられ
る。
In the conventional structure and manufacturing method described above, when cooling from the maximum temperature during firing, the difference in the contraction rate due to the difference in the thermal expansion coefficient between the external electrode 3 and the ceramic layer 1 is increased. And cracks 4 occur in the ceramic layer 1 as shown in FIG. 7, resulting in a variation in electrical characteristics. This crack 4 occurs because the external electrodes 3 are formed on the four surfaces adjacent to both end surfaces of the electronic component body, and the strain due to the difference in shrinkage described above is concentrated on the end of the external electrode 3. , On the line connecting the ends of the external electrodes 3.

【0006】すなわち、両端面だけでなく端面に隣接す
る4面に外部電極3が形成されている場合、熱収縮の違
いによる応力が3次元に働き、端面から隣接する4面に
形成されている外部電極3の端部が端面上の外部電極3
に引張られ、これにより外部電極3の4面の端部に応力
が集中し、セラミック層1にクラック4が発生すると考
えられる。
That is, when the external electrodes 3 are formed not only on the end faces but also on the four faces adjacent to the end faces, the stress due to the difference in thermal contraction acts three-dimensionally and is formed on the four faces adjacent to the end faces. The end of the external electrode 3 is the external electrode 3 on the end face.
It is considered that the stress is concentrated on the end portions of the four surfaces of the external electrode 3 and the cracks 4 occur in the ceramic layer 1.

【0007】本発明は以上のような従来の欠点を除去
し、製造時にクラックの発生しない積層形セラミック電
子部品を提供することを目的とするものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a multilayer ceramic electronic component which eliminates the above-mentioned drawbacks of the prior art and does not generate cracks during manufacturing.

【0008】[0008]

【課題を解決するための手段】上記課題を解決するため
に本発明の積層形セラミック電子部品は、セラミック層
の間に交互に端面に表出する内部電極を設けた積層体の
内部電極の表出する両端面のみに外部電極を形成したも
のである。
In order to solve the above-mentioned problems, a laminated ceramic electronic component according to the present invention has a structure in which internal electrodes of a laminated body having internal electrodes alternately exposed on an end face between ceramic layers are provided. The external electrodes are formed only on the both end faces that are exposed.

【0009】上記構成とすることにより、セラミックと
外部電極の熱膨張係数の違いからくる熱収縮率による歪
みによってセラミック層にクラックを発生させることが
阻止できることになる。
With the above configuration, it is possible to prevent cracks from being generated in the ceramic layer due to distortion due to thermal contraction caused by a difference in thermal expansion coefficient between the ceramic and the external electrode.

【0010】[0010]

【発明の実施の形態】本発明の請求項1に記載の発明
は、セラミック層の間に交互に端面に表出する内部電極
を設けた積層体の内部電極の表出する両端面のみに外部
電極を形成したものであり、製造過程で熱収縮率の差に
よるクラックの発生は阻止することができる。
BEST MODE FOR CARRYING OUT THE INVENTION The invention according to the first aspect of the present invention is directed to a laminated body having internal electrodes alternately exposed on the end faces between ceramic layers. An electrode is formed, and it is possible to prevent the occurrence of cracks due to a difference in the heat shrinkage rate during the manufacturing process.

【0011】請求項2に記載の発明は、外部電極を被い
積層体の端面に隣接する他の4面にまたがるように補強
用電極を設けたものであり、外部電極の積層体からの剥
れを阻止することができる。
According to a second aspect of the present invention, the reinforcing electrode is provided so as to cover the external electrode and to extend over the other four surfaces adjacent to the end face of the laminate, and to peel off the external electrode from the laminate. Can be prevented.

【0012】以下、本発明の積層形セラミック電子部品
の一実施の形態の具体例について図面を用いて説明す
る。
Hereinafter, a specific example of an embodiment of the multilayer ceramic electronic component of the present invention will be described with reference to the drawings.

【0013】図1は本発明の一実施の形態における積層
形セラミックコンデンサを例とする積層形セラミック電
子部品の一部切欠斜視図、図2は同要部の断面図、図3
は同製造工程上の分解斜視図、図4は同製造方法を示す
工程図、図5は他の例を示す要部の断面図である。
FIG. 1 is a partially cutaway perspective view of a multilayer ceramic electronic component as an example of a multilayer ceramic capacitor according to an embodiment of the present invention. FIG.
FIG. 4 is an exploded perspective view showing the same manufacturing process, FIG. 4 is a process diagram showing the same manufacturing method, and FIG. 5 is a sectional view of a main part showing another example.

【0014】まず、図1、図2において、5はセラミッ
ク層であり、6は交互にセラミック層5の端面に表出す
るように設けた内部電極、7はこの複数のセラミック層
5と内部電極6によって構成された積層体、8はこの積
層体7の内部電極6の交互に表出する両端面にのみ設け
られた外部電極である。
First, in FIGS. 1 and 2, 5 is a ceramic layer, 6 is an internal electrode provided so as to be alternately exposed on the end face of the ceramic layer 5, and 7 is a plurality of ceramic layers 5 and the internal electrode. The laminated body constituted by 6 and 8 are external electrodes provided only on both end faces of the laminated body 7 which are alternately exposed.

【0015】次に上記構成の積層形セラミック電子部品
を製造する方法について説明する。まず、SrTiO3
(98.0mol%)を主成分とし、これにNb2
5(1.0mol%),MnO(1.0mol%)を混
合してなるセラミック材料を空気中で600〜1200
℃で仮焼し、平均粒径が0.5μm以下になるように粉
砕し、この粉砕された微粉末を出発原料とした。
Next, a method of manufacturing the multilayer ceramic electronic component having the above-described structure will be described. First, SrTiO 3
(98.0 mol%) as the main component, and Nb 2 O
5 (1.0 mol%) and MnO (1.0 mol%) are mixed with each other to form a ceramic material of 600 to 1200 in air.
C. and calcined so that the average particle size becomes 0.5 μm or less, and the pulverized fine powder was used as a starting material.

【0016】この微粉末の出発原料をブチラール樹脂な
どの有機バインダーとともに溶媒中に分散させてスラリ
ー状とし、このスラリーをドクターブレード法によって
20μm程度の厚さの生シートにして所定の大きさに切
断した。
The starting material of the fine powder is dispersed in a solvent together with an organic binder such as butyral resin in a solvent to form a slurry, and the slurry is cut into a predetermined size into a raw sheet having a thickness of about 20 μm by a doctor blade method. did.

【0017】次に図3に示すように、生シート9の上に
Pdからなる内部電極ペースト10を所定の大きさに応
じてスクリーン印刷によりパターン印刷した。このよう
に内部電極ペースト10を印刷した生シート9を複数枚
積層し、最上層および最下層の生シート9aには内部電
極ペーストを印刷しないものを積層した。また、内部電
極ペースト10を印刷した生シート9は、内部電極ペー
スト10が端縁まで形成される側を交互に対向する端縁
にくるように積層し、最終的には加熱しながら加圧して
圧着した。
Next, as shown in FIG. 3, an internal electrode paste 10 made of Pd was pattern-printed on a raw sheet 9 by screen printing according to a predetermined size. A plurality of the raw sheets 9 on which the internal electrode paste 10 was printed in this way were laminated, and those on which the internal electrode paste was not printed were laminated on the uppermost and lowermost raw sheets 9a. Further, the raw sheet 9 on which the internal electrode paste 10 is printed is laminated so that the side on which the internal electrode paste 10 is formed up to the edge alternately comes to the opposite edge, and finally pressurized while heating. Crimped.

【0018】次に空気中で600〜1250℃で脱脂、
仮焼を行った後、内部電極6が表出した両端面に隣接す
る4面にAg−Pdからなる外部電極ペーストがまわり
こまないように塗布し、還元雰囲気中で1200〜13
50℃で焼成した。この焼成後、空気中で900〜12
50℃で再酸化して図1、図2に示す積層形セラミック
電子部品とした。
Next, degreasing at 600 to 1250 ° C. in air,
After the calcination, an external electrode paste made of Ag-Pd is applied on four surfaces adjacent to both end surfaces on which the internal electrodes 6 are exposed so as not to flow around, and then coated in a reducing atmosphere at 1200 to 13%.
It was baked at 50 ° C. After this firing, 900-12 in air
It was reoxidized at 50 ° C. to obtain a multilayer ceramic electronic component shown in FIGS.

【0019】なお、外部電極8の剥れが心配な場合は、
上記外部電極8を被うようにAgよりなる補強用電極ペ
ーストを隣接する4面の一部にも形成されるように塗布
し、空気中で850℃、15分間焼付けて補強用電極1
1を形成した。
If there is a concern that the external electrode 8 will peel off,
A reinforcing electrode paste made of Ag is applied so as to cover the external electrodes 8 so as to be formed also on a part of the four adjacent surfaces, and baked in air at 850 ° C. for 15 minutes to form the reinforcing electrode 1.
1 was formed.

【0020】この製造方法を図4に示すとともにその構
成を図5に示す。また、具体例としては幅3.2mm、奥
行き1.6mm、厚み0.5mmの寸法で内部電極の形成さ
れた有効層を30層、上下端面に無効層を配置して積層
したバリスタ機能付セラミックコンデンサとし、その容
量と容量のばらつき、さらに割れの発生率を(表1)に
示した。ただし、このときの焼成などの各条件は粉末段
階における空気中での脱脂、仮焼は1200℃、2時
間、N2:H2=99:1の還元雰囲気中での焼成は13
00℃、2時間、再酸化は1100℃、1時間で行った
ものである。
FIG. 4 shows this manufacturing method, and FIG. 5 shows its structure. Further, as a specific example, a ceramic with a varistor function, in which 30 effective layers having internal electrodes formed thereon and having dimensions of 3.2 mm in width, 1.6 mm in depth and 0.5 mm in thickness, and ineffective layers arranged on upper and lower end surfaces, is laminated. The capacitors were used as capacitors, and their capacities, variations in capacities, and cracking rates are shown in Table 1. However, the respective conditions such as firing at this time are as follows: degreasing and calcination in the powder stage in air at 1200 ° C. for 2 hours, and firing in a reducing atmosphere of N 2 : H 2 = 99: 1 is 13 hours.
The reoxidation was performed at 1100 ° C. for 1 hour at 00 ° C. for 2 hours.

【0021】なお、容量Cは測定電圧1.0V、周波数
1.0kHzでの値であり、割れの発生率は、樹脂中に
測定済みのバリスタ機能付セラミックコンデンサを埋め
込み、バフ研磨などの研磨をし、顕微鏡観察を行って得
たものである。
The capacitance C is a value at a measured voltage of 1.0 V and a frequency of 1.0 kHz. The cracking rate is determined by embedding a measured varistor function-equipped ceramic capacitor in a resin and performing polishing such as buffing. And obtained by microscopic observation.

【0022】[0022]

【表1】 [Table 1]

【0023】(表1)から明らかなように本発明による
積層形セラミック電子部品は、従来例に比べ割れも抑制
され、容量のばらつきも著しく低減されている。
As can be seen from Table 1, the multilayer ceramic electronic component according to the present invention has less cracks than the prior art, and the variation in capacitance is significantly reduced.

【0024】なお、本実施の形態においては、セラミッ
ク材料にSrTiO3系の材料を用いたが、この材料と
してはBaTiO3などの他の誘電体材料やZnOやサ
ーミスタなどの半導体セラミックでも有効である。
In this embodiment, an SrTiO 3 -based material is used as the ceramic material, but other dielectric materials such as BaTiO 3 and semiconductor ceramics such as ZnO and thermistors are also effective. .

【0025】また、内部電極用ペースト10にPd、外
部電極用ペーストにPd−Agを用いたが、内部電極に
Pt、Pd−Agや卑金属であるNi、Cu、外部電極
にPt、Pd、Ni、Cuあるいはそれらの混合物のペ
ーストを用いてもよい。
Although Pd was used for the internal electrode paste 10 and Pd-Ag was used for the external electrode paste, Pt, Pd-Ag and the base metals Ni and Cu were used for the internal electrodes, and Pt, Pd, and Ni were used for the external electrodes. , Cu, or a paste of a mixture thereof may be used.

【0026】[0026]

【発明の効果】以上のように本発明によれば、セラミッ
ク層にクラックを発生させることなく、ヒートサイクル
が加えられても十分に耐えられる積層形セラミック電子
部品とすることができる。
As described above, according to the present invention, it is possible to obtain a laminated ceramic electronic component which can sufficiently withstand a heat cycle without causing cracks in the ceramic layer.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の積層形セラミック電子部品の一実施の
形態における一部切欠斜視図
FIG. 1 is a partially cutaway perspective view of a laminated ceramic electronic component according to an embodiment of the present invention.

【図2】同要部の断面図FIG. 2 is a cross-sectional view of the main part.

【図3】同製造工程途上の分解斜視図FIG. 3 is an exploded perspective view during the manufacturing process.

【図4】同製造工程図FIG. 4 is a manufacturing process diagram of the same.

【図5】他の実施の形態の要部の断面図FIG. 5 is a sectional view of a main part according to another embodiment.

【図6】従来の積層形セラミック電子部品の一部切欠斜
視図
FIG. 6 is a partially cutaway perspective view of a conventional multilayer ceramic electronic component.

【図7】同要部の断面図FIG. 7 is a cross-sectional view of the main part.

【符号の説明】[Explanation of symbols]

5 セラミック層 6 内部電極 7 積層体 8 外部電極 11 補強用電極 Reference Signs List 5 ceramic layer 6 internal electrode 7 laminate 8 external electrode 11 reinforcing electrode

フロントページの続き (72)発明者 岡本 香織 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 ▲高▼見 昭宏 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 小林 喜美男 大阪府門真市大字門真1006番地 松下電器 産業株式会社内Continued on the front page (72) Inventor Kaori Okamoto 1006 Kazuma Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. 72) Inventor Kimio Kobayashi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 セラミック層の間に交互に端面に表出す
る内部電極を設けた積層体の内部電極の表出する両端面
のみに外部電極を形成してなる積層形セラミック電子部
品。
1. A multilayer ceramic electronic component in which external electrodes are formed only on both exposed end faces of an internal electrode of a laminate having internal electrodes alternately exposed on end faces between ceramic layers.
【請求項2】 積層体の両端面に設けた外部電極を被い
積層体の端面に隣接する他の4面にまたがるように補強
用電極を設けた請求項1に記載の積層形セラミック電子
部品。
2. The multilayer ceramic electronic component according to claim 1, wherein external electrodes provided on both end surfaces of the multilayer body are covered, and reinforcing electrodes are provided so as to extend over the other four surfaces adjacent to the end surface of the multilayer body. .
JP430297A 1997-01-14 1997-01-14 Multilayer ceramic electronic part Pending JPH10199752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP430297A JPH10199752A (en) 1997-01-14 1997-01-14 Multilayer ceramic electronic part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP430297A JPH10199752A (en) 1997-01-14 1997-01-14 Multilayer ceramic electronic part

Publications (1)

Publication Number Publication Date
JPH10199752A true JPH10199752A (en) 1998-07-31

Family

ID=11580724

Family Applications (1)

Application Number Title Priority Date Filing Date
JP430297A Pending JPH10199752A (en) 1997-01-14 1997-01-14 Multilayer ceramic electronic part

Country Status (1)

Country Link
JP (1) JPH10199752A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001358032A (en) * 2000-06-12 2001-12-26 Matsushita Electric Ind Co Ltd Chip electronic parts
US6769159B2 (en) * 1998-07-27 2004-08-03 Murata Manufacturing Co., Ltd. Method for producing a ceramic electronic part
JP2008186951A (en) * 2007-01-29 2008-08-14 Tdk Corp Varistor element
JP2012038917A (en) * 2010-08-06 2012-02-23 Murata Mfg Co Ltd Ceramic electronic component and method for manufacturing the same
JP2014003053A (en) * 2011-08-09 2014-01-09 Murata Mfg Co Ltd Thermistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6769159B2 (en) * 1998-07-27 2004-08-03 Murata Manufacturing Co., Ltd. Method for producing a ceramic electronic part
JP2001358032A (en) * 2000-06-12 2001-12-26 Matsushita Electric Ind Co Ltd Chip electronic parts
JP2008186951A (en) * 2007-01-29 2008-08-14 Tdk Corp Varistor element
JP2012038917A (en) * 2010-08-06 2012-02-23 Murata Mfg Co Ltd Ceramic electronic component and method for manufacturing the same
JP2014003053A (en) * 2011-08-09 2014-01-09 Murata Mfg Co Ltd Thermistor

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