JP2756745B2 - Manufacturing method of multilayer ceramic capacitor - Google Patents

Manufacturing method of multilayer ceramic capacitor

Info

Publication number
JP2756745B2
JP2756745B2 JP7828692A JP7828692A JP2756745B2 JP 2756745 B2 JP2756745 B2 JP 2756745B2 JP 7828692 A JP7828692 A JP 7828692A JP 7828692 A JP7828692 A JP 7828692A JP 2756745 B2 JP2756745 B2 JP 2756745B2
Authority
JP
Japan
Prior art keywords
internal electrode
layer
ceramic
particle size
laminate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7828692A
Other languages
Japanese (ja)
Other versions
JPH05243081A (en
Inventor
貴文 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP7828692A priority Critical patent/JP2756745B2/en
Publication of JPH05243081A publication Critical patent/JPH05243081A/en
Application granted granted Critical
Publication of JP2756745B2 publication Critical patent/JP2756745B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、内部電極層とセラミッ
ク層との間の剥離を防ぐことができる積層セラミックコ
ンデンサ(積層磁器コンデンサ)の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multilayer ceramic capacitor (multilayer ceramic capacitor) capable of preventing separation between an internal electrode layer and a ceramic layer.

【0002】[0002]

【従来の技術】積層セラミックコンデンサを製作する時
には、内部電極層(コンデンサ電極層)を有するセラミ
ック生シート(グリーンシート)の複数枚と、これ等の
上下に配置された内部電極層を持たないカバー用セラミ
ック生シートと、必要に応じて内部電極層を有するセラ
ミック生シートの複数の組の間に配置された内部電極層
を持たないトリム即ち調製用セラミック生シートとの積
層体を焼成する。
2. Description of the Related Art When a multilayer ceramic capacitor is manufactured, a plurality of ceramic green sheets (green sheets) having internal electrode layers (capacitor electrode layers) and a cover having no internal electrode layers disposed above and below these sheets are provided. A laminate of the ceramic green sheet for preparation and a trim having no internal electrode layer, that is, a ceramic raw sheet for preparation, disposed between a plurality of sets of the ceramic green sheet having internal electrode layers as necessary.

【0003】[0003]

【発明が解決しようとする課題】ところで、内部電極層
とカバー層又はトリム層との間にデラミネーション(剥
離)が生じることがある。このデラミネーションは、積
層体の熱伝導率の不均一性及び圧着の不均一性に基づい
て生じるものと考えられる。即ち、内部電極層はセラミ
ック層よりも熱伝導率が大きいために、内部電極層に挟
まれた比較的薄い領域の焼結及び収縮が比較的厚いカバ
ー層やトリム層よりも早く始まり、ここでは内部電極層
とセラミックが良好に密着するが、焼結が遅れるカバー
層やトリム層では内部電極層にセラミックが良好に密着
せず、デラミネーションが生じる。また、積層体の中央
部の内部電極層の相互間のセラミック層は比較的薄いの
で、内部電極層の厚みを無視することができず、圧着時
に内部電極層のセラミック層に対する強いくい込みが生
じて良好な密着性が得られるが、比較的厚いカバー層又
はトリム層に対しては内部電極層の強いくい込みが生じ
ないために密着性が悪くなり、結果としてデラミネーシ
ョンが生じる。
Incidentally, delamination (peeling) may occur between the internal electrode layer and the cover layer or the trim layer. This delamination is considered to be caused by the non-uniformity of the thermal conductivity and the non-uniformity of the pressure bonding of the laminate. That is, since the internal electrode layer has a higher thermal conductivity than the ceramic layer, sintering and shrinkage of a relatively thin region sandwiched between the internal electrode layers starts earlier than a relatively thick cover layer or trim layer. Although the internal electrode layer and the ceramic adhere well, the ceramic does not adhere well to the internal electrode layer in the cover layer or trim layer where sintering is delayed, and delamination occurs. Also, since the ceramic layers between the internal electrode layers in the center of the laminate are relatively thin, the thickness of the internal electrode layers cannot be ignored, and the internal electrode layers are strongly penetrated into the ceramic layers during crimping. Although good adhesion can be obtained, adhesion to the relatively thick cover layer or trim layer does not occur because strong penetration of the internal electrode layer does not occur, resulting in delamination.

【0004】そこで、本発明の目的は、内部電極層の剥
離(デラミネーション)が生じにくい積層セラミックコ
ンデンサの製造方法を提供することにある。
It is an object of the present invention to provide a method for manufacturing a multilayer ceramic capacitor in which the internal electrode layer is less likely to peel (delamination).

【0005】[0005]

【課題を解決するための手段】上記目的を達成するため
の本発明は、第1の粒径の第1のセラミック粉末から成
る第1のセラミック生シートに内部電極層を設けたもの
を複数枚積層した容量取得部と、内部電極層を具備して
いない前記第1の粒径よりも小さい第2の粒径の第2の
セラミック粉末から成る第2のセラミック生シートの単
数又は複数から成るカバー部及び/又はトリム部とを有
する積層体を形成し、この積層体を焼成することを特徴
とする積層セラミックコンデンサの製造方法に係わるも
のである。
In order to achieve the above-mentioned object, the present invention provides a first ceramic green sheet comprising a first ceramic powder having a first particle size and a plurality of sheets each having an internal electrode layer provided thereon. A cover made of one or more of a stacked capacitance acquisition portion and a second ceramic green sheet made of a second ceramic powder having a second particle size smaller than the first particle size and not having the internal electrode layer. The present invention relates to a method for manufacturing a multilayer ceramic capacitor, which comprises forming a laminate having a portion and / or a trim portion and firing the laminate.

【0006】[0006]

【作用及び効果】一般的に、セラミック粉末の粒径が小
さくなると、反応性が高まり焼結の始まる温度が低くな
る。本発明においては、カバー部とトリム部とのいずれ
か一方又は両方のセラミック粉末の粒径が内部電極層を
備えた第1のセラミック生シートのセラミック粉末の粒
径よりも小さいので、カバー部及び/又はトリム部の焼
結の開始を早める作用が生じ、積層体の全領域における
焼結開始の均一化が達成され、内部電極のデラミネーシ
ョンを防ぐことができる。
In general, as the particle size of the ceramic powder becomes smaller, the reactivity increases and the temperature at which sintering starts is lowered. In the present invention, since the particle size of the ceramic powder of one or both of the cover portion and the trim portion is smaller than the particle size of the ceramic powder of the first ceramic green sheet provided with the internal electrode layer, An effect of hastening the start of sintering of the trim portion occurs, and uniform sintering start is achieved in all regions of the laminate, and delamination of the internal electrodes can be prevented.

【0007】[0007]

【実施例】次に、本発明の実施例に係わる積層セラミッ
クコンデンサの製造方法を説明する。まず、X7R規格
用のコンデンサを得るために、平均粒径が1.0μm
(第1の粒径)と0.5μm(第2の粒径)の2種類の
(BaTiO3 +Nb2 5 +Co2 3 )+SrO組
成のチタン酸バリウム系セラミック粉末を用意した。次
に、1.0μm及び0.5μmのセラミック粉末に対し
て有機バインダーを加えて夫々のスラリーを形成し、ド
クターブレード法によって厚さ約23μmの長尺のセラ
ミック生シート(磁器生シート)即ちグリーンシートを
夫々形成し、所定の寸法に切断することによって複数枚
の第1及び第2のグリーンシートを夫々得た。
Next, a method of manufacturing a multilayer ceramic capacitor according to an embodiment of the present invention will be described. First, in order to obtain a capacitor for X7R standard, the average particle size is 1.0 μm.
Two kinds of (BaTiO 3 + Nb 2 O 5 + Co 2 O 3 ) + SrO barium titanate-based ceramic powder of (first particle size) and 0.5 μm (second particle size) were prepared. Next, an organic binder is added to the ceramic powders of 1.0 μm and 0.5 μm to form respective slurries, and a long ceramic raw sheet (porcelain raw sheet) of about 23 μm in thickness, that is, green by a doctor blade method. A plurality of first and second green sheets were respectively obtained by forming sheets and cutting them into predetermined dimensions.

【0008】次に、粒径1.0μmのセラミック粉末に
基づく複数枚の第1のグリーンシートにパラジウム(P
d)と有機バインダーと溶剤とから成る導電性ペースト
を塗布して積層コンデンサ50個分の内部電極層を所定
パターンに形成した。
Next, palladium (P) is applied to a plurality of first green sheets based on ceramic powder having a particle size of 1.0 μm.
A conductive paste composed of d), an organic binder, and a solvent was applied to form a predetermined pattern of internal electrode layers for 50 laminated capacitors.

【0009】次に、内部電極層を有する複数枚の第1の
グリーンシートと内部電極層を持たない粒径0.5μm
のセラミック粉末から成る第2のグリーンシートとを周
知の方法で積層し、圧力350kg/cm2 、70℃の条件
で熱圧着した後に所定の寸法(1.83mm×0.92m
m)切断することによって図1に示す構造の積層体を5
0個得た。この積層体1は、内部電極層2を有する粒径
1.0μmのセラミック粉末に基づく第1のグリーンシ
ートから成る電極用層E1 、E2 、E3 、E4 と、内部
電極層を持たない粒径0.5μmのセラミック粉末に基
づく第2のグリーンシートから成るカバー層C1 、C2
、C3 、C4 、C5 及びトリム層T1 との積層体から
成る。熱圧着した後には各グリーンシートは一体化され
るが、説明の都合上図1では独立に示されている。
Next, a plurality of first green sheets having an internal electrode layer and a particle size of 0.5 μm having no internal electrode layer
A second green sheet made of a ceramic powder is laminated by a known method and thermocompressed under the conditions of a pressure of 350 kg / cm 2 and 70 ° C., and then a predetermined size (1.83 mm × 0.92 m) is obtained.
m) By cutting, the laminate having the structure shown in FIG.
0 were obtained. This laminate 1 has electrode layers E1, E2, E3, E4 composed of a first green sheet based on a ceramic powder having a particle diameter of 1.0 μm and having an internal electrode layer 2; Cover layers C1, C2 consisting of a second green sheet based on 0.5 .mu.m ceramic powder
, C3, C4, C5 and a trim layer T1. After the thermocompression bonding, the green sheets are integrated, but are separately shown in FIG. 1 for convenience of explanation.

【0010】図1において、複数の内部電極層2は交互
に反対方向に導出されている。最も上の内部電極層2の
上には3枚のカバー層C1 〜C3 が配置され、最も下の
電極用層E4 の下には2枚のカバー層C4 、C5 が配置
され、中間の電極用層E2 、E3 間にトリム層T1 が配
置されている。トリム層T1 は、内部電極層2を伴なっ
ている上側の2枚の電極用層E1 、E2 から成る第1の
容量取得部と下側の2枚の電極用層E3 、E4 から成る
第2の容量取得部との間に介在して緩衝層として機能す
る。
In FIG. 1, a plurality of internal electrode layers 2 are alternately led out in opposite directions. Three cover layers C1 to C3 are arranged on the uppermost internal electrode layer 2, and two cover layers C4 and C5 are arranged below the lowermost electrode layer E4. A trim layer T1 is arranged between the layers E2 and E3. The trim layer T1 is composed of a first capacitance acquisition section composed of two upper electrode layers E1 and E2 with an internal electrode layer 2 and a second capacitance acquisition section composed of two lower electrode layers E3 and E4. And functions as a buffer layer interposed between them.

【0011】次に、積層体1を炉に入れて、大気雰囲気
中で室温から1100℃までは40℃/hrの昇温速度で
加熱し、1100℃から1300℃までは160℃/hr
の昇温速度で加熱し、1300℃を1時間保持すること
によって焼結体を得た。次に、図2に示すように焼結体
3に一対の外部電極層4、5を設けて積層セラミックコ
ンデンサを完成させた。
Next, the laminate 1 is placed in a furnace and heated at a rate of 40 ° C./hr from room temperature to 1100 ° C. in the air atmosphere, and 160 ° C./hr from 1100 ° C. to 1300 ° C.
And heated at 1300 ° C. for 1 hour to obtain a sintered body. Next, as shown in FIG. 2, a pair of external electrode layers 4 and 5 were provided on the sintered body 3 to complete a multilayer ceramic capacitor.

【0012】次に、この焼結体3における内部電極層2
aのセラミック層3aに対するデラミネーション(剥
離)を調べたところ、50個のコンデンサのすべてにお
いて発生していなかった。比較のために、カバー層C1
〜C5 、トリム層T1 のセラミック粉末の粒径を電極用
層E1 〜E4 と同一の1.0μmとした他は、実施例と
同一の方法で焼結体を作り、内部電極層のデラミネーシ
ョンを調べたところ、50個のコンデンサにつき32個
発生していた。
Next, the internal electrode layer 2 in the sintered body 3
When delamination (peeling) of the ceramic layer 3a into the ceramic layer 3a was examined, no delamination occurred in all of the 50 capacitors. For comparison, the cover layer C1
C5, the sintered body was made in the same manner as in the embodiment except that the particle size of the ceramic powder of the trim layer T1 was 1.0 μm, which is the same as that of the electrode layers E1 to E4, and the delamination of the internal electrode layer was reduced. Inspection revealed that 32 capacitors were generated for every 50 capacitors.

【0013】また、カバー層C1 〜C5 とトリム層T1
のセラミック粉末の粒径の変化とデラミネーションとの
関係を詳しく調べるために、電極用層E1 〜E4 のセラ
ミック粉末の粒径を1.0μm一定として、カバー層C
1 〜C5 及びトリム層T1 のセラミック粉末の粒径を
0.4、0.6、0.7、0.8、0.9、1.2μm
に変化させた他は前述の実施例と同一の方法で焼結体を
作り、内部電極層のデラミネーションを夫々調べたとこ
ろ、2個、0個、0個、0個、5個、45個であった。
これから明らかなように、カバー層C1 〜C5 及びトリ
ム層T1 のセラミック粉末の粒径を0.5〜0.8μm
にすること、即ち電極用層E1 〜E4 のセラミック粉末
の粒径に対して50%〜80%にすることが望ましい。
なお、焼成時の1100℃〜1300℃までの昇温速度
を320℃/hr、又は80℃/hrにした場合においても
同様な結果が得られた。但し、昇温速度を低くすればす
るほどデラミネーションの発生は低下した。
The cover layers C1 to C5 and the trim layer T1
In order to investigate in detail the relationship between the change in the particle size of the ceramic powder and the delamination, the cover layer C was prepared by setting the particle size of the ceramic powder in the electrode layers E1 to E4 to 1.0 μm.
1 to C5 and the particle size of the ceramic powder of the trim layer T1 are 0.4, 0.6, 0.7, 0.8, 0.9 and 1.2 .mu.m.
A sintered body was prepared in the same manner as in the above embodiment except that the internal electrode layer was delaminated, and two, zero, zero, zero, five, and forty-five were obtained. Met.
As is clear from this, the particle size of the ceramic powder of the cover layers C1 to C5 and the trim layer T1 is 0.5 to 0.8 .mu.m.
In other words, it is desirable that the content be 50% to 80% with respect to the particle size of the ceramic powder of the electrode layers E1 to E4.
Similar results were obtained when the rate of temperature increase from 1100 ° C to 1300 ° C during firing was 320 ° C / hr or 80 ° C / hr. However, the lower the heating rate, the lower the occurrence of delamination.

【0014】[0014]

【変形例】本発明は上述の実施例に限定されるものでな
く、例えば次の変形が可能なものである。 (1) セラミック粉末の組成及び/又は粒径を種々変
えることができる。 (2) トリム層T1 を省くことができる。 (3) 電極用層の数を更に増やすことができる。 (4) 積層体の焼成温度は組成の変化等に応じて例え
ば900℃〜1400℃の範囲で変えることができる。 (5) 内部電極層の電極材料として銀、銀−パラジウ
ム、ニッケル等を使用することができる。 (6) セラミック生シ−トの厚さを種々変えることが
できる。
[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) The composition and / or particle size of the ceramic powder can be variously changed. (2) The trim layer T1 can be omitted. (3) The number of electrode layers can be further increased. (4) The firing temperature of the laminate can be changed, for example, in the range of 900 ° C. to 1400 ° C. according to a change in composition or the like. (5) Silver, silver-palladium, nickel or the like can be used as an electrode material of the internal electrode layer. (6) The thickness of the ceramic green sheet can be variously changed.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例に係わる積層体を示す断面図で
ある。
FIG. 1 is a sectional view showing a laminate according to an embodiment of the present invention.

【図2】完成した積層セラミックコンデンサを示す断面
図である。
FIG. 2 is a cross-sectional view showing a completed multilayer ceramic capacitor.

【符号の説明】[Explanation of symbols]

2 内部電極 E1 〜E4 電極用層 C1 〜C5 カバー層 T1 トリム層 2 Internal electrodes E1 to E4 Electrode layers C1 to C5 Cover layer T1 Trim layer

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 第1の粒径の第1のセラミック粉末から
成る第1のセラミック生シートに内部電極層を設けたも
のを複数枚積層した容量取得部と、内部電極層を具備し
ていない前記第1の粒径よりも小さい第2の粒径の第2
のセラミック粉末から成る第2のセラミック生シートの
単数又は複数から成るカバー部及び/又はトリム部とを
有する積層体を形成し、この積層体を焼成することを特
徴とする積層セラミックコンデンサの製造方法。
1. A capacity acquisition section in which a plurality of first ceramic green sheets made of a first ceramic powder having a first particle size and provided with internal electrode layers are stacked, and no internal electrode layer is provided. A second particle having a second particle size smaller than the first particle size;
Forming a laminate having at least one cover portion and / or trim portion of a second ceramic green sheet made of a ceramic powder, and firing the laminate. .
JP7828692A 1992-02-28 1992-02-28 Manufacturing method of multilayer ceramic capacitor Expired - Fee Related JP2756745B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7828692A JP2756745B2 (en) 1992-02-28 1992-02-28 Manufacturing method of multilayer ceramic capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7828692A JP2756745B2 (en) 1992-02-28 1992-02-28 Manufacturing method of multilayer ceramic capacitor

Publications (2)

Publication Number Publication Date
JPH05243081A JPH05243081A (en) 1993-09-21
JP2756745B2 true JP2756745B2 (en) 1998-05-25

Family

ID=13657714

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7828692A Expired - Fee Related JP2756745B2 (en) 1992-02-28 1992-02-28 Manufacturing method of multilayer ceramic capacitor

Country Status (1)

Country Link
JP (1) JP2756745B2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4983307B2 (en) * 2006-03-20 2012-07-25 Tdk株式会社 Multilayer electronic component and manufacturing method thereof
JP4782598B2 (en) * 2006-03-28 2011-09-28 京セラ株式会社 Multilayer ceramic capacitor
KR20120091655A (en) * 2011-02-09 2012-08-20 삼성전기주식회사 Multilayer ceramic electronic part and a manufacturing method thereof
KR101580349B1 (en) * 2012-01-31 2015-12-24 삼성전기주식회사 Multilayered ceramic electronic component and fabricating method thereof

Also Published As

Publication number Publication date
JPH05243081A (en) 1993-09-21

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