JPH042046U - - Google Patents
Info
- Publication number
- JPH042046U JPH042046U JP4192590U JP4192590U JPH042046U JP H042046 U JPH042046 U JP H042046U JP 4192590 U JP4192590 U JP 4192590U JP 4192590 U JP4192590 U JP 4192590U JP H042046 U JPH042046 U JP H042046U
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor element
- resin
- die
- sealed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Description
第１図は、実施例の説明図、第２図は、別の実
施例の説明図、第３図は、絶縁膜の説明図、第４
図は、従来例の説明図、第５図は、蒸気の作用説
明図、第６図は、別の従来例の説明図である。 １，１１……樹脂封止型半導体装置、２，１２
……ダイパツト、３，４，１３乃至１６……外側
面、８……リード、９……絶縁膜、２０……半導
体素子、２１，３１……パツケージ。
施例の説明図、第３図は、絶縁膜の説明図、第４
図は、従来例の説明図、第５図は、蒸気の作用説
明図、第６図は、別の従来例の説明図である。 １，１１……樹脂封止型半導体装置、２，１２
……ダイパツト、３，４，１３乃至１６……外側
面、８……リード、９……絶縁膜、２０……半導
体素子、２１，３１……パツケージ。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 半導体素子を装着したダイパツトと、 前記ダイパツトの周辺に配設した複数のリード
と、 前記半導体素子と前記ダイパツトと前記各リー
ドのダイパツト側の端部とを封止したパツケージ
とにより構成した樹脂封止型半導体装置において
、 前記ダイパツトの一部または全部の外側面を外
方へ膨出させた状態で、かつ膨出させた外側面を
凸状曲面に形成し、 前記ダイパツトの外側面をも前記パツケージで
覆つたことを特徴とする樹脂封止型半導体装置。 (2) 前記ダイパツトにおいて、半導体素子が装
着される部分を除いた部分で、少なくとも半導体
素子装着側のダイパツト面に絶縁膜を設けたこと
を特徴とする請求項１記載の樹脂封止型半導体装
置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4192590U JPH042046U (ja) | 1990-04-19 | 1990-04-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4192590U JPH042046U (ja) | 1990-04-19 | 1990-04-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH042046U true JPH042046U (ja) | 1992-01-09 |
Family
ID=31553013
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4192590U Pending JPH042046U (ja) | 1990-04-19 | 1990-04-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH042046U (ja) |
-
1990
- 1990-04-19 JP JP4192590U patent/JPH042046U/ja active Pending