JPS63178342U - - Google Patents

Info

Publication number
JPS63178342U
JPS63178342U JP1987070466U JP7046687U JPS63178342U JP S63178342 U JPS63178342 U JP S63178342U JP 1987070466 U JP1987070466 U JP 1987070466U JP 7046687 U JP7046687 U JP 7046687U JP S63178342 U JPS63178342 U JP S63178342U
Authority
JP
Japan
Prior art keywords
semiconductor device
resin
die pad
utility
scope
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987070466U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987070466U priority Critical patent/JPS63178342U/ja
Publication of JPS63178342U publication Critical patent/JPS63178342U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205—Shape
    • H01L2224/32057—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10158—Shape being other than a cuboid at the passive surface

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は実施例の断面図、第２図は実施例の平
面図、第３図及び第４図は他の実施例の断面図、
第５図は他の実施例の平面図である。 １はダイパツド、２は凹部、３はリードフレー
ム、４はＡｇペースト、５は半導体装置、６は樹
脂、７は樹脂封止型半導体装置、８は金線、９は
凸部、１０は溝である。

Claims (1)

    【実用新案登録請求の範囲】
  1. ダイパツド上面の少くなくとも半導体装置に対
    応する部分に凹凸部を設けたことを特徴とする樹
    脂封止型半導体装置。
JP1987070466U 1987-05-12 1987-05-12 Pending JPS63178342U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987070466U JPS63178342U (ja) 1987-05-12 1987-05-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987070466U JPS63178342U (ja) 1987-05-12 1987-05-12

Publications (1)

Publication Number Publication Date
JPS63178342U true JPS63178342U (ja) 1988-11-18

Family

ID=30912127

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987070466U Pending JPS63178342U (ja) 1987-05-12 1987-05-12

Country Status (1)

Country Link
JP (1) JPS63178342U (ja)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0710939U (ja) * 1993-07-28 1995-02-14 サンケン電気株式会社 回路基板を有する半導体装置
JPH07201893A (ja) * 1995-01-31 1995-08-04 Sony Corp 半導体装置
JP2011171766A (ja) * 2011-05-27 2011-09-01 Seiko Instruments Inc 半導体装置
JP2011253972A (ja) * 2010-06-03 2011-12-15 Renesas Electronics Corp 半導体装置及びその製造方法
JP2014197634A (ja) * 2013-03-29 2014-10-16 新電元工業株式会社 リードフレーム、半導体装置及びその製造方法
JP2015060916A (ja) * 2013-09-18 2015-03-30 セイコーインスツル株式会社 半導体装置
JP2016213505A (ja) * 2016-09-07 2016-12-15 日亜化学工業株式会社 発光装置用パッケージ成形体及びそれを用いた発光装置
US9893255B2 (en) 2012-01-20 2018-02-13 Nichia Corporation Molded package and light emitting device
US10163829B2 (en) 2017-02-20 2018-12-25 Murata Manufacturing Co., Ltd. Compound semiconductor substrate and power amplifier module

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0710939U (ja) * 1993-07-28 1995-02-14 サンケン電気株式会社 回路基板を有する半導体装置
JPH07201893A (ja) * 1995-01-31 1995-08-04 Sony Corp 半導体装置
JP2011253972A (ja) * 2010-06-03 2011-12-15 Renesas Electronics Corp 半導体装置及びその製造方法
JP2011171766A (ja) * 2011-05-27 2011-09-01 Seiko Instruments Inc 半導体装置
US9893255B2 (en) 2012-01-20 2018-02-13 Nichia Corporation Molded package and light emitting device
US10050186B2 (en) 2012-01-20 2018-08-14 Nichia Corporation Light emitting device
US10522731B2 (en) 2012-01-20 2019-12-31 Nichia Corporation Method of manufacturing light emitting device and light emitting device
US11018286B2 (en) 2012-01-20 2021-05-25 Nichia Corporation Method of manufacturing light emitting device and light emitting device
JP2014197634A (ja) * 2013-03-29 2014-10-16 新電元工業株式会社 リードフレーム、半導体装置及びその製造方法
JP2015060916A (ja) * 2013-09-18 2015-03-30 セイコーインスツル株式会社 半導体装置
JP2016213505A (ja) * 2016-09-07 2016-12-15 日亜化学工業株式会社 発光装置用パッケージ成形体及びそれを用いた発光装置
US10163829B2 (en) 2017-02-20 2018-12-25 Murata Manufacturing Co., Ltd. Compound semiconductor substrate and power amplifier module

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