JPH04160563A - Address designating device - Google Patents

Abstract

PURPOSE:To shorten the processing time required for bit reverse by alternatively selecting straight address designation and inverse conversion address designation where the arrangement of prescribed bits of the address is reversed to write or read data. CONSTITUTION:Address lines AO to An-1 are connected to address lines BO to Bn-1 by a control signal USEL of straight address designation from a processor 2. Data is transferred to the processor 2 from a memory 1 through a data bus 3 by this address and is read out and is subjected to FFT (fast Fourier transform) processing by the processor 2, and address lines An-1 to AO are connected to address lines BO to Bn-1 by the control signal USEL of inverse conversion address designation from the processor 2, and the FFT processing result is transferred from the processor 2 to the memory 1 through the data bus 3 by the converted address and is written. Therefore, bit reverse in the FFT algorithm is executed, and its processing in the processor 2 is unnecessary. Thus, the processing time of bit reverse is shortened.

Description

[Detailed Description of the Invention] [Summary] The present invention is an addressing device that can alternatively select between straight addressing and reverse conversion addressing, and
FT (Fast Fourier Transfer
m) The bit reverse processing in process (1) is not necessary, and the speed of FFT processing can be increased.

[Industrial application field]

The present invention relates to addressing devices necessary for writing or reading data to or from memory.

In particular, the present invention refers to an improvement in an addressing device that speeds up FFT processing used in various applications based on observation of frequency components.

[Conventional technology]

FIG. 4 is a diagram showing a conventional addressing device. Note that similar components are represented by the same symbols or symbols throughout the drawings. First, the configuration of this figure is shown. This diagram shows a memory 1 that stores data, a processor 2 that processes the data, a data bus 3 that exchanges data between the memory 1 and the processor 2, and a data bus 3 that writes or receives data to the memory 1. and an address bus 4 for specifying an address for reading.

Next, FFT (Fas
tFourier Transform) processing will be explained.

In the FFT algorithm, it is necessary to exchange data using the IJ berth at some point before or after FFT processing. When performing FFT processing on 2” data,
The address that specifies this data is 1] bit, and any address a is set as a=(ao).

al+ a2+ ”' + ah-2+ an-1)2
, where a, , :Q or 1 represents a binary number.

FIG. 5 is a diagram showing a standard FFT signal flow. This figure shows FFT processing of 8 points, or 23 data, as parameters in the frequency domain. In this case, bit reversal is required before FFT processing. Here x (QCx (1),...
x(7) represents the time domain signal, X(0),
(1),...X(7) represent signals in the frequency domain.

Bit reverse refers to the addresses 0, 1, 2, 3, 4, 5.6 for the above 8 points in Figure 6, that is, 000.001 expressed in binary numbers. O], 0.011.100.1
01. .

110, 111 as address 0.4, 2, 6.1, 5.3
゜7 or 000.100.010 expressed in binary.
110°001, IOL 111 This means that if the order of the bits in the former is reversed during conversion, the latter is obtained.

Therefore, in general, in FFT processing, the address is a ``'
(aO+ aI+ a2+ ”' + a, -2+
al, -1) as a'=(ah-1+ an-2+ '''
+ a2+ al+ aO) is required.

FIG. 6 is a diagram showing the procedure of IJ birth.

First, set ordinal number i=Q (step 1). It is necessary to determine whether this 1 is smaller than the predetermined number of points (step 2), and if it is smaller, address A-1,
On the other hand, bit reversed “r dress B =re
Set v(i) (step 3). Determine address A by address B (step 4), and if this relationship is satisfied, the data at address A and the data at address B are exchanged (step 5).

If address A>address B, no exchange is performed. This is to prevent it from returning to its original state. Increment the ordinal number by 1 and repeat the above operation to perform bit reparsing.

[Problem to be solved by the invention]

However, in the conventional addressing device, it is necessary to perform an IJ berth to convert the address before or after the FFT processing every time the FFT processing is performed, so there is a problem that this processing takes a long time.

SUMMARY OF THE INVENTION Therefore, it is an object of the present invention to provide an addressing device that can shorten the processing time required for PIP/IJ berths.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention has two methods: straight addressing, in which data is written to or read from memory while leaving the bit arrangement of the atto I/S as is; Choose between reverse conversion address specification for writing or reading.
A selective addressing device is provided.

[For production]

According to the addressing device of the invention, each address line A is controlled by a straight addressing control signal USEL from the processor 2. ,A, ,A2. ...1A+'+
-2+ A, -1 is address line B. ,B,,B2.・
....

B l'lJ1 Bh-, respectively, and the memory 1 is connected to the processor 2 by the data bus 3 at this address.
The data is transferred and read from F
After the FT processing, each address line Ah-,
, Al1-2+ +++ , A2. A1. AQ is address line BOI BI+ 821-I B11-21
Bn-1 respectively, and F with the translated address.
The FT processing result is transferred from the processor 2 to the memory 1 via the data bus 3 and written therein. Therefore, bit reversal in the FFT algorithm is executed, and this processing in the processor 2 is unnecessary. Also, contrary to the above, when reading from memory 1, specify the reverse conversion address and perform FFT.
It is also possible to write to the memory 1 by specifying a straight address after processing.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an addressing device according to this embodiment. The configuration of this figure will be explained. This diagram shows a memory 1 that stores data, a processor 2 that processes data read from the memory 1 and stores the processed data in the memory 1, and a communication between the memory 1 and the processor 2. A data bus 3 for transferring data, an address bus 4 for specifying the address of data to be transferred for writing or reading by the data bus 3, and a data bus 4 for specifying the address of data to be written or read by the data bus 3, and for writing or reading the data while leaving the bit arrangement of the address unchanged. an addressing device 5 that selectively selects between straight addressing and inverse conversion addressing that writes and reads data by reversing the arrangement of bits according to the bit length of the address; and a control unit 6 that selects between 1 and 2 and reverse translation address designation.

FIG. 2 is a diagram showing the configuration of an addressing device according to an embodiment of the present invention. In this figure, for simplicity of explanation, the number of address lines of the address bus 4 is assumed to be five at maximum. Address a to which data is written from processor 2 is a= (
It can be expressed in binary numbers as ao a, a2 a3 a4). ao-a4 is O or 1 from processor 2 to each address line A; .

It is output to Al1A2+A3+A4.

This figure shows each address line A. and gate circuits 10 and 11 connected to each address line A1 and A4, gate circuits 12 and 13 connected to each address line A1 and A3, and gate circuit 14 and 1 connected to each address line A3 and A1.
5 and each address line A4 and A.

and an OR circuit 30 connected to the outputs of the gate circuits 10 and 11.
An OR circuit 31 connected to the outputs of the gate circuits 12 and 13, an OR circuit 32 connected to the outputs of the gate circuits 14 and 15, and an address on the memory 1 side connected to the outputs of the gate circuits 16 and 17. O output to line B4
R circuit 33, gate circuits 18 and 19 connected to the output of each OR circuit 30 and 32, and gate circuit 20 connected to the output of each OR circuit 31 and address line A2.
and 21, gate circuits 22 and 23 connected to each address line A2 and the output of the OR circuit 31, and each OR
Gate circuit 24 connected to the outputs of circuits 32 and 30
and 25, an OR circuit 34 connected to the outputs of the gate circuits 18 and 19, and the gate circuits 20 and 21.
an OR circuit 35 connected to the output of the memory 1 side and outputs to the address line B1 on the memory 1 side; an OR circuit 36 connected to the outputs of the gate circuits 22 and 23; and an OR circuit 36 connected to the outputs of the gate circuits 24 and 25 An OR circuit 37 that outputs to the side address line B3, gate circuits 26 and 27 connected to the outputs of each OR circuit 34 and 36, and
Gate circuits 28 and 29 connected to circuits 36 and 34, and address line B connected to the outputs of gate circuits 26 and 27 on the memory 1 side. An OR circuit 38 connected to the gate circuits 28 and 29 and output to the address line B2 on the memory 1 side, and each selection signal USELI + USEL2 and USEL 3 from the processor 2 are inverted. (9) includes inverters 41, 42, and 43, and
SELI is a control signal for the gate circuits 10, 12,
14 and 16 manually, and this inversion U S E L l
is input as a control signal to gate circuits 11, 13, 15 and 17, USEL 2 is input as a control signal to gate circuits 18, 20, 22 and 24,
This reversal USI! L2 is input as a control signal to gate circuits 19, 21, 23 and 25, and
E L 3 is used as a control signal for gate circuits 26 and 2.
This inverted USEL3 is input to gate circuits 27 and 29 as a control signal.

Next, the operation of this writing addressing device will be explained. FFT processing in processor 2 is performed using, for example, 32 points as frequency domain parameters, and in order to write this to memory 1 with straight addressing, US
ELI + USEL2 and U, l:L3 as 'H(H
i gh)”. As a result, the gate circuit 10
, 12 , 14 , 16 , 18 , 20 , 22 ,
24, 26 and 28 are in a passing state, and the gate circuits 11, 13, 15, 17°19, 21, 23
, 25, 27 and 29 are cut off, and each address line A on the processor 2 side. ,A, ,A2. A3゜A4
is address line B on the memory 1 side. ,B,,B2. B3゜B
4 respectively. Next, in order to write to memory 1 with reverse conversion address specification under the condition of 32 points, U, 1
．． Set it to ``Directly Low'' and set USEL□, U, and HL3 to H''. Compared to the previous case, U,. Ll is 'L
'', the gate circuits 10゜12, 14 and 16 are cut off, and the gate circuits 11゜13, 1
5 and 17 are in a passing state. For this reason, processor 2
Each address line A on the side 4. A3. A 2+ A +,
A.

is address line B on the memory 1 side. ,B,,B2. B3. B
4 respectively.

Next, in the case of 16 points as a frequency domain parameter, set USELI and USEL3 to "H", and set USELI and USEL3 to "H" when specifying a straight address.In this case, each address line A on the processor 2 side , A + , A 2+ A 3.A 4 are the address lines B on the memory 1 side as described above., B 1 .
B2. B 3. B 4 respectively.

When specifying a reverse translation address, USEL2 is set to "L". As a result, the gate circuits 18°20, 22 and 24 are cut off, and the gate circuits 19°21, 23
and 25 are in a passing state. In this case, each address line A3 on the processor 2 side. A2. AI, AO, and A4 are address lines B on the memory side. , B l, B2+ B3+
Each is connected to B4.

Furthermore, in the case of 8 points as a frequency domain parameter, set USELI and UsEL2 to H''',
USEL when specifying a straight address.

Set to “H”. In this case, each address line A on the processor 2 side. ,A, ,A2. A3; A4 is the address line B on the memory 1 side as described above. , B II B2+ 8
3. Each is connected to B4. When specifying a reverse conversion address, U S E t 3 is set to L''. This causes the gate circuits 26 and 28 to be cut off, and the gate circuits 27 and 29 to be passed. In this case, each address line on the processor 2 side A2.A1.AO, A3+
A4 is address line B on the memory 1 side. ,B11B2+B
3. Each is connected to B4. The address line is 5 or more.
Although the case of books has been described, the present invention is not limited to this.

Next, a series of operations of this embodiment will be explained. FIG. 3 is a flowchart (I2) of a series of operations in this embodiment. First, specify the number of points from the control unit 6 and
t-"H'" to set the straight addressing mode (step 1). As a result, the data is transferred from the memory 1 to the inside of the processor 2 via the data bus 3 with the bit arrangement unchanged (step 2). FFT processing is performed using this data (step 3). When the processing is completed, the processor 2 sends a US signal to the addressing device 5.
EL=“L” is sent and the inverse translation addressing mode is entered (step 4). The data is transferred from inside the processor 2 to the reversely converted address in the memory 1.

Note that it is also possible to read data from the memory 1 in reverse conversion addressing mode before FFT processing, and then write the processed data to memory 1 in straight addressing mode after FFT processing.

〔Effect of the invention〕

As explained above, according to the present invention, it is now possible to select between straight addressing and inverse conversion addressing, which eliminates the need for bit reverse processing in FFT processing, making it possible to speed up FFT processing. can.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the addressing device according to the present embodiment, FIG. 2 is a diagram showing the configuration of the addressing device according to the embodiment of the present invention, and FIG. 3 is a flowchart of a series of operations according to the present embodiment. , FIG. 4 is a diagram showing a conventional computer addressing device, FIG. 5 is a diagram showing a standard FFT signal flow, and FIG. 6 is a diagram showing a bit reversal procedure. In the figure, ■...Memory, 2...Processor,
3...Data bus, 4...Address bus, 5...Addressing device. FIG. 1 shows a response designation device according to this embodiment.FIG. 5 shows a conventional computer addressing device.
4. Flowchart of a series of operations in this embodiment Xo(K
) XI(K) X2(K) x3(K
) (a) Bitverse standard FFT after FFT processing 1 1 ×. (K) x, (K) X2 (K)
x3(K)(b) Figure 5 showing the bitverse language flow before F'FT processing

Claims (1)

[Claims] 1. Comprising a memory (1) for storing data and a processor (2) for processing the data, and writing and reading the data by specifying an address in the memory (1). In a computer addressing device, there are two types of addressing: straight addressing, in which the data is written or read while the bit arrangement of the address remains unchanged, and inverse conversion addressing, in which the data is written or read by reversing the arrangement of predetermined bits of the address. 1. An addressing device characterized by selectively selecting a designation.