JPH01109474A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To shorten a processing time by using a dual port RAM, which can parallely set a writing address and a reading address and simultaneously executing the operation processing of data from the set reading address and a shift processing. CONSTITUTION:The reading address is inputted to a reading address port RA of a dual port RAM1 and the read data are supplied to an operating part 2. Then, the operation processing of the data is executed and simultaneously, the data are inputted from an input port W and written to an address which is inputted from a writing address port WA. Then, the shift processing is executed. Thus, the operating step number of the operating part 2 is decreased and the processing time can be shortened. Processing quantity can be widely improved.

Description

TECHNICAL FIELD The present invention relates to a digital signal processing circuit, and more particularly to a circuit that performs shift processing and arithmetic processing such as a transversal filter.

Prior Art Conventionally, in a digital signal processing circuit, as shown in FIG. 3, an input/output data port W/R and a port W/RA for specifying a write address and a read address are physically the same. A random access memory (hereinafter referred to as RAM) 6 was used. This R.A.
The transfer address and read address to M6 are specified via the address bus 106, the input/output data port W/R of RAM6 is connected to the data bus 105, and data input and output to the calculation unit 2 are performed using the same data. The configuration was such that it was performed via the bus 105.

In such conventional digital signal processing circuits, when applied to a transversal filter that is often used in digital signal processing and performs shift processing and arithmetic processing, as shown in Figure 2 (this transversal filter (in the case where the shift processing is performed in the RAM 6 in FIG. 3 and the arithmetic processing is performed in the arithmetic unit 2), the arithmetic processing that reads data from the transversal filter shift register 4-n and performs 'am'; This data is transferred to the next shift register 4-(n-
1) and the shift process for moving to 1) are processed separately, resulting in an increase in the number of steps in arithmetic processing and an increase in processing time.

1. The present invention was made to eliminate the drawbacks of the conventional ones as described above, and is a digital signal processing circuit that can reduce the number of steps in *i processing and shorten the processing time. For the purpose of providing.

1. Digital signal processing according to the present invention! l! The circuit is a digital signal processing circuit that performs shift processing and arithmetic processing, and is a random access memory that has a data input port and a data output port, and can set write addresses and read addresses in parallel. By setting the read address in the random access memory, the data outputted from the data output port is supplied to the arithmetic processing unit to perform the arithmetic processing, and at the same time, the data output from the m memory is set in the random access memory. The present invention is characterized in that the data is input from the data input port and the shift processing is performed by setting an address.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a digital signal processing circuit according to an embodiment of the present invention is composed of a dual port RAMI, an arithmetic unit 2, and a selector 3.

Write data from the selector 3 is input to the data input port W of the dual port RAM 1, and written to the address specified by the write address 102 input from the write address port W.

Further, from the data output port R of the dual port RAMI, data read from the address specified by the read address 1G3 inputted from the read address port RA is output onto the data bus 104. The data output from this data output port R is sent to the calculation unit 2 and the selector 3.
is input.

The arithmetic unit 2 performs arithmetic processing on data from the dual port RAM 1. Further, the selector 3 selects one of the external input signal 101 and the data inputted from the dual port RAM 1 via the data bus 104, and outputs the selected data to the dual port RAM 1 as combined data.

A case in which the digital signal processing circuit configured as described above is applied to a transversal filter as shown in FIG. 2 will be described below.

Shift register 4-i of this transversal filter
Shift by (i-1, 2,..., n-1, n)! l
! Ill! is performed in a dual-port RAMI. Here, it is assumed that the data held in each shift register 4-i is stored in the dual port RAM 1.

First, the address corresponding to the shift register 4-1 is input to the read address port RA of the dual port RAMI, and the data of the shift register 4-1 is read from that address and input to the arithmetic unit 2. The calculation unit 2 performs calculations on the data and stores it in an internal memory (not shown) of the calculation unit 2.

When performing shift processing and arithmetic processing of data in the shift register 4-2 next to the shift register 4-1, input the address corresponding to the shift register 4-2 to the read address port RA of the dual port RAM 1, The address corresponding to the shift register 4-1 is input to the polished address port WA, and the selector 3 selects the data output from the dual baud RAMI.

That is, the data of the shift register 4-2 is stored in the address where the data of the shift register 4-1 was stored in the dual port RAMI, and the data of the shift register 4-2 is operated in the performance section 2. The calculation result is stored in internal memory.

By repeating the above process, shift register 4-n
Shift processing and arithmetic processing up to the data are performed simultaneously and in parallel.

In this way, by inputting a read address to the read address port RA of the dual port RAM 1, the read data is supplied to the arithmetic unit 2 to perform arithmetic processing on the data, and at the same time, the data is sent to the data input port W. By performing shift processing by inputting data from the address port WA and writing to the address input from the write address port WA, the number of calculation steps of the calculation unit 2 can be reduced and the processing time can be shortened.

Additionally, this makes it possible to significantly improve the throughput.

L! As explained above, according to the present invention, a RAM having a data input port and a data output port and in which a write address and a read address can be set in parallel is used to read data from a set read address. By performing data operation and shift processing at the same time, the number of steps in arithmetic processing can be reduced and the processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing a 1-lance universal filter to which the embodiment of the present invention is applied, and FIG. 3 is a block diagram showing the configuration of a conventional example. FIG. Explanation of symbols of main parts 1...Dual Baud 1-RAM2...
・Calculation section 3...Select

Claims (1)

[Claims] A digital signal processing circuit that performs shift processing and arithmetic processing, and includes a random access memory that has a data input port and a data output port and can set a write address and a read address in parallel, By setting the read address in the random access memory, the data output from the data output port is supplied to an arithmetic processing unit to perform the arithmetic processing, and at the same time, the write address is set in the random access memory. A digital signal processing circuit characterized in that the shift processing is performed by inputting the data from the data input port.