JPH06175964A - Data read circuit - Google Patents

Abstract

PURPOSE:To accelerate the read data transfer speed of a data read circuit. CONSTITUTION:This data read circuit which temporarily holds data read out from a data memory and transfers this data in the next step is provided with a data holding circuit 2 which directly reads out and holds data in each of first and following data read steps, a data holding circuit 1 which holds data held in the data holding circuit 2 in the second data read step, and data transfer lines 3 and 4 connected to these data holding circuits 1 and 2 respectively, and data transfer lines 3 and 4 are arbitrarily selected for transfer of data held in data holding circuits 1 and 3.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a data read circuit.

[0002]

2. Description of the Related Art FIG. 2 shows an example of a conventional data read circuit. As shown in FIG. 2, this conventional example is composed of a data holding circuit 6 and data transfer paths 7 and 8 corresponding to the data memory 9 in which data is stored. 1 when reading data from 9
The amount of data read from the data memory 9 at one time and the amount of transfer of the data are limited to be the same. For example, when the data width is 8 bits, in order to transfer 16-bit data, first data is read from the data memory 9 and held in the data holding circuit 6. Next, the upper 8 bits of data are transferred using the data transfer path 7. Next, the second data is read from the data memory 9 and held in the data holding circuit 6. Then, using the data transfer path 8, the lower 8 bits of data are transferred.

[0003]

In the above-mentioned conventional data read circuit, the data width is 8 as described above.
When reading and transferring 16-bit data in bits, it is necessary to repeat the data reading and the data transfer twice. Therefore, there is a drawback that the read data transfer rate is slow, that is, the read of the data and the transfer of the data must be repeated because the width of the data to be read is large.

[0004]

SUMMARY OF THE INVENTION A data read circuit of the present invention is a data read circuit which temporarily holds data read from a predetermined data memory and which functions to transfer the data in the next step. , A first data holding circuit that directly reads and holds data from the data memory in each data reading step, including the first data reading step, and n (n
= 2, 3, ..., N) In the data reading step, the nth data holding circuit holds the data held in the (n-1) th data holding circuit, and the N data holding circuits. And N data transfer paths each connected to the circuit, and arbitrarily selecting the N data transfer paths for transferring the data held in the N data holding circuits. It is characterized by being able to.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. As shown in FIG. 1, this embodiment
Corresponding to memory 5, data holding circuits 1 and 2 and data transfer paths 3 and 4 are provided. In FIG. 1, the data holding circuit 1 always holds the data immediately preceding the data holding circuit 2. When the first data read from the data memory 5 is performed, the read data is first held in the data holding circuit 2. Next, when the second data read is performed, the data read first is transferred to the data holding circuit 1 and held, and the data read second is held in the data holding circuit 2. After that, the data transfer paths 3 and 4 are simultaneously used to perform data transfer, and the above-mentioned first read data and second read data are simultaneously transferred through the data transfer paths 3 and 4, respectively. To be done.

[0007]

As described above, according to the present invention, when the data read from the data memory for the second time is performed, a data holding circuit for holding the data read for the first time is added to the data memory. There is an effect that it is possible to improve the transfer speed of the read data from, and this effect becomes more remarkable as the data width increases.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

[Explanation of symbols]

 1, 2, 6 Data holding circuit 3, 4, 7, 8 Data transfer path 5, 9 Data memory

Claims (1)

[Claims] 1. A data read circuit which functions to hold data read from a predetermined data memory and transfer the data in the next step, starting from the first data read step. In each data reading step, a first data holding circuit that directly reads and holds data from the data memory, and in the nth (n = 2, 3, ..., N) data reading step, -1) An nth data holding circuit for holding the data held in the data holding circuit, and N data transfer paths respectively connected to the N data holding circuits, The data reading is characterized in that N data transfer paths can be arbitrarily selected for transferring the data held in the N data holding circuits. Circuits.