JPS62226360A - Data converting circuit - Google Patents

Abstract

PURPOSE:To enhance the throughput of a system by halving the time of possession of a system bus at the time of data transfer. CONSTITUTION:At the time of outputting odd number-th data, clock is inputted to a latch 4 by gating the output of AD0 and the inverse of WRITE signal with an AND circuit 10 and data are held. At the time of outputting even number-th data, the output of AD0 inverted by an NOT circuit 9 and the inverse of WRITE signals are gated with an AND circuit 12 to make it the inverse of WRITE signal to a memory, and held temporarily in a control buffer 13. The inverse of HOLDREQ signal is sent to a CPU15, and after the inverse of HOLDACK signal which is an answer signal, becomes low level, the inverse of WRITE signal to a memory held by the control buffer 13 and 16-bit data held by a bus buffer 7 are outputted on a system but 3.

Description

[Detailed Description of the Invention] The present invention relates to data transfer between digital information processing devices,
More specifically, the present invention relates to data transfer when devices connected to each other have different numbers of processing bits.

Processing pin 1 - Data transfer between different numbers of information processing devices 1
For example, when using an 8-bit LSI and transferring data from a processing circuit to a memory or the like via a 16-bit wide system bus, conventionally 8-bit transfer was performed depending on the processing circuit. In this case, even though the system bus is capable of 16-bit transfers, 8-bit transfers are performed, resulting in poor utilization of the system bus, and if the amount of data is large, the system bus may be used for a long time. During this time, no other processing using the system bus could be performed.

Therefore, a data transfer method is known in which the transferred 8-bit data is temporarily held, and then output when it is compiled into 16-bit transfer data that matches the bus width.

However, with this method, the system bus occupation time is halved.
However, since the control is such that the processing circuit outputs the WRITE signal after confirming that two units of transfer data, that is, 16 bits, have been retained, each time data conversion is performed, This has the drawback that the number of WRITE signals of the processing circuit increases by one compared to the case of 8-bit transfer, and the time required for data transfer becomes longer.

The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and provides a data conversion circuit that can extend the data transfer time, and also reduce the system bus occupation time during data transfer. The purpose is to

In order to achieve the above object, the present invention is characterized in that the input/output signals of the conventional processing circuit are utilized as they are.

The present invention will be specifically explained below based on Examples.

The figure shows the data conversion circuit of the present invention applied between the processing circuit and the system bus when inputting and outputting data from the 8-bit processing circuit to the memory via the 16-bit system bus.

The configuration of the embodiment will be described with reference to the drawings.

A processing circuit (2) that can become a bus master and a system bus (
On the data bus between 3), there is a latch (
4) and an internal bus (6) for passing the data output for even numbers, which latches the odd numbers of the continuous 8-bit 11th data group output from the processing circuit (2). (4) Hold 1. By passing the even numbered data through the internal bus (6), it is combined into a path buffer (7) as 16-bit data and output onto the system bus (3).

Also, an internal bus (6) that passes the upper 8 bits of the 16-bit data when inputting data from the system bus (3) to the processing circuit (2) (also serves as the internal bus that passes the data output in the case of an even number). A latch (5) is provided to temporarily hold the lower 8-bit data, which is 16 bits.
The data fetched from the system bus (3) is separated into upper 8 bits and lower 8 bits by the bus buffer (8), and the upper 8 bits are input directly to the processing circuit (2) via the internal bus (6), and the lower After the 8 bits are temporarily held in the latch (5), they are input to the processing circuit (2).

In this configuration, data is first output from the processing circuit.
The operation when writing to the memory (14) will be explained.

The address when outputting the first data is 00...
......00'', and the second is 00...
・・・・・・・・・01・', :lth is 00...
...10" (hereinafter omitted), the output of the address signal output line ADO is 0°L, O, t... (hereinafter 1+)
13) is repeated. Using this, when outputting odd-numbered data, the output of the ADO and the WRITE signal are
By gated with the ND circuit (10), the latch (
4) Input the clock and hold the data. Also, when outputting data for even numbered slots, the output of the above ADO is NOT
Invert with circuit (9) and place WRI! The number is AN
W to the memory is gated by the D circuit (12).
RITE signal and send it to the control buffer (13).
Hold the barb. When using the system bus, the processing circuit (2) needs to become the bus master. This request is HO
The LDREQ signal is sent to the CPTJ (15), and after the response signal HOLDACK signal becomes low level, the WRITE signal to the memory held in the control buffer (13) and the path buffer (7) are sent. The 16-bit data held in the system bus (3) is outputted to the system bus (3).

By the way, in the above data conversion, if the 8-bit data group output from the processing circuit is an even number, it is sufficient to transfer it as 16 bits for each 2111th place, but if it is an odd number, the last 8-bit data is latched (4 ) and end up leaving. This process will be described below.

The processing circuit (2) switches to C when all data transfer is completed.
It interrupts the PU (15), transfers it, and informs it of the number of 8-bit data groups. Cp TJ (15) transfers, and if the number of 8-bit data groups is odd, latches (
4) determines that data remains in 1, outputs a READ signal to the data conversion circuit (1), and 1. Latch (4)
By setting the path buffer (7) to one novel, the remaining 8 bits of data are read out and stored in a predetermined location in the memory.

Next, the operation when inputting data from the system bus (3) to the processing circuit (2) will be explained.

You can think of this in the same way as when outputting data. Processing circuit (2)
Of the READ signals, only the odd-numbered one is output to the memory via the system bus (3), and the data conversion circuit (
1) Load data into. Odd number? The 1[3-bit data transferred by the h-th READ signal is separated into upper 8 bits and lower 8 bits by the bus buffer (8), and the upper 8 bits are directly sent to the processing circuit (2) through the internal bus (6). ). The lower 8 bits are latched (
5), and is taken into the processing circuit (2) using the next READ signal, that is, the output of the even-numbered READ signal.

In this embodiment, data transfer between an 8-bit processing circuit and a 16-bit system bus will be described, but the invention can of course also be applied to a case where the processing circuit is a 16-bit system bus and the system bus is of a 32-bit configuration.

! As is clear from the above description, according to the present invention, the system bus occupation time during data transfer can be reduced to 172 seconds, improving system throughput.

Furthermore, since the data (No. 8) output from the conventional processing circuit is used as is, it is easy to apply the data conversion circuit of the present invention to the conventional system.

4. The first explanatory diagram of the drawings is a block diagram showing the configuration of a system implementing the present invention.

Claims (1)

[Claims] In a data conversion circuit provided for transferring data between devices having different processing bit numbers; Storage means for holding one unit of transfer data; Allowing one unit of transfer data to bypass the storage means A data conversion circuit comprising: a transfer means; and a control means for distributing continuously transferred data to the storage means and the transfer means.