JPS6271084A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable the write from external by providing plural pairs of address temporary holding circuits and data temporary holding circuits. CONSTITUTION:When a write control input signal 5 is inputted, a latch signal 7a is outputted from an internal write control circuit 6 in synchronism with the signal 5, and values of an address input 1 and data input 9 are held in an address temporary holding circuit 2a and a data temporary holding circuit 10a. When the write control input signal 5 rises, a storage circuit write signal 8a having a certain pulse width is outputted, and address information and data information held in the address temporary holding circuit 2a and the data temporary holding circuit 10a are outputted through an internal address bus 4, an internal data bus 12, an internal address signal driver 3a, and an internal data signal driver 11a in synchronism with the signal 8a, and data is written in a prescribed address of a storage circuit 13. Though the write operation from the external is performed when the signal 8a is outputted, values of the address input 1 and the data input 9 at this time are held in another pair of temporary holding circuits, namely, an address temporary holding circuit 2b and a data temporary holding circuit 10b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data saving method for a semiconductor integrated circuit incorporating a memory circuit and a data holding circuit.

[Conventional technology]

The conventional equipment for this building is shown in Figure 3. Figure 3 is a block diagram showing the configuration of a conventional data write-in circuit, in which (1) is an address input from the outside, (2) is an address temporary holding circuit, (3) is an internal address signal driver, and (4) is Internal address bus, (5) is a write control manual signal from the outside, (6) is an internal write control circuit, (7) is a latch signal for the temporary holding circuit, (8) is a memory circuit fill signal, (9) is data input from outside, (l
O) is a data temporary holding circuit, (il) is an internal data signal driver, (12) is an internal data pan 1, and (13) is a storage circuit.

Next, the operation of the conventional circuit will be explained. In Fig. 3, when performing 1 from the input operation, external address input 11), external data input (9, I) gives the address and data of the memory circuit to be loaded 4F, and at the same time inputs the A control input signal i5+ is given, i.e. if the pledge control input signal (5) is negative;
In synchronization with this negative pulse, the address temporary holding circuit (2r1 bitter temporary holding circuit (1
Input external address to 0) (1), external data person crab 9)
A latch signal (7) that latches the is output. When the pulse of the write control input signal (5) changes from negative to positive,
The previous external address input (1), external data input (
9) is held in the temporary address holding circuit (2) and the temporary data holding circuit i15 (10)K.

At this time, the memory circuit write signal (8) with a constant pulse width is output from the write control circuit M161 after the write control input signal (5) rises, and in synchronization with this, the internal address bus (4) and the internal data An internal address signal driver (3) and an internal data signal driver (11) are connected to the bus (12).
), the address information and data information held in the temporary address holding circuit (2) and the temporary data holding circuit (10) are output, and the data is written to a predetermined address of the memory times % (13). FIG. 4 is an operation timing diagram showing the timing of the above operation, where (14) is the input waveform of the write control input signal (5) from the outside, (15) is the address temporary holding circuit (2), and the data temporary holding circuit. Circuit (■0)
(i6) is the input waveform of the address or data written externally, (i6) is the waveform of the latch signal (7) input to
17) shows the waveform of the address or data held by the temporary holding circuit (2) or (lO), and (18) shows the waveform of the memory circuit pledge signal (8) inside the data write circuit. Furthermore, in the conventional data write circuit, when the internal 9-part storage circuit-IN write signal (8) is output, the address temporary holding circuit (2) and the data temporary holding circuit (10
) cannot be changed, so
During this time, the configuration is such that no external write operation is allowed.

[Problem that the invention seeks to solve]

In the conventional data write circuit as described above, when the internal memory circuit write signal is output at V, no external write operation is allowed, so after the external write is completed, the internal write operation is not allowed. There was a problem that the next external write could not be performed until the write operation was completed.

The present invention was made to solve this problem, and aims to obtain data write +o1 that can be written from outside regardless of whether there is redundancy in the internal write operation.

[Means for solving problems]

The data loading circuit according to the present invention is provided with several sets of temporary address holding circuits and temporary data holding circuits.

[Effect]

In this invention, even if an internal nuisance operation is performed by providing a plurality of sets of address temporary holding circuits and data temporary holding circuits, it is possible to perform H input from the outside. can.

[Implementation sequence of the invention]

Embodiments of the invention will now be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention. The same reference numerals as in Figure 3 indicate the same or monk parts, (2a) (2b)
are address temporary holding circuits, (3a) and (3b) respectively.
are internal address signal drivers (7a) and (-7) corresponding to address temporary holding circuits (2a) and (2b), respectively.
b) is a latch signal for each address or data temporary holding circuit, (8a), (8b) is a memory circuit protection signal corresponding to each address or data temporary holding circuit, (10a) , (10
b) are data temporary holding I circuits, (lla), (
llb) are data temporary holding circuits (10a) and (
The internal data signal corresponding to 10b), (19) is the a write signal for the memory circuit L+ (13>),
The OR circuit generated by (8b), (2(') is a write control signal for the memory circuit (13).

Next, the operation of this invention will be explained. In FIG. 1, when writing from the outside is executed, the external address input (1) and external data input (9) are input to the temporary address holding circuit (2) in synchronization with the rising edge of the write control input signal (5).
A value is held in either a) or (2c) and either the data temporary holding circuit (10a) or (LOb). The two sets of address temporary holding circuits and data temporary holding circuits output latch signals (7a) or (7h) every - times by the internal write control circuit (6) so that they are used alternately for external writing. be done. Then, some write operation causes the address or data to be
The operation when data is written to the temporary address holding circuit (2a) and the temporary data holding circuit (10a) will be explained.

, When the write control input signal (5) is input manually, the internal write control circuit (6) outputs the latch signal (7) in synchronization with it.
a) is output, and the - value of the address input +11 data input (9) is held in the address temporary holding circuit m (2a) and the data temporary holding circuit (10a). When the blue control input signal (5) rises, a memory circuit write signal (8a) with a constant pulse width is output, and in synchronization with this, an internal address signal driver is sent to the internal AT1 NOS bus (4) and the internal data bus (12). (3a, internal data signal driver (
The address information held in the address temporary holding circuit (2a), the data temporary holding circuit N (10a), and the 4 data information are outputted via the address temporary holding circuit (1la), and the data is stored at a predetermined address in the d memory circuit (13). Even if an external write operation is performed during the period when this write circuit entry signal (8a) is output, the address input (1) at this time is
), the data input (9) has its value held in another set of temporary holding circuits, namely the temporary address holding circuit (2b) and the temporary data holding circuit (ivb), so it does not affect the write operation to the memory circuit. It never goes away. That is, in the conventional circuit configuration, while the memory circuit write operation was being performed inside the data write circuit, a write operation using an external force was not possible, whereas in the present invention, during that time, a separate address temporary holding circuit , and is controlled to write to the data temporary holding circuit. FIG. 2 is an operation timing diagram showing the operation of the present invention, where the same reference numerals as in FIG. 4 indicate the same or equivalent waveforms, and (J5a) is an address temporary holding circuit (
2a).

Latch signal (7a) of the controller temporary holding circuit (10a)
The waveform (251)') is the address temporary holding circuit (2b
), the latch signal (7b) of the data temporary holding circuit (10b)
), (L7a) is the waveform of the address or data latched by the latch signal (7a), (17b) is the waveform of the address or data latched by the latch signal (7b), and (18a) is the waveform of the address or data latched by the latch signal (7a). ) is the waveform of the signal (8a) for writing the data latched by the latch signal (7b), and (18b) is the waveform of the signal (8b) for writing all the data latched by the latch signal (7b).
) waveform is shown.

Although two address and data temporary holding circuits are used in the above embodiment, the number can be increased to six depending on the degree of input of external write signals.

〔Effect of the invention〕

As explained above, this invention provides a plurality of registers for temporarily holding the data and address values stored in the memory 191 or the data holding circuit.
Even when a write operation is being performed internally, it is possible to write data from the outside, and it is possible to eliminate the time required for writing data from the outside. be.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention; Fig. 2 is an operation timing diagram of the circuit shown in Fig. 1; Fig. 3 is a block diagram showing the RI41 reverse of the conventional data input circuit. , FIG. 4 is an operation timing diagram of the circuit shown in FIG. 3. flj is an external address input signal, (2a), (2
b) are address temporary holding circuits, (3a) and (3
b) are internal address signal drivers, (4) are internal address buses, (5) are write control input signals, and (6) are internal address signal drivers.
) are internal input control circuits, (7a) and (7b3 are latch signals for temporary holding circuits, respectively, (8a) and (8b) are memory circuit write signals, (9) are data input signals, and (10) are Data temporary holding circuit, (ll&), (l
lb) ri each internal data signal driver, (12
) id internal data bus, (13) is a memory circuit, (14)
is the input waveform of the write control input signal (5), ("5&>
, (!5a) are the waveforms of the latch signals for the temporary holding circuit, (16) are the input waveforms of address or data from the outside, and C17&)? (17b) is the waveform of No. 16 held in the temporary holding circuit, (m8a), (18b)
are the write waveforms to the memory circuit, and (19) is the OR
circuit, (20) is a memory circuit write signal. Note that 1o and i- symbols in each figure indicate the same or equivalent parts. No. 4 Engineering ↓ Former 4-man Juji t1 Yumo Diagram 4 Procedure Amendment (Voluntary) January 22nd, 1988

Claims (1)

[Claims] A temporary address holding circuit and a temporary data holding circuit that input address and data input signals from the outside and temporarily hold them, and a memory circuit that receives data held in the temporary data holding circuit by signals from the outside. In a semiconductor integrated circuit having an internal write control circuit for writing to an address position held in a temporary address holding circuit,
A plurality of sets of temporary address holding circuits and temporary data holding circuits are provided, and when an internal write is being performed to the storage circuit according to the contents of one set of the temporary address holding circuit and data temporary holding circuit, another write is instructed from the outside. When addresses and data are input, input from the outside to addresses that temporarily hold addresses and data for the above-mentioned internal writing to address temporary holding circuits and data temporary holding circuits other than the time holding circuit and data temporary holding circuit. temporarily holding addresses and data, and sequentially outputting the values temporarily held in the plurality of address temporary holding circuits and data temporary holding circuits to the storage circuit, and writing data to the storage circuit. A semiconductor integrated circuit characterized by: