JPH04195889A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To eliminate the need of making external pointer signals at the time of data transfer cycle and supplying them from outside by executing the data transfer cycle, transferring only read data, and setting a data transfer cycle after a successive read cycle. CONSTITUTION:This device is so structured that a control signal-WE to be inputted from outside is added to a transfer control circuit 11, and internal transfer gate control signals are divided to give independence to pointer transfer gate control signals phiGA and data transfer gate control signals phiGD to respectively input to a pointer transfer circuit 4 and data transfer circuit 6. And, when the control signals -RAS, -WE, and -OE are all in activated state, only the data transfer circuit 6 is activated to allow only the read data to be transferred, and a data transfer cycle is set after a successive read cycle. Thus, the successive read cycle that uses the newly transferred read data is made to start, and the need to supply the external pointer signals from outside at the time of the output transfer cycle is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory device used for both general purpose and image processing purposes.

[Prior Art] In recent years, semiconductor memory has become more and more popular and faster, and the field of application of the product has also expanded, and it has also been used for image processing, or as one form of it. There are semiconductor memory devices that add circuits to general-purpose semiconductor memory devices and serve both general-purpose and image processing purposes.

FIG. 5 is a block diagram showing a conventional example of this type of semiconductor memory device, and FIG. 6 shows a pointer transfer circuit 4 and a data transfer circuit 6 of the conventional example of FIG. The figure is number 5
FIG. 8 is a timing diagram showing the operation of the conventional example shown in FIG. 5. FIG. 8 is a circuit diagram of a specific example of IA. Here, to simplify the explanation, a tuffle strobe type semiconductor memory device in which two externally applied activation control signals, RAS and CAS, are used will be taken as an example.

This semiconductor memory device includes a cell matrix 1 which is a collection of memory cells, an address buffer circuit 2, an address code circuit 3, a pointer transfer circuit 4, a pointer count circuit 5, a data transfer circuit 6, and a register. A line buffer circuit 7, which is a set of
, an output buffer circuit 9, a control circuit 1o, and a transfer control circuit 11A, and has an address signal input terminal A1N and a pointer control signal input terminal S as signal input/output terminals.
C, data output terminal SO and control signal input terminal RAS
, CAS, WE and POS.

Next, the operation of this conventional example will be explained with reference to FIGS. 5 and 6.

In the transfer cycle, a row address signal applied from the outside to the address signal input terminal A11 is amplified in the address buffer circuit 2, and is then decoded as an internal address signal No. 3 AX. It is input into cell matrix 1 as . At the same time, external address signal input terminal A. . Cell matrix 1 is manually operated. Read data D from the memory cells of the row selected by the row selection signal X is transferred via the data transfer circuit 6 to a register in the line buffer circuit 7 as transfer data D1. Here, the number of register circuits is equal to the maximum number of addresses that the external pointer signal has, and each register has an address corresponding to the address indicated by the external pointer signal. - On the other hand, the internal column address signal AY is passed through the pointer transfer circuit 4 as the transfer column address signal AY to the pointer count circuit 5.
will be forwarded to. In pointer count circuit 5, transfer column address signal A7. is converted into an internal address pointer signal AP synchronized with a pointer control signal applied from the outside to the pointer control signal input terminal SC, and inputted to the data selection circuit 8. After the internal address pointer signal AP is decoded in the data select circuit 8, it is converted into a data register selection signal S, and is input to the line buffer circuit 7, which selects the register at the address indicated by the external pointer as the first register. This causes a transfer cycle to be executed.

In the sequential read cycle following the transfer cycle, the transfer data D1 of the first register selected in the transfer cycle is
is amplified by the output buffer circuit 9, and then outputted to the data output terminal S○ in synchronization with a pointer control signal applied from the outside to the pointer control signal input terminal SC. In the next sequential read cycle, the register at the address next to the register selected in the previous sequential read cycle is selected and the transfer data D1 is amplified by the output buffer circuit 9, and the pointer control signal input terminal SC is input from the outside. is output to the data output terminal SO in synchronization with the pointer control signal applied to the pointer control signal. Until the sequential read cycle is set as the next transfer cycle, the pointer control signal input terminal SC is input from the outside.
It is executed repeatedly in synchronization with the pointer control signal applied to the pointer control signal. In a transfer cycle, the transfer control circuit 11A generates an internal transfer gate control signal φ6 based on a control signal including a transfer command applied from the outside to the control signal input terminals RAS and OE, and outputs an internal transfer gate control signal φ6 between the pointer transfer circuit 4 and the data transfer circuit 6. The transfer of internal column address signal AY and read data D is controlled by activating or deactivating AY within the same cycle. Here, in FIG. 5, the control signal from the control circuit 10 is omitted, or the control circuit 10 is connected to the control signal input terminals RAS, CAS, WE and O
The entire apparatus is controlled so that general-purpose and image processing operations are performed without any equipment based on control signals including write and read commands applied externally to E.

[Problems to be Solved by the Invention] A conventional dual semiconductor memory device does not maintain the continuity of registers while executing a sequential read cycle; When attempting to use , a transfer cycle must be executed, and since the internal column address signal AY and read data D are transferred within the same cycle, the register selected in the next successive read cycle must be transferred. Since it is necessary to create an external pointer signal having address information in advance and apply it to the address signal input terminal from the outside during a transfer cycle, there is a drawback that the timing of use for the semiconductor memory device becomes complicated.

An object of the present invention is to create an external pointer signal having the address information of a register to be selected in the next successive read cycle so that there is no need to supply it to an address signal input terminal from the outside during a data transfer cycle, and to use the signal in a semiconductor memory device. It is an object of the present invention to provide a semiconductor memory device whose timing can be easily set.

[Means to solve BB] The semiconductor memory device according to the present invention includes: A cell matrix is a collection of memory cells.

Amplify the row address signal and column address signal input to the address signal input terminal, pointer control signal input terminal, data output terminal, control signal input terminals such as RAS, CAS, WE, OE, etc. and fidget internal row address signal,
An address buffer circuit that outputs an internal column address signal, and an atrestecoat circuit that Tecotes the internal row address signal and internal column address signal output from the address buffer circuit and outputs them to the cell matrix as a row selection signal and a column selection signal, respectively. , a data transfer circuit, a pointer transfer circuit, and an internal column address signal is transferred as a transfer column address signal via the pointer transfer circuit, and the transfer column address signal is synchronized with a pointer control signal from a pointer control signal input terminal. A pointer count circuit that converts it into an internal address pointer signal and outputs it, a data select circuit that decodes the internal address pointer signal and converts it into a data register selection signal, an output buffer circuit, and a pointer count circuit that converts it into an internal address pointer signal and outputs it. Consisting of registers, each register has an address corresponding to the address indicated by the column address signal, and read data from one row of memory cells not selected by the row selection signal is transferred to the register via a data transfer circuit, A pointer transfer cycle is executed by selecting the register at the address indicated by the internal address pointer as the first register, and in the sequential read cycle following the transfer cycle, the data of the first register selected in the pointer transfer cycle is output to the buffer circuit. The data of the register at the next address selected by the previous sequential read cycle is output to the motor output terminal in synchronization with the pointer control signal via the output buffer until the next pointer transfer cycle is set. A line buffer circuit that returns sequential read cycles to the motor output terminal in synchronization with the pointer control signal through the circuit;
When the control signals '1' of , WE, and OE are all activated, only the data transfer gate control signal is output, the data transfer circuit is activated, and the RAS is activated.

When the control signals of OE are both activated and W's control No. 45 is inactivated, the pointer transfer control signal and data transfer control signal are output, and the pointer transfer circuit and data transfer circuit transfer control circuit that activates RAS, CAS, WE, and O from the control signal input terminal.
E control (based on No. 3, it has a control circuit that controls the entire device).

[Operations] The difference between the present invention and the conventional example is that a control signal WE manually input from the outside is added to the transfer control circuit, and the internal transfer gate control signal φ6 is further divided into a pointer transfer gate control signal φGA and a data transfer gate control signal. -1・Control signal φ. 0 independently,
The pointer transfer gate control signal φ6A is input to the pointer transfer circuit, and the data transfer gate control signal φ6A is input to the pointer transfer circuit. 0 is configured to manually input data to the data transfer circuit. And R.A.S.
When the WE and OE control signals are both activated, only the data transfer circuit is activated and the register selected in the previous sequential read cycle is held in the selected state, while the pointer transfer gate control signal φ is activated. 6 remains inactive, allowing transfer of only successive data. By setting a data transfer cycle after a sequential read cycle, a sequential read cycle using newly transferred read data starts. can.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the first embodiment. In this embodiment, parts corresponding to those in FIG. 5 are given the same reference numerals.

The difference between this embodiment and the conventional example shown in FIG. 5 is that the transfer control circuit 1
A control signal WE manually input from the outside is added to No. 1, and an internal transfer gate control signal φ6 is further divided into a pointer transfer gate control signal φ6A and a data transfer gate control signal No. 3 φ.
Independently of GD, the pointer transfer gate control signal φGA is input to the pointer transfer circuit 4, and the data transfer gate control signal φ64. is configured to be input to the data transfer circuit 6.

In the data transfer cycle shown in FIG. 2, at the time when a signal applied from the outside to the control signal input terminal RAS changes from high potential to low potential, the control signal input terminals WE and O
Only when both external signals applied to E are low potential,
The data transfer gate control signal φ6o becomes a high potential one-shot signal and activates the data transfer circuit 6. on the other hand,
Since the pointer transfer gate control signal φ6A maintains a low potential, the register selected in the immediately preceding sequential read cycle maintains its selected state, and only read data D can be transferred. Therefore, the data transfer cycle is started after the sequential read cycle. By setting, a sequential read cycle using newly transferred read data D can be started. Also,
At the time when a signal applied from the outside to the control signal input terminal RAS changes from high potential to low potential, the control signal input terminal O
Signal applied from outside to E or low potential, control signal input terminal W
If the signal applied to is at a high potential, pointer transfer gate control signal φcr & theta transfer gate control signal φGD
Both become high-potential one-shot signals, and both the pointer transfer circuit 4 and the data transfer circuit 6 are activated.
As in the conventional transfer cycle, internal column address No. 15 AY and read data D are transferred.

FIG. 3 shows the first transfer control circuit 11 of the embodiment shown in FIG.
FIG. 2 is a logic circuit diagram of a specific example.

It is clear that the pointer transfer gate control signal φ6A and the data transfer gate control signal φGD can be realized by the external control signals in the timing diagram of FIG.

FIG. 4 shows the second transfer control circuit 11 of the embodiment shown in FIG.
FIG. 2 is a logic circuit diagram showing a specific example.

The difference from the first specific example is that in the first specific example, the control signal input terminal WE was manually operated by a buffer, whereas in the second specific example, it is an inverter.

In the second specific example, at the time when the signal applied from the outside to the control signal input terminal RAS changes from high potential to low potential, the signal applied from the outside to the control signal input terminal OE is low potential,
If the signal applied from the outside to the control signal input terminal WE is at a high potential, it becomes a pointer transfer cycle, but if the signal applied from the outside to the control signal input terminal WE is at a low potential, it becomes a transfer cycle as in the conventional example. It is.

For simplicity of explanation, both the conventional example and the embodiment are implemented using a tuple strobe type semiconductor memory device in which two activation control signals, RAS and CAS, are applied from the outside. However, it is obvious that the scope of the present invention falls within the scope of the present invention, as long as the transfer control circuit includes additional control means for controlling only the data transfer circuit.

[Effects of the Invention] As explained above, in the present invention, by executing a data transfer cycle, only read data is transferred. There is no need to create an external pointer signal with the address information of the register selected in the sequential read cycle and apply it to the address signal input terminal from the outside during the data transfer cycle, making it easier to set the usage timing for the semiconductor memory device. There is.

[Brief explanation of the drawing]

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of the embodiment of FIG. 1, and FIG. 3 is a transfer control circuit of the embodiment of FIG. 1. 11 is a logic circuit diagram showing a first specific example, FIG. 4 is a logic circuit diagram showing a second specific example, FIG. 5 is a block diagram showing a conventional example of a semiconductor memory device, and FIG. 7 is a circuit diagram of a specific example of the transfer control circuit 11A of the conventional example shown in FIG. 5, and FIG. FIG. 3 is a timing diagram showing an example operation. 1...Cell matrix 2...Address buffer circuit 3...Atreste code circuit 4...Pointer transfer circuit 5...Pointer count circuit 6...Theta transfer circuit 7...Line buffer circuit 8 ...Data select circuit 9...Output buffer circuit 10...Control circuit 11) IIA...Transfer control circuit A, N...To address signal input terminal〇...Internal row address signal AY...・Internal column address signal・Data register selection signal PAS, CAS, OE, WE-- Control signal input terminal SC... Pointer control input terminal SO... Data output terminal φG... Internal transfer gate control signal φ6A... Pointer transfer gate Control signal φ6D・-・
Theta Transfer Case 1/Control Signal Patent Applicant: NEC IG Microcomputer Systems Co., Ltd.

Claims (1)

[Claims] 1) A cell matrix that is a collection of memory cells, an address signal input terminal, a pointer control signal input terminal, a data output terminal, and control signal input terminals such as ■, ■, ■, ■, etc. The row address signal and column address signal input to the address signal input terminal are amplified, and the internal row address signal and internal row address signal are respectively output.
An address buffer circuit that outputs an internal column address signal, and an address decode circuit that decodes the internal row address signal and internal column address signal output from the address buffer circuit and outputs them to the cell matrix as a row selection signal and a column selection signal, respectively. A zeta transfer circuit, a pointer transfer circuit, and an internal column address signal that is transferred as a transfer column address signal via the pointer transfer circuit and that synchronizes the transfer column address signal with a pointer control signal from a pointer control signal input terminal. A pointer count circuit that converts it into a pointer signal and outputs it, a data select circuit that decodes the internal address pointer signal and converts it into a zeta register selection signal, an output buffer circuit, and a register with the maximum number of addresses that the column address signal has. Each register has an address corresponding to the address indicated by the column address signal, and the read zeta from one row of memory cells selected by the row selection signal is transferred to the register via the zeta transfer circuit, and the internal address is transferred to the register via the zeta transfer circuit. A pointer transfer cycle is executed by selecting the register at the address indicated by the pointer as the first register, and in the sequential read cycle following the transfer cycle, the data in the first register selected in the pointer transfer cycle is transferred via the output buffer circuit. The data is output to the data output terminal in synchronization with the pointer control signal, and thereafter, the data in the register at the next address selected in the previous sequential read cycle is passed through the output buffer circuit until the next pointer transfer cycle is set. A line buffer circuit that repeats a sequential read cycle that is output to a data output terminal in synchronization with a pointer control signal, and a line buffer circuit that outputs only a data transfer gate control signal when all of the control signals ①, ②, and ② are activated; Activate the data transfer circuit, and control signals ■ and ■ are both activated, ■
A transfer control circuit that outputs a pointer transfer gate control signal and a data transfer gate control signal to activate the pointer transfer circuit and data transfer circuit when the control signal of , (1), (2), and (2) a control circuit that controls the entire device based on control signals.