JPS63122093A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the use of the software of a system by consecutively reading data in case of reading the data from all the memory cells in accordance with the order of consecutive addresses even without any supply of external row address signals. CONSTITUTION:An automatic transmission decision circuit 31 outputs an automatic transmission activating signal phi1 depending on the combination among a control signal, the inverse of RAS, the inverse of WE, the inverse of DT/OE that are supplied from the external. By the signal phi1, an automatic transmission control circuit 33 switches an input change-over circuit 51 to automatic transmission mode, and through a serial address circuit 7, by which an address signal for automatic transmission is generated by from the circuit 33 by the automatic transmission start signal phi2 of a serial address detection circuit 32. And, one- line-share of data is read out from a cell matrix 1 via the circuit 51, an address circuit 2 and through a line buffer circuit 6. Upon completion of a read, the circuit 33 designates a new row address. Therefore, data can be read out consecutively, and the use of software can be relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can be used for both general purpose and image processing purposes.

<Conventional technology> In recent years, semiconductor memory devices have become increasingly larger in capacity and faster, and along with this, the fields of application of the products have also expanded.
It has also been used for image processing in this field, and one form of such a semiconductor memory device is a general-purpose semiconductor memory device that has a circuit added to it so that it can be used for both general-purpose and dual-purpose processing. FIG. 4 shows an example of the circuit block diagram. In FIG. 4, a cell matrix (1) which is an aggregation of many memory cells as a storage device, an address circuit (2),
It consists of a 0 buffer circuit (3), an IO register circuit (4), a control circuit (5), a line buffer circuit (6), a serial address circuit (7), and an image data buffer circuit (8), and serves as a signal input/output terminal. , address signal input terminal (AIN), general-purpose data signal input/output terminal (11), image data signal output terminal (12), and control signal input terminal (
RAS), (CAS), (WE), and (DTloE
), etc. FIG. 5 is a timing diagram showing the combination of inputs of control signals in the data transfer cycle in the conventional example shown in FIG. 4, and in the figure, the shaded portions of each waveform are undefined. The operation of the conventional example will be explained below with reference to FIG. In a data transfer cycle, a row address signal externally applied to the address signal input terminal (AIN) is amplified and decoded in the address circuit (2).
The data (22) read from the memory cells for one row specified by the row selection signal (21), which is supplied to the cell matrix (1) as one row selection word (21), is amplified and then sent to the line buffer. In the circuit (6), the memory cell
Data is transferred to the serial register group corresponding to the row. Here, the number of serial register circuits is equal to the maximum number of addresses indicated by the column address signal. On the other hand, a column address signal applied from the outside to the address signal input terminal (AIN) is amplified in the address circuit (2), decoded in the serial address circuit (7), and then sent to the line buffer as a serial register selection signal (23). Circuit (6)
The operation of the data transfer cycle is completed by selecting the serial register at the address indicated by the column address signal supplied to the column address signal as the first register. Each register indicated by the address is sequentially selected and their serial register data (24)
is transmitted to the image data buffer circuit (8), amplified, and then sequentially outputted to the image data signal output terminal (12). Although the control signal from the control circuit (5) is omitted in FIG. 4, the control circuit (5) is connected to the control signal input terminals (RAS), (CAS), (WE) and (D
The entire device is managed so that image data readout operations and other operations are performed without delay based on control signals including data transfer and sequential readout commands and other commands applied from the outside to the TloE.

<Problems to be solved by the invention> However, in the data transfer cycle of the conventional semiconductor memory device explained above, the line buffer circuit (6
) can only transfer read data for memory cell rows, so the cell matrix (1)
Jl from consecutive address addresses of all memory cells in
When attempting to read the lff-th data, set the data transfer cycle shown in Figure 6 from the outside again after the sequential reading from all serial registers in the line buffer circuit (6) is completed, and repeat the previous data transfer cycle. It is necessary to externally supply a row address signal indicating the address above the address indicated by the row address signal used in the data transfer cycle and a column address signal indicating the lowest address to the address signal input terminal, and this data transfer This has the disadvantage that the number of cycles required is equal to the maximum address of the row address signal. In FIG. 6, "tl" represents a data transfer cycle, and "t2" represents a sequential read cycle. The present invention was made in view of the current situation, and in the case of a mode in which data is read out from all memory cells in a cell matrix according to the order of consecutive addresses, the mode (hereinafter referred to as automatic transfer mode) is determined. It is an object of the present invention to provide a semiconductor memory device having a function of automatically setting a data transfer cycle by performing the following steps.

<Means, operations, and effects for solving the problems> A semiconductor device according to the present invention includes a cell matrix in which a plurality of memory cells are arranged in rows and columns, an address circuit that decodes a row address signal, and a plurality of registers. It has a line buffer circuit that temporarily holds one row of data read out based on the row address signal in each of the plurality of serial registers, and a column address signal that can be decoded to specify the plurality of serial registers. In addition to the serial address circuit, there is also an automatic transfer judgment circuit that outputs an automatic transfer activation signal indicating automatic transfer mode according to an external command, and a serial address circuit that specifies a predetermined serial register when the automatic transfer activation signal is output. Then, a serial address detection circuit outputs an automatic transfer start signal, generates an automatic transfer row address signal that increments sequentially when the automatic transfer start signal is output, and replaces the automatic transfer row address signal with the above row address signal. and an automatic transfer control circuit that can be supplied to the address circuit. Therefore, when automatic transfer mode is instructed, after the data stored in a predetermined serial register is read out of one line of data stored in the line buffer circuit, the serial address detection circuit outputs an automatic transfer start signal. In response to this, the automatic transfer control circuit generates an automatic transfer row address name designating a new row address. As a result, multiple rows of data can be read out continuously without externally supplying a row address signal, and the software requirements of a system including a semiconductor memory device can be reduced.

<Embodiment> FIG. 1 is a block circuit diagram showing an embodiment of the present invention, and parts corresponding to those in FIG. 4 are given the same reference numerals. Further, FIG. 2 is a timing diagram showing the state of manual combination of control signals in the automatic transfer mode setting cycle in the embodiment of FIG. 1, and the shaded portion in the diagram indicates undefined.

FIG. 3 is a timing diagram supplementing the explanation of the internal operation shown in FIG. 1. In the embodiment shown in FIG. 1, compared to the conventional example shown in FIG.
3), Manual switching circuit (51) (δ2) (δ3) (δ4)
and (55) are added. Here, the output signal (φ1) of the automatic transfer judgment circuit (31) is the output signal (φ1) of the serial address detection circuit (32) in the automatic transfer mode.
and an automatic transfer activation signal for the automatic transfer control circuit (33). Also, among the serial registers in the line buffer circuit (6), the serial register selection signal (23) input to the serial register at the maximum address indicated by the column address is especially used as the serial register final signal (YE) to the serial address detection circuit. (32) is also supplied. During the activation period by the automatic transfer activation signal (φ1), a sequential image data read cycle is executed and each serial register indicated by consecutive addresses is selected and selected one after another. The serial register final signal (YE) changes, and the automatic transfer start signal (φ2) output from the serial address detection circuit (32) changes.

The automatic transfer control circuit (33) receives an automatic transfer start signal (φ
2) is manually operated, and the automatic transfer row address signal (φAi), automatic transfer control signals (φR) (φC) and (φ0), and the manual switching signal (φ3) necessary to execute automatic transfer are
) and the manual switching circuit (51) (52) (53)
It is supplied to (54) and (55). Input switching circuit (
51) (52) (53) (54) and (55) are signal input terminals (AIN) (CAS) (WE) (RAS) (
It plays a role of switching either the signal from DTloE) or the automatic transfer control signals (φAi) (φC) (φR) and (φ0) using the switching signal (φ3) and supplying the signal to the internal circuit.

A specific example of the operation of the embodiment shown in FIG. 1 is shown in the timing diagram of FIG.
A specific example of 1) is shown in Figure 7, where the serial address detection circuit (
32) is shown in Fig. 8, the automatic transfer control circuit (33)
Specific examples of input switching circuits are shown in Figures 10 and 1I.
Specific examples of 1) to (55) are shown in FIGS. 12 to 14, respectively.

For convenience of explanation, specific examples of these circuits are CMOS FETs.
However, this is merely for convenience and does not relate to the essence of the present invention.

A detailed explanation will be given below based on specific details. In FIG. 7, the control signal input terminal (R
The control signal input terminals (WE) and (D
The input (T) of the T-type flip-flop in the circuit becomes high potential only when the signals applied from the outside at T/1 are both at ground potential, and the binary output (Q) is inverted, so the binary output (Q) is ) is used to supply information as to whether or not the automatic transfer mode is in the automatic transfer mode to the next stage circuit as an automatic transfer activation signal (φ1) connected to the binary output (Q). When changing to automatic transfer mode from an operation mode other than automatic transfer mode, execute the data transfer cycle in the state of manual combination of control signals shown in Figure 2, and the automatic transfer activation signal (φ1) becomes high potential, and the data The transfer cycle is determined to be an automatic transfer mode setting cycle, but if the data transfer cycle in the manual combination state of the control signals shown in FIG. 2 is executed again after the subsequent image data sequential read cycle, the automatic transfer is activated. signal (
φ1) becomes the ground potential, and this data transfer cycle is determined to be an automatic transfer mode release cycle. As shown in FIG. 8, the image data sequential readout cycle is executed while the automatic transfer activation signal (φ1) is at a high potential, and when the serial register final signal (YE) goes to a high potential, the automatic transfer The automatic transfer start signal (φ2) supplied to the transfer control circuit (33) becomes high potential. As shown in FIG. 10, an automatic transfer row address signal (φ Ai) generation circuit is constructed by cascading as many reset type flip-flops as the number of row address signals. A reverse phase signal of the automatic transfer activation signal (φ1) is used as a reset signal, and the automatic transfer row address signal (φAi) is at the ground potential during periods other than the automatic transfer mode.

During the automatic transfer mode, the automatic transfer start signal (φ2
) becomes a high potential, the automatic transfer row address signal (φAi
The address indicated by ) is the one higher address, and this is repeated every time the automatic transfer start signal (φ2) becomes a high potential. FIG. 9 shows a specific example of a flip-flop with a beam set, which is conventionally known. Figure 11 shows the automatic transfer start signal (φ2), the manual switching signal (φ3), and the automatic transfer control signal (φR) (
This shows a configuration for generating φC) and (φO), and it is clear that the human output relationship is as shown in the timing diagram of FIG. FIG. 12 shows a specific example of the manual switching circuit (54), in which when the manual switching signal (φ3) is at a high potential, the signal from the signal input terminal (RAS) supplied from the outside is
At the time of the ground potential, the automatic transfer control signal (φR) is
The configuration is such that the power is supplied to the internal circuit. Manual switching circuit (
52) and (55), the signal input terminal (RAS) shown in FIG. 12 is connected to (CAS) and (DTloE),
The automatic transfer control signal (φR) is changed to (φC) and (φO), respectively. FIG. 14 shows a specific example of the manual switching circuit (53), and shows the manual switching circuit (53).
When φ3) is at a high potential, the external signal input terminal (WE
), and when the signal (φ3) is at ground potential, a high potential from the power supply is supplied to the internal circuit. FIG. 13 shows a specific example of the input switching circuit (51). When the manual switching signal (φ3) is at a high potential, a signal from an external signal input terminal (AIN) is supplied to the internal circuit. (φ3) becomes the ground potential, and at the same time the automatic transfer row address signal (φAi) and then the automatic transfer control signal (φC) change to the ground potential, the reset transistor becomes conductive and supplies the ground potential to the internal circuit. It is configured to do this. As explained above, in this embodiment, when the mode is to read image data from all memory cells in the cell matrix (1) in the order of consecutive addresses, the data transfer cycle is started by determining the mode. Since the settings are performed automatically, the number of external data transfer cycles is reduced and the method of using the device is simplified. In addition, in the circuit examples shown in and after Figure 7, CMOS
Although it is realized by FET, it is obvious that other types of semiconductor devices and other circuit connection formats are also included in the scope of the present invention as long as they have the automatic transfer function according to the present invention. It is.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing one embodiment of the present invention, and FIG.
The figure is a timing diagram of an external control signal of one embodiment, FIG. 3 is a timing diagram explaining the internal operation of one embodiment, FIG. 4 is a block circuit diagram of a conventional example, and FIG. 5 is an external control signal of a conventional example. 6 is a timing diagram explaining the internal operation of the conventional example, FIG. 7 is a circuit diagram of an automatic transfer determination circuit of one embodiment, and FIG. 8 is a circuit showing a serial address detection circuit of one embodiment. 9 is a circuit diagram of a D flip-flop with reset, FIG. 10 is a circuit diagram showing a part of an automatic transfer control circuit of one embodiment, and FIG. 11 is a part of an automatic transfer control circuit of one embodiment. FIG. 12 and FIG. 14 are circuit diagrams showing a manual switching circuit used in one embodiment. 1...Cell matrix, 2...Address circuit, 6...Line buffer circuit, 7...Serial address circuit, 31...Automatic transfer judgment circuit, 32...Serial address detection Circuit, 33... automatic transfer control circuit. Patent applicant: NEC Corporation Figure 7 YE Figure 9 φ2 φ3 φc 4). Figure 1I q'j Figure 72 Figure 73

Claims (1)

[Claims] A cell matrix in which a plurality of memory cells are arranged in rows and columns, a line buffer circuit that temporarily holds one row of data read out based on a row address signal in each of the plurality of serial registers, and a column address signal. an automatic transfer determination circuit that outputs an automatic transfer activation signal indicative of an automatic transfer mode in accordance with an external command in a semiconductor storage device including a serial address circuit that can decode and specify the plurality of serial registers; A serial address detection circuit that outputs an automatic transfer start signal when the serial address circuit specifies a predetermined serial register when outputting a signal, and a serial address detection circuit that generates an automatic transfer row address signal that increments sequentially when the automatic transfer start signal is output. A semiconductor memory device further comprising an automatic transfer control circuit capable of supplying the automatic transfer row address signal to the address circuit instead of the row address signal.