JPS6124087A - Analog memory circuit - Google Patents

Abstract

PURPOSE:To realize a long storage time by one chip integrated circuit by mounting an address generating circuit and the 2nd RAM writing the 1st address value and the 2nd address value finished for write on one chip. CONSTITUTION:The content of the 1st address register at start of write is written in an address location possible for write in a RAM 18. The content of the 1st address register is fed to a data input line 19 and the content of an address register (2nd address register) corresponding to the RAM 18 is fed to an address input line 21, then a write enable signal is fed to the signal line 20. At the end of write, the value of the address counter is written in the next write location of the RAM 18 and the value of the 1st and 2nd address registers is set to the address value of the next write enable location. In applying a reset signal to a reset terminal 23, the 1st and 2nd address registers are reset to the 1st address location of the RAM 2 and 18.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an electrical analog memory realized as a one-chip integrated circuit.

(Prior Art and its Problems) When a device or the like that processes image signals or audio signals performs processing that cannot be executed in real time, it becomes necessary to store analog quantities.

However, analog memories that have been put into practical use to store analog quantities are non-electrical devices such as image storage tubes and magnetic tapes, and are difficult to incorporate into electrical circuits. Therefore, in order to electrically store analog quantities, analog delay elements using charge transfer elements are used as a substitute, but they can only store information for a very short time, and this poses a major limitation in configuring the device. It has become.

(Object of the invention) In view of the above, the present invention has a long storage time,
It is an object of the present invention to provide an electrical analog memory circuit that is easy to use and can be implemented as an 1-chip integrated circuit.

(Structure of the Invention) According to the present invention, the AD converter and the data input terminal are
a first random access memory (hereinafter referred to as RAM) connected to the D-conversion converter output;
a DA converter connected to the data output terminal of the RAM;
When writing data to the first RAM, a continuously changing address signal starting from a first address value indicating the first address of an area where data is not written in the first RAM is sent to the first RAM. an address generation circuit that is applied to an address input terminal of a RAM; and a second RAM that writes the first address value and a second address value that has been written when writing data to the first RAM;
An analog memory circuit characterized by being mounted on a chip is obtained.

(Summary of the present invention) The present invention takes advantage of the high degree of integration of recent integrated circuits, combines an analog signal/digital signal mutual conversion circuit, and a digital memory, and combines a control circuit called an address generation circuit and a digital memory. It is mounted on a single chip integrated circuit together with another digital memory for memorizing the write position above.

When a control signal instructing write to the address generation circuit is applied from the outside, the address generation circuit converts the analog signal into a digital signal and generates a control signal to write it into an unused area of the digital memory.

At the same time, the write location is stored in the second digital memory. Furthermore, when a control signal that instructs the address generation circuit to read and a signal that instructs the data to be written is applied from the outside, the address generation circuit determines the write position stored in the second digital memory. When reading, a control signal is generated to convert the digital signal stored at that position into an analog signal and output it.

In this way, it operates as an electrical analog memory element when viewed from the outside.

(Example) The present invention will be explained below using FIG. 1 showing one example.

In FIG. 1, 1 is an AD conversion circuit, 2 is a RAM, 3 is a DA conversion circuit, and 4 is an address generation circuit. The input of the AD conversion circuit 1 is connected to an analog input terminal 5, and the output is connected to a data input line 6 of the RAM 2. The input of the DA conversion circuit 3 is connected to the data output line 7 of the RAM 2, and the output is connected to the analog output terminal 8.

Address generation circuit 4 applies an address signal to the address input line of RAM 2 through signal line 12.

Further, the address generation circuit 4 applies a conversion start signal to the AD conversion circuit 1 through a signal line 9, and also applies a conversion start signal to the AD conversion circuit 1 through a signal line 10.
Receives a conversion end signal from the D conversion circuit 1. Further, the address generation circuit 4 applies a write enable signal to the RAM 2 through a signal line 11, and also applies an output enable signal to the DA conversion circuit 3 through a signal #13. Further, the address generation circuit 4 is connected to the data input line 19 of the RAM 18 and to the data output line 22. Further, the address generation circuit 4 is R
A write enable signal is applied to AM18 through signal line 2o, and an address signal is applied through signal line 21.

The circuit of FIG. 1 operates as follows. The address generation circuit has two address registers internally, each with R
The currently writable first address locations of AM2 and RAM 18 are set.

When writing data, a write signal is applied to the write control terminal 14. The address generation circuit sets the value of the address register (hereinafter referred to as cylinder 1 address register) corresponding to RAM 2 in the address counter, and
A signal that disables the output of the DA converter 3 is output to terminal 16, and a signal indicating that the chip is currently in a readable state is output to terminal 16.

Next, a conversion start signal is applied to the AD conversion circuit 1 through the signal line 9. When the AD conversion circuit 1 receives this signal, it converts the analog signal on the analog input terminal 5 into a digital signal, and when it is applied to the data input 6 of the RAM 2, it applies a conversion end signal to the address generation circuit 4 through the signal line 10. . Then, the address generation circuit 4 adds the contents of the address counter to the address input of the RAM 2 through the signal line 12, and then the signal line 111! - applies a write enable signal to RAM2 through. In this way, the signal on the data input 6 is written to the first address of the specified segment on RAMZ.

Next, the address generation circuit disables the write enable signal on the signal line 11 again, increments the contents of the address counter by one, and also applies a conversion start signal to the AD conversion circuit 1 through the signal line 9.

The AD conversion circuit 1 converts the input signal on the analog input terminal 5 at the next sampling point into a digital signal, applies it to the data input line 6, and outputs a conversion end signal on the signal line lo. The data on data input line 6 is written to the next address on RAM 2 in exactly the same way as the first data. The contents of the address counter are also incremented.

The above steps are repeated, and the input signals are successively converted into digital signals and written into the RAM 2. In order to finish writing, the application of the write signal to the terminal 14 is stopped. Then, the address generation circuit 4 no longer outputs a conversion start signal to the signal line 9, stops the write operation, and outputs a signal to the terminal 16 indicating that the circuit is ready for reading. The contents of the first address register at the start of writing are written to the first writable address location of RAM 18 at the start or end of writing.

Therefore, K adds the contents of the first address register to the data input line 19, and also adds the contents of the address register corresponding to the RAM 18 (hereinafter referred to as the address register of tube 2) to the address input line 21, and then connects the signal line to the address input line 21. A write enable signal is added to 20.

Also, at the end of writing, the value of the address counter is stored in the RAM.
Similarly, writing is performed at the next writing position after No. 18. Next, the values of the first and second address registers are set to the values of the addresses of the next writable locations.

When reading data, first add a signal to terminal 17 indicating which data is written.

Next, a read start signal is applied to the terminal 15. When the address generation circuit 4 receives this signal, it first determines the address value on the RAM 18 in which the address data corresponding to the specified order on the RAM 18 is written, and adds it to the address input line 21. The two values are sequentially read out to the data output line 22. One of the two read values is the first address value on RAMZ where data corresponding to the specified order is written (hereinafter referred to as the start address value), and the other value is the last value. The address value of (
(hereinafter referred to as the end address value).

Next, a start address value is set in the address counter, and a signal is sent to the signal line 13 to enable the output of the DA conversion circuit 3. Thereafter, the contents of the address counter are added to the address input line 12 while being incremented at regular time intervals until the end address value is reached.

In this way, an analog signal is obtained at the analog output terminal 8. At this time, if the time interval for incrementing the address counter is made the same as the sampling interval during writing, the same signal as the written signal can be obtained. By changing this, you can also obtain a waveform whose time axis is expanded or contracted. Further, if necessary, an external terminal may be provided to control this time interval.

When a reset signal is applied to the reset terminal 23, the first and second address registers are set to RAM2 and RAM, respectively.
It is reset to the first address location of 18, and new data can be written from the first location.

As described above, the circuit shown in FIG. 1 functions as an analog memory circuit when viewed from the external terminal.

Note that it is not necessarily necessary to indicate a readable state to the terminal 16 or to disable output through the signal line 13, and these may be provided as necessary. In addition, in the embodiment shown in FIG. 1, the conversion start signal and conversion end signal are used to synchronize the AD conversion circuit and address generation circuit during writing, but this is done by using the same clock in both circuits. You can also omit it by doing this.

(Effects of the Invention) As described above, according to the present invention, the storage time is arbitrary,
A one-chip analog memory element that is easy to use can be obtained, and has great effects on signal processing devices such as audio storage devices.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, 1 is an AD converter. 2 and 18 are RAM
It is. 4 is an address generation circuit. 5 is an analog input terminal. 6 and 19 are data input lines. 7 and 22 are data output lines. 8 is an analog output terminal. 9, 10, 11, 12゜13, 20, 21 are signal lines, 9 is the conversion start signal, 10 is the gender conversion end signal, 11 and 20 are the write enable signals, 12 and 21 are the signal lines. 13 outputs an address signal and 13 outputs an output enable signal, respectively. 14 is a write control terminal. 15 is a read instruction terminal. 16 is a readable display terminal. 17 is a read data instruction terminal. 23 is an address reset terminal. Representative Patent Attorney Susumu Uchihara1' ,-,,,-,
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Claims (1)

[Claims] an AD converter, and a first random access memory (hereinafter referred to as R) whose data input terminal is connected to the output of the AD converter.
AM), a DA converter whose input terminal is connected to the data output terminal of the first RAM, and the first RA
When writing data to M, the first address indicating the first address of the area where data is not written in the first RAM
an address generation circuit that applies a continuously changing address signal starting from an address value to an address input terminal of the first RAM; and an address generation circuit that applies a continuously changing address signal starting from an address value of An analog memory circuit characterized in that a second RAM for writing a completed second address value is mounted on one chip.