JPH03295095A - Variable capacity fifo memory - Google Patents

Abstract

PURPOSE:To reduce a phase difference between write and readout by devising the memory capacity to be freely set externally. CONSTITUTION:When a desired storage capacity is entered to an address control circuit 12 by using a storage capacity signal MS, the circuit 12 monitors a write pointer circuit 2 and a read pointer circuit 3, compares an address corresponding to a setting storage capacity with write and read addresses generated respectively from the circuits 2, 3 and controls the write pointer circuit 2 and the read pointer circuit 3, by which a required storage capacity is set. As a result of setting an adaptive storage capacity, the phase difference between the write and readout is decreased in the FIFO memory.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a circuit configuration of a FIFO memory.

[Prior art 1 Figure 3 shows High Performance-CMO5
DATA BOOK SUPPLE! i! ENT 198
This is a functional block diagram showing the conventional FIFO memory shown in Figure 9. In Figure 1, (1) is a memory array circuit that stores data, (2) is a write pointer circuit that generates a write address, and (3) is a read address. (4) is a write control circuit that controls writing, (5) is a read control circuit that controls reading, (6) is a reset circuit that resets the internal, and (7) is various types. A flag generation circuit generates a flag, (8) is an expansion circuit for cascading FIFOs, (9) is a data input circuit, (1
0) is a tri-state buffer for data output, (11)
is the data output.

Next, the operation will be explained.

When the noset signal (R3) is made significant and inputted to the reset circuit (6), the reset circuit (6) resets the internal circuit and reads the write and read addresses generated from the write pointer circuit (2) and read pointer circuit (3). Set each to "0", and then set the flag generation circuit (7) and expansion circuit (8) to "0".
) disables the flag output from After resetting, write (R) by external input (W).
) is used for reading.

First, the write operation will be explained.

When the write enable signal (W) is made significant.

The signal applied to the data input (9) is input to the initialized write address "0" of the memory array circuit (1). When (W) becomes insignificant, writing is inhibited and the signal from the data input (9) has no effect within the FIFO. At this time, the write pointer circuit (2) counts and the write address changes to rlJ.

The write address changes sequentially and the write operation is performed by repeating the above operation, but when the write data becomes half the capacity of the memory array circuit (1), a half flag (XO/HF) is set in the expansion circuit (8). make significant.

Further, when the write data fills the capacity of the memory array circuit (1), the full flag (FF) is made significant in the flag generation circuit (7).

Next, the read operation will be explained.

Immediately after resetting, since no valid data is stored in the memory array circuit fl), the flag generation circuit (7
) makes the empty flag (E/F) significant.

(E/F) becomes insignificant after one word of data is written to the memory array circuit (1). Lead
When the enable signal (R) is made significant, the read address "0" indicated by the read pointer circuit (3) immediately after reset.
'' data is passed through a tri-state buffer (10) and outputted (11).

Then, when (R) becomes insignificant, the read pointer circuit (
3) performs counting, and the read address indicates "1". Further, when the tri-state buffer is set to 2, output is prohibited and becomes a high impedance state.

The read address also changes in order, and the read operation is performed by repeating the above operation, but when all the valid data stored in the memory array circuit (1) has been read out, the flag generation circuit (7) E/F) becomes significant.

XI and XO are signals for cascading FIFOs, and by connecting xO to XI of the next stage FIFO, the FIFO can be expanded in the word direction.

[Problems to be Solved by the Invention] Since the conventional FIFO memory is configured as described above, the storage capacity is fixed, and a single FIFO cannot be used adaptively from a small capacity to a large capacity. In addition, writing and reading are used asynchronously, and although there are many types of required capacities, in order to improve hardware efficiency, when using a single FIFO, it is asynchronous, so writing and reading are asynchronous. There is a phase difference in the timing, which gradually becomes larger (particularly when the capacity used is small compared to the capacity of the FIFO, the time it takes to read the written data becomes very long).

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a FIFO memory in which the storage capacity can be arbitrarily specified from the outside and the storage capacity can be adaptively controlled.

[Means for Solving the Problems] A FIFO memory according to the present invention is provided with a write and read address control circuit that allows changing the storage capacity according to storage capacity information input from the outside.

[Operation] The FIFO memory according to the present invention has the above-described configuration so that the FIFO memory according to the storage capacity input from the outside,
An address control circuit operates to control write and read addresses and set the required storage capacity. As a result, data that has been manually entered can be outputted from the FIFO at the time when data corresponding to the set storage capacity has been written.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In Figure 1, (11 is a memory array circuit that stores data, (2) is a write pointer circuit that generates a write address, (3) is a read pointer circuit that generates a read address, and (4) is a write pointer circuit that controls writing. A control circuit (5) is a read control circuit for controlling reading, and (6) is a reset circuit for resetting the internal components.

(7) is a flag generation circuit that generates various flags.

(8) is an expansion circuit for cascading FIFOs, (9) is a data input, (10) is a tri-state buffer for data output, and (11) is a data output.

(12) is an address control circuit for monitoring and controlling addresses generated in the write pointer circuit and read pointer circuit.

Next, the operation will be explained.

When the reset signal (R3) is made significant and input to the reset circuit (6), the reset circuit (6) resets the internal circuit and writes and reads addresses generated from the write pointer circuit (2) and read pointer circuit (3). Set each to "0", and then set the flag generation circuit (7) and expansion circuit (8) to "0".
) disables the flag output from After resetting, write (R) by external input (W)
Read is performed by.

First, the write operation will be explained.

When the write enable signal (W) is made significant.

The signal applied to the data input (9) is input to the initialized write address "0" of the memory array circuit (1). When (W) becomes insignificant, writing is prohibited and the signal from data input (9) is transferred to the FIFO
does not affect internally. At this time, the write pointer circuit (2)
counts, and the write address changes to "1".

The write address changes sequentially, and the write operation is performed by repeating the above operation.

Next, the read operation will be explained.

Immediately after resetting, since no valid data is stored in the memory array circuit (1), the flag generation circuit (7)
), the empty flag (E/F) is made significant by being reset.

(E/F) becomes insignificant after one word of data is written to the memory array circuit (1).

When the node enable signal (R) is made significant, the data at the read address "0" indicated by the read pointer circuit (3) immediately after reset is outputted (11) through the tristate buffer (1O). When (R) becomes insignificant, the read point circuit (3) counts and the read address indicates "1".

Further, the tri-state buffer is inhibited from outputting at this time and enters a high impedance state.

The read address also changes sequentially, and the read operation is performed by repeating the above operation.

Next, the operation of setting the storage capacity will be explained.

From the storage capacity information signal (MS) to the address control circuit (12
), the address control circuit (12) monitors the write pointer circuit (2) and the read pointer circuit (3).

The write address and read address generated from each are compared with the address corresponding to the storage capacity to be set, and the write pointer circuit (
2) Control the read pointer circuit (3)? Set the required storage capacity by wholesale.

When the write data becomes half of the set storage capacity, the half flag (XO/HF) is made significant in the expansion circuit (8). When the write data fills the set storage capacity, the flag generation circuit (7) generates a full flag (F
/F) is made significant.

Furthermore, when all the valid data stored in the memory array circuit (1) is read out, the empty flag (E/F) is made significant in the flag generation circuit (7).

XI and XO are signals for connecting and sussing the FIFO; by connecting xO to XI of the next stage FIFO, the FIFO can be expanded in the word direction.

In the above embodiment, write control circuit (4) read control (5) reset circuit (7) expansion circuit (
8), but these circuits may be omitted.

Further, a 2-port RAM or RAM is used for the memory array circuit (1), and there are no restrictions on the number of bits and the number of words.

Other embodiments of the invention will be described below with reference to the drawings.

In Figure 2, (1) is a memory array circuit that stores data, (2) is a write pointer circuit that generates a write address, (3) is a read pointer circuit that generates a read address, and (4) is a circuit that controls writing. A write control circuit, (5) a read control circuit that controls reading, and (6) a reset circuit that resets the internals.

(7) is a flag generation circuit that generates various flags.

(8) is an expansion circuit for cascading FIFOs, (9) is a data input, (lo) is a tri-state buffer for data output, and (11) is a data output.

(12) is an address control circuit for controlling addresses generated in the write pointer circuit and read pointer circuit.

[Effects of the Invention] As described above, according to the present invention, the write and read addresses are controlled by the address control circuit in accordance with external storage capacity information, so that the required storage capacity can be set arbitrarily. This has the effect of shortening the phase difference between writing and reading by adaptively setting the storage capacity externally.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing a variable capacity FIFO memory according to one embodiment of the present invention, FIG. 2 is a functional block diagram showing a variable capacity FIFO memory according to another embodiment of the present invention, and FIG. 3 is a functional block diagram showing a variable capacity FIFO memory according to another embodiment of the present invention. In the functional block diagram showing memory, (1) is a memory array circuit, and (2) is a write pointer circuit. (3) is a read pointer circuit, (4) is a write control circuit, and (5) is a read control circuit. (6) is a reset circuit, and (7) is a flag generation circuit. (8) is an expansion circuit, (9) is a data input, (io) is a tri-state buffer for data output, (11) is a data output, and (12) is an address control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts. Figure 1 Figure 2

Claims (1)

[Claims] (1) A FIFO memory equipped with a memory array circuit that stores data, a write pointer circuit that indicates the write position, and a read pointer circuit that indicates the read position, the storage capacity of which can be arbitrarily set from the outside. Variable capacity FIFO memory.