JPS6310447B2 - - Google Patents
Info
- Publication number
- JPS6310447B2 JPS6310447B2 JP57200169A JP20016982A JPS6310447B2 JP S6310447 B2 JPS6310447 B2 JP S6310447B2 JP 57200169 A JP57200169 A JP 57200169A JP 20016982 A JP20016982 A JP 20016982A JP S6310447 B2 JPS6310447 B2 JP S6310447B2
- Authority
- JP
- Japan
- Prior art keywords
- digital data
- analog input
- output
- circuit
- conversion circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 15
- 239000003990 capacitor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Analogue/Digital Conversion (AREA)
Description
【発明の詳細な説明】
本発明はアナログ入力の変換回路に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an analog input conversion circuit.
近来、マイクロコンピユータが多方面にわたつ
て使用されてきており、これに伴つてアナログ入
力をデジタルデータに変換するインターフエイス
としてＡ―Ｄ変換回路の需要が急速に増大してき
ている。ところが複数種類のアナログ入力をデジ
タルデータに変換する場合に、その数だけＡ―Ｄ
変換回路を必要とし、その分だけの出力端子を必
要とするものであつた。 In recent years, microcomputers have been used in a wide variety of fields, and as a result, the demand for AD conversion circuits as interfaces for converting analog input into digital data is rapidly increasing. However, when converting multiple types of analog input into digital data, the number of A-D
This required a conversion circuit and an output terminal corresponding to the conversion circuit.
そこで本発明は１系統のアナログ入力を時系列
的に複数系統に変換した各アナログ出力を一旦容
量素子に記憶させた後一つのＡ―Ｄ変換回路によ
つて順次時分割的にデジタルデータに変換し記憶
回路に記憶させるようにし、簡単な構成で安価な
アナログ入力の変換回路を提供するものである。 Therefore, the present invention converts one analog input system into multiple systems in time series, stores each analog output in a capacitive element, and then sequentially converts it into digital data in a time-sharing manner using one AD conversion circuit. The present invention provides an analog input conversion circuit which has a simple configuration and is inexpensive, by storing the information in a memory circuit.
以下本発明の一実施例を図面に基づいて説明す
る。M′はマルチプレクサで、端子ａからの１系
統のアナログ入力を時系列的に８系統のアナログ
出力に変換するものである。C1〜C8は各アナロ
グ出力を記憶する容量素子、Ｍは選択回路を構成
するマルチプレクサ、SEはマルチプレクサＭの
制御回路である。DEはＡ―Ｄ変換回路、REはレ
ジスタ、Aw，Arはそれぞれ書込み用および読出
し用のアドレス指定回路である。 An embodiment of the present invention will be described below based on the drawings. M' is a multiplexer that converts one system of analog input from terminal a into eight systems of analog output in time series. C1 to C8 are capacitive elements that store each analog output, M is a multiplexer forming a selection circuit, and SE is a control circuit for the multiplexer M. DE is an AD conversion circuit, RE is a register, and Aw and Ar are addressing circuits for writing and reading, respectively.
上記の構成は総て１チツプの集積回路にまとめ
てある。 All of the above configurations are integrated into a single chip integrated circuit.
以上の構成において、Ａ―Ｄ変換回路DEの変
換時間に比べて変化の速いアナログ入力を連続的
に変換する場合について説明する。マルチプレク
サM′の入力端子a0には連続したアナログ入力が
供給され、これが制御回路SE′の出力によつて、
クロツクパルスの周期にしたがつて順次容量素子
C1〜C8にサンプリングされる。 In the above configuration, a case will be described in which an analog input that changes faster than the conversion time of the AD conversion circuit DE is continuously converted. The input terminal a 0 of the multiplexer M′ is supplied with a continuous analog input, which is controlled by the output of the control circuit SE′.
The capacitive elements are sequentially connected according to the period of the clock pulse.
Sampled from C1 to C8 .
一方、制御回路SEには端子Clからクロツクパ
ルスが供給されており、その出力によつてマルチ
プレクサＭから容量素子C1〜C8の各出力が順次
時分割的に生じる。この各出力はＡ―Ｄ変換回路
DEによつてデジタルデータに変換されレジスタ
REに順次供給される。これに同期してアドレス
指定回路Awによつてアドレス指定が行なわれ８
種類のデジタルデータがレジスタREに書き込ま
れる。 On the other hand, the control circuit SE is supplied with a clock pulse from the terminal Cl, and the output of the clock pulse causes the multiplexer M to output each of the capacitive elements C1 to C8 sequentially in a time-division manner. Each output is an A-D conversion circuit
Converted to digital data by DE and registered
Sequentially supplied to RE. In synchronization with this, addressing is performed by the addressing circuit Aw.
digital data of type is written to register RE.
読出し用のアドレス指定回路Arには、例えば
マイクロコンピユータ（図示せず。）から端子r1
〜r3にアドレス指定データが供給され、これによ
つてレジスタREから各データが読み出される。
本例では一つのデータを８ビツトで表わし、１デ
ータずつ端子d1〜d8からマイクロコンピユータに
供給される。 The read addressing circuit Ar includes, for example, a terminal r 1 from a microcomputer (not shown).
~ r3 is supplied with addressing data, thereby reading each data from register RE.
In this example, one piece of data is represented by 8 bits, and each piece of data is supplied to the microcomputer from terminals d1 to d8 .
上記動作が、端子Wrに書込み信号が供給され
るごとに行なわれ、その時点での各アナログ入力
がデジタルデータに変換される。 The above operation is performed every time a write signal is supplied to the terminal Wr, and each analog input at that time is converted into digital data.
これによればアナログ入力を高速でサンプリン
グでき、変化が急激なものでも忠実にデジタルデ
ータに変換することができる。 According to this, analog input can be sampled at high speed, and even rapid changes can be faithfully converted into digital data.
なお上記の各実施例では１系統のアナログ入力
を８ビツトのデジタルデータに変換したが、これ
らの数値に限定されるものではない。 Note that in each of the above embodiments, one system of analog input is converted into 8-bit digital data, but the invention is not limited to these numerical values.
以上詳述したごとく本発明によれば、端子数の
少ない簡単な回路構成で１系統のアナログ入力を
時系列的にデジタルデータに変換することがで
き、高速で変化するアナログ入力を比較的低速の
Ａ―Ｄ変換回路で変換することができる。しかも
各構成を１チツプのモノリシツクMOSIC上に作
るのが容易であり、この場合部品点数および実装
コストの低減が図れる。 As detailed above, according to the present invention, one system of analog input can be converted into digital data in time series with a simple circuit configuration with a small number of terminals, and analog input that changes at high speed can be converted to digital data at relatively low speed. It can be converted using an A-D conversion circuit. Moreover, each configuration can be easily fabricated on a single-chip monolithic MOSIC, and in this case, the number of components and mounting cost can be reduced.
図面は本発明の一実施例を示したブロツク図で
ある。
C1〜C8…容量素子、M′…マルチプレクサ、Ｍ
…選択回路、DE…Ａ―Ｄ変換回路、RE…レジス
タ。
The drawing is a block diagram showing one embodiment of the present invention. C 1 to C 8 ...Capacitive element, M'...Multiplexer, M
...Selection circuit, DE...A-D conversion circuit, RE...Register.
Claims (1)
系統のアナログ出力に変換するマルチプレクサ
と、このマルチプレクサからの各系統のアナログ
出力をそれぞれ記憶する容量素子と、この各容量
素子の出力を順次時分割的に選択する選択回路
と、この選択回路からの出力をデジタルデータに
変換するＡ―Ｄ変換回路と、このＡ―Ｄ変換回路
からのデジタルデータを記憶する記憶回路とから
なるアナログ入力の変換回路。1. A multiplexer that converts one system of analog input into multiple systems of analog output in time series, a capacitor that stores each system's analog output from this multiplexer, and a time-division multiplexer that sequentially converts the output of each capacitor into multiple systems of analog output. An analog input conversion circuit consisting of a selection circuit that selects the digital data, an AD conversion circuit that converts the output from the selection circuit into digital data, and a storage circuit that stores the digital data from the AD conversion circuit. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20016982A JPS5990139A (en) | 1982-11-15 | 1982-11-15 | Converting circuit of plural data |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20016982A JPS5990139A (en) | 1982-11-15 | 1982-11-15 | Converting circuit of plural data |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5990139A JPS5990139A (en) | 1984-05-24 |
| JPS6310447B2 true JPS6310447B2 (en) | 1988-03-07 |
Family
ID=16419936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20016982A Granted JPS5990139A (en) | 1982-11-15 | 1982-11-15 | Converting circuit of plural data |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5990139A (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61107815A (en) * | 1984-10-30 | 1986-05-26 | Nec Corp | Digital coder |
| JPH03238923A (en) * | 1990-02-15 | 1991-10-24 | Mitsubishi Electric Corp | A/d converter |
| JPH07297721A (en) * | 1994-07-29 | 1995-11-10 | Hitachi Ltd | A/d conversion method |
| KR100538226B1 (en) * | 2003-07-18 | 2005-12-21 | 삼성전자주식회사 | Analog to digital converting device for processing plural analog input signal by high speed and display apparatus using the same |
| JP4660138B2 (en) * | 2004-08-12 | 2011-03-30 | 三洋電機株式会社 | A / D converter and receiving apparatus using the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4852439A (en) * | 1971-11-05 | 1973-07-23 | ||
| JPS50109659A (en) * | 1974-02-04 | 1975-08-28 | ||
| JPS5245850A (en) * | 1975-10-08 | 1977-04-11 | Nippon Denso Co Ltd | Data input equipment |
| JPS52127136A (en) * | 1976-04-19 | 1977-10-25 | Seikosha Kk | Data processing system |
| JPS5313941A (en) * | 1976-07-23 | 1978-02-08 | Chino Works Ltd | Data collecting device |
-
1982
- 1982-11-15 JP JP20016982A patent/JPS5990139A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4852439A (en) * | 1971-11-05 | 1973-07-23 | ||
| JPS50109659A (en) * | 1974-02-04 | 1975-08-28 | ||
| JPS5245850A (en) * | 1975-10-08 | 1977-04-11 | Nippon Denso Co Ltd | Data input equipment |
| JPS52127136A (en) * | 1976-04-19 | 1977-10-25 | Seikosha Kk | Data processing system |
| JPS5313941A (en) * | 1976-07-23 | 1978-02-08 | Chino Works Ltd | Data collecting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5990139A (en) | 1984-05-24 |
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