JP4660138B2 - A / D converter and receiving apparatus using the same - Google Patents

Description

  The present invention relates to an A / D conversion device and a receiving device using the same.

In recent years, in digital control systems in various fields, the types and number of analog signals to be handled as control amounts are increasing in order to achieve high performance and high functionality. Therefore, in the digital control system, it is necessary to provide an A / D conversion device that converts analog signals respectively obtained from a plurality of channels (analog signal transmission paths) into digital signals (see, for example, Patent Document 1 shown below). .
JP 2001-223586 A

  By the way, as a configuration of an A / D conversion device that converts an analog signal obtained from each of a plurality of channels into a digital signal, for example, one A / D corresponding to each analog signal obtained from each of a plurality of channels. An embodiment having D converters corresponding to the number of channels is conceivable. However, in general, an A / D converter is likely to have a problem in circuit scale and power consumption as compared with other components, and moreover, as the number of channels tends to increase, one A / D converter is required. There are many problems in providing as many channels as possible.

  Therefore, there is a need for a mechanism in which an A / D conversion device converts an analog signal obtained from each of a plurality of channels into a digital signal using a single A / D converter. However, in such a mechanism, one A / D converter converts analog signals respectively obtained from a plurality of channels into digital signals, so that the processing inside the A / D converter is complicated. It will be something. For this reason, when an analog signal obtained from each of a plurality of channels is converted into a digital signal in one A / D converter, the efficiency of processing inside the A / D converter must be improved.

Primary aspect of the present invention to solve the problems described above, n (n is a natural number of 2 or more) in the A / D converter to convert the after sample and hold the respective resulting analog signals from the number of channels to digital signals, 1 One A / D converter including a plurality of first sample and hold circuits, and an analog signal to be processed first by the A / D converter in the first sample and hold circuit; At the same time, n−1 second samples obtained by sampling and holding the analog signals to be processed by the A / D converter from the second to the nth, respectively, obtained from the n−1 channels. The hold circuit, the analog signal to be processed first by the A / D converter, obtained from one channel, and the second sample and hold circuit collectively support the analog signal. An analog signal selection circuit that sequentially selects the sampled and held analog signal according to the processing order in the A / D converter and supplies the analog signal to the A / D converter. The sampler samples and holds the first analog signal selected in the analog signal selection circuit in the first sample and hold circuit, and then selects the second to nth analog signals sequentially selected in the analog signal selection circuit. The first sample and hold circuit sequentially samples and holds .

  ADVANTAGE OF THE INVENTION According to this invention, the A / D conversion apparatus which aimed at the efficiency of internal processing, and a receiver using the same can be provided.

=== A / D Converter ===
<Overall configuration>
FIG. 1 is a diagram illustrating an example of input / output signal specifications of an A / D conversion apparatus 100 according to an embodiment of the present invention. The A / D converter shown in the figure sequentially converts analog signals respectively obtained from 4 channels (analog signal paths) into 10-bit digital signals using one A / D converter. In case of specifications. Of course, the number of channels of the analog signal is not limited to this specification, and may be a natural number of 2 or more. Similarly, the number of bits of the digital signal is not limited to this specification, and any number of bits can be adopted.

  As the pin specifications on the input signal side of the A / D converter 100, analog signals AINA, AINB, AINC, and AIND obtained from four channels (ch. A, ch. B, ch. C, ch. D), respectively, are used. There are a pin for inputting, a pin for inputting the reference clock signal CLKIN, and a pin for inputting a standby mode setting signal STBY for setting the standby mode. Note that the standby mode is a mode in which the current path inside the A / D converter 100 is cut off.

  As the pin specifications on the output signal side of the A / D converter 100, a 10-bit digital signal Dn (n = 0 to 9) A as a result of A / D conversion performed on each of the analog signals AINA to AIND, Dn (n = 0 to 9) B, Dn (n = 0 to 9) C, Dn (n = 0 to 9) D output pins, and the timing of each of the digital signals DnA to DnD are external to the A / D converter 100. And a pin for outputting a reference clock signal OCLK for controlling the signal.

  FIG. 2 is a diagram showing a configuration of the A / D conversion apparatus 100 according to an embodiment of the present invention.

  The sample-and-hold circuits 10a, 10b, and 10c are an embodiment of the “second sample-and-hold circuit” recited in the claims. The sample and hold circuits 10a, 10b, and 10c, except for the analog signal AINA to be processed first in the A / D converter 12, based on the sample and hold control signal SHCLK generated in the timing signal generation circuit 15, ch. B-ch. In the A / D converter 12 obtained from D, a total of 3 (= 4-1) analog signals of analog signals AINB to AIND to be sequentially processed after the second are sampled and held together.

  The analog input selection circuit 11 is an embodiment of an “analog signal selection circuit” recited in the claims. Based on the analog input selection signals SELAI to SELDI generated by the timing signal generation circuit 15, the analog input selection circuit 11 has one ch. The analog signal AINA to be processed first obtained from A and the analog signals AINB, AINC, and AIND to be processed second and later that have been collectively sampled and held in the sample hold circuits 10a, 10b, and 10c are The signals are sequentially selected according to the processing order in the D converter 12 and supplied to the A / D converter 12.

  The A / D converter 12 is one analog input AIN (any one of AINA or AINB to AIND after sample hold) including one sample hold circuit 120, and one 10-bit digital output D9 to D0. This is an A / D converter. The A / D converter 12 is an embodiment of the “A / D converter” recited in the claims of the present application, and the sample hold circuit 120 is configured of the “first sample hold” recited in the claims of the present application. It is one embodiment. In recent years, with the progress of semiconductor integration technology such as CMOS, a sample hold circuit provided as a peripheral circuit of an A / D converter is simplified as a peripheral circuit like the A / D converter 12. For this purpose, sample-hold circuit built-in A / D converters are in circulation.

  The A / D converter 12 adopts a so-called pipeline type (or a traveling wave type) that performs A / D conversion processing on analog signals for a plurality of channels in an overlapping manner. To do. The pipeline type A / D converter is disclosed in, for example, “Yoshiyama Toshikazu, New Edition Illustrated A / D Converter Introduction, pages 128 to 129, published by Ohmsha”, and will be described in detail later. The A / D converter 12 is not limited to the pipeline type, and is a successive approximation type with a low sampling rate (100 sps (sample per second) to about 2 Msps) and a low power consumption, and a high sampling rate (1 Msps). A flash type having a power consumption of about 80 Msps and a large power consumption may be employed. However, in the A / D conversion apparatus 100 of the present application, the A / D conversion processing for analog signals obtained from a plurality of channels is speeded up while achieving a reduction in circuit scale and power consumption to some extent. Therefore, it is preferable to adopt a pipeline type that has a medium to high sampling rate (about 1 Msps to 80 Msps) and consumes less power than a flash type.

  The A / D converter 12 is based on the A / D conversion control signal ADCLK generated by the timing signal generation circuit 15 and other A / D converters 12 in addition to the sample / hold timing in the sample / hold circuit 120. Internal operation timing is controlled.

  Based on the digital output selection signals SELAO to SELDO generated by the timing signal generation circuit 15, the digital output selection circuit 13 selects the digital signals D9 to D0 that are sequentially converted from the A / D converter 12 and output. To the corresponding register 14 for the channel.

  The register 14 temporarily holds the digital signals D9 to D0 selected by the digital output selection circuit 13. When all the digital signals DnA to DnD corresponding to the analog signals AINA to AIND are held in the register 14, the register 14 selects the digital signals DnA to DnA to DnA to DnA to DnA to DnA to DnA to DnA to DnA to DnA to DnA to DnA. DnD is output externally.

  The timing signal generation circuit 15 receives the sample hold control signal SHCLK, the analog input selection signals SELAI to SELDI, the A / D conversion control signal ADCLK, the digital output selection signals SELOA to SELDO, and the reference clock signal OCLK based on the reference clock signal CLKIN. Is to be generated. When the standby signal STBY is input, the internal analog circuit does not function and the digital output signals DnA to DnD are indefinite.

<Sample hold circuit>
FIG. 3 is a diagram showing the configuration of the sample and hold circuits 10a, 10b, 10c and 120 according to the embodiment of the present invention.

  Sample hold circuits 10a, 10b, 10c and 120 employ differential output amplifiers in order to improve A / D conversion accuracy. That is, the analog signals AINB to AIND input to the sample and hold circuits 10a, 10b, and 10c and the analog signal AIN input to the sample and hold circuit 120 become differential input signals AINP and AINM whose phases are inverted.

  The sample hold circuits 10a, 10b, 10c and 120 are supplied to the switch groups S1 and S1 ′ supplied with the differential input signal and the switch groups S2 and S2 ′ supplied with the reference voltage Vref based on the sample hold control signal. On the other hand, when one switch group is turned on, the other switch group is turned off.

  Here, when the switch groups S1 and S1 ′ are turned on and the switch groups S2 and S2 ′ are turned off, the differential input signals AINP and AIMM are supplied to one terminal of each of the capacitive elements C1 and C1 ′ and charged. This is a so-called sample mode. Subsequently, when the switch groups S1 and S1 ′ are turned off and the switch groups S2 and S2 ′ are turned on, the reference voltage Vref is supplied to one terminal of each of the capacitive elements C1 and C1 ′. Become.

  In the hold mode, based on the charge conservation law, the charges charged in the capacitive elements C1 and C1 ′ in the sample mode are stored between the capacitive elements C1 and C2, and between the capacitive elements C1 ′ and C2 The charge is transferred to and from '. As a result, the differential output amplifier has a difference according to the differential voltage between the differential output signal AINP ′ corresponding to the differential voltage between the reference voltage Vref and the differential input signal AINP, and the differential voltage between the reference voltage Vref and the differential input signal AINM. The dynamic output signal AINM ′ is output.

<A/D converter with built-in sample and hold circuit>
FIG. 4 is a diagram showing a configuration of the pipeline type A / D converter 12 including the sample hold circuit 120 according to the embodiment of the present invention. Note that the A / D converter 12 shown in FIG. 4 uses the 4-bit D9 to D6 and the 2-bit D5 to D4 for the 10-bit digital signals D9 to D0 that are finally generated as in the sub-ranging method. Assume that the data is generated in a total of four steps in the order of 2-bit D3 to D2 and 2-bit D1 to D0. The analog signals AINA to AIND are sequentially input to the A / D converter 12 as differential input signals AINP and AINM.

  First, in the first step, the differential input signals AINP and AINM are sampled and held in the sample-and-hold circuit 120 based on the A / D conversion control signal ADCLK, and quantized to 4-bit D9 to D6 in the 4-bit ADC 121a. It becomes. The quantized 4-bit D9 to D6 are converted into analog signals again in the 4-bit DAC 122a, and then the original differential input signals AINP and AINM and the 4-bit DAC 122a output sampled and held in the adder 123a. The differential analog signal is obtained. The quantized 4-bit D9 to D6 are propagated in the order of D-type flip-flops 125a, 125b, 125c, and 125d based on the A / D conversion control signal ADCLK and supplied to the digital output synthesis circuit 126. The

  In the second step, the output of the adder 123a (differential analog signal) obtained in the first step is amplified by the amplifier 124a and then quantized to the next two bits D5 to D4 in the 2-bit ADC 121b. The quantized 2-bit D5 to D4 are converted again into analog signals in the 2-bit DAC 122b, and then the difference between the adder 123a output further amplified in the amplifier 124b and the 2-bit DAC 122b output in the adder 123b. An analog signal is obtained. Also, the quantized 2-bit D5 to D4 are propagated in the order of D-type flip-flops 125e, 125f, and 125g based on the A / D conversion control signal ADCLK and supplied to the digital output synthesis circuit 126.

  In the third step, the output of the adder 123b (differential analog signal) obtained in the second step is amplified by the amplifier 124c and then quantized to the next 2-bit D3 to D2 by the 2-bit ADC 121c. The quantized 2-bit D3 to D2 are converted again to an analog signal in the 2-bit DAC 122c, and then, in the adder 123c, the difference between the output of the adder 123b further amplified in the amplifier 124d and the output of the 2-bit DAC 122c An analog signal is obtained. The quantized 2-bit D3 to D2 are propagated in the order of the D-type flip-flops 125h and 125i based on the A / D conversion control signal ADCLK and supplied to the digital output synthesis circuit 126.

  In the fourth step, the output of the adder 123c (differential analog signal) obtained in the third step is amplified by the amplifier 124e, and then quantized to the next 2-bit D1 to D0 by the 2-bit ADC 121d. The quantized 2-bit D1 to D0 are propagated to the D-type flip-flop 125j based on the A / D conversion control signal ADCLK and supplied to the digital output synthesis circuit 126.

  Through such first to fourth steps, the digital output synthesis circuit 126 is obtained in 4 bits D9 to D6 obtained in the first step, 2 bits D5 to D4 obtained in the second step, and in the third step. The 2-bit D3 to D2 and the 2-bit D1 to D0 obtained in the fourth step are combined to generate a 10-bit digital signal D9 to D0.

  A specific example of the operation of the A / D converter 12 will be described based on FIG. 5 with reference to FIG.

  In the first step, in the 4-bit ADC 121a, the input analog signal has a level corresponding to “1000” in the analog range divided by 16 (2 4) from the power supply potential VCC to the ground GND. “1000” is generated as the most significant 4 bits D9 to D6 of the 10-bit digital signal.

  In the second step, first, in the amplifier 124a, the analog range of the differential analog signal between the original analog signal and the analog signal obtained by D / A converting “1000” set in the first step is expanded. In the 2-bit ADC 121b, the differential analog signal has a level corresponding to “10” in the analog range divided by 4 (the square of 2). “10” is generated as D4.

  In the third step, first, in the amplifier 124c, the analog range of the differential analog signal between the differential analog signal in the second step and the analog signal obtained by D / A converting “10” set in the second step is expanded. . In the 2-bit ADC 121c, the differential analog signal has a level corresponding to “10” in the analog range divided by 4 (the square of 2). “10” is generated as D2.

  In the fourth step, first, in the amplifier 124e, the analog range of the differential analog signal between the differential analog signal in the third step and the analog signal obtained by D / A converting “10” set in the third step is expanded. . In the 2-bit ADC 121d, the differential analog signal has a level corresponding to “00” in the analog range divided by 4 (the square of 2), and therefore, the next 2 bits D1 to D1 after the 10-bit digital signal. “00” is generated as D0.

  As a result of performing the first to fourth steps, “1000101000” is generated as a 10-bit digital signal.

  The first to fourth steps are performed for each analog signal AINA to AIND that is sequentially input to the A / D converter 12 in accordance with the A / D conversion control signal ADCLK. For example, as shown in FIG. 6, in cycle 1 of the A / D conversion control signal ADCLK, the analog signal AINA is input to the A / D converter 12 and sampled and held in the sample and hold circuit 120, and the digital signal DnA D9 to D6 are generated.

  In the next cycle 2 of the A / D conversion control signal ADCLK, D5 to D4 of the digital signal DnA are generated and the analog signal AINB is input to the A / D converter 12, and the sample hold circuit 120 And D9 to D6 of the digital signal DnB are generated.

<Timing signal generation circuit>
Based on FIG. 7, the configuration of the timing signal generation circuit 15 according to an embodiment of the present invention will be described. An example of the waveform of each timing signal generated in the timing signal generation circuit 15 will be described with reference to FIG.

  The frequency dividing circuit 151 is composed of a two-stage D-type flip-flop circuit, and generates a frequency-divided by 2 and a frequency-divided inversion / non-inversion signal by dividing one cycle of the reference clock signal CLKIN. Note that the maximum frequency dividing number of the frequency dividing circuit 151 is not limited to the frequency dividing by 4, and is a number corresponding to the number of channels of the analog signal. In the frequency divider 151, when the standby signal STBY is supplied, the two-stage D-type flip-flop circuit is reset.

  The logic circuit 152 appropriately synthesizes the reference clock signal CLKIN and the divide-by-2 and divide-by-4 inverting / non-inverted signals generated by the dividing circuit 151 to thereby generate the A / D conversion control signal ADCLK, the sample hold The control signal SHCLK, the digital output selection signals SELAO to SELDO, and the reference clock signal OCLK are generated.

  The A / D conversion control signal ADCLK is generated as a pulse signal having the same frequency as that of the reference clock signal CLKIN. The sample hold control signal SHCLK is generated as a pulse signal having an H level section equal to the H level section of the A / D conversion control signal ADCLK every four cycles of the A / D conversion control signal ADCLK. That is, the frequency of the A / D conversion control signal ADCLK (the sampling frequency of the sample hold circuit 120) is the frequency of the sample hold control signal SHCLK (the sampling frequency of the sample hold circuits 10a, 10b, 10c) × the number of analog signal channels “4”. "Is set.

  Further, the digital output selection signals SELAO to SELDO are sequentially output from the A / D converter 12 in accordance with the output timings of the digital signals DnA to DnD, and sequentially in the H level interval for each cycle of the reference clock signal CLKIN. Is generated as a pulse signal. Therefore, the digital output selection circuit 13 can prevent the selection of the digital signals DnA to DnD from overlapping based on the digital output selection signals SELAO to SELDO.

  The reference clock signal OCLK is a signal obtained by delaying the digital output selection signal SELDO by a predetermined time (more than the time required for holding in the register 14). That is, when the digital output selection signal SELDO is in the H level section and a predetermined time has passed since then, all the digital signals DnA to DnD are held in the register 14 and the digital signals DnA to DnD can be output from the A / D converter 100. It is because it will be in a state.

  The shift register 153 is composed of four stages of D-type flip-flops. Based on the reference clock signal CLKIN, the shift register 153 generates a synthesized signal of the divide-by-2 and divide-by-4 / inverted / non-inverted signals generated by the divider circuit 151. shift.

  The logic circuit 154 generates analog input selection signals SELAI to SELDI by appropriately combining the respective bit outputs of the shift register 153.

  The analog input selection signals SELAI to SELDI are generated as pulse signals indicating the H level section in order for each period of the reference clock signal CLKIN. Therefore, the analog input selection circuit 11 can prevent the selection of the analog signals AINA to AIND from overlapping based on the analog input selection signals SELAI to SELDI.

<Overall Operation of A / D Converter>
The overall operation of the A / D conversion apparatus 100 according to an embodiment of the present invention will be described with reference to FIG.

  First, it is assumed that the analog signals AINA to AIND are input to the A / D converter 100 in the first cycle 1 based on the reference clock signal CLKIN. Since the analog input selection signal SELAI is in the H level section, the analog signal AINA to be processed first in the A / D converter 12 is selected in the analog input selection circuit 11, and the sample hold of the A / D converter 12 is performed. This is supplied to the circuit 120. The sample hold circuit 120 samples and holds the analog signal AINA based on the sampling timing of the analog signal AINA (falling edge of the A / D conversion control signal ADCLK).

  In parallel with the sampling of the analog signal AINA in the sample and hold circuit 120, analog signals AINB to AIND to be processed second and later in the A / D converter 12 are supplied to the sample and hold circuits 10a, 10b, and 10c. The Then, in the sample hold circuits 10a, 10b, and 10c, based on the sampling timing of the analog signals AINB to AIND (falling edge of the sample hold control signal SHCLK), the batch sample hold of the analog signals AINB to AIND is performed on the analog signal AINA. This is done at the same time as the sample hold.

  The A / D conversion control signal ADCLK and the sample hold control signal SHCLK are generated from the same reference clock signal CLKIN, and thus are synchronized. For this reason, the sampling timing of the analog signal AINA in the sample hold circuit 120 and the sampling timing of the analog signals AINB to AIND in each of the sample hold circuits 10a, 10b, and 10c are synchronized. That is, the analog signals AINA to AIND for the total number of channels are sampled all together in a predetermined sample and hold circuit.

  In cycles 2 to 4 after cycle 1, the analog input selection signals SELBI to SELDI are sequentially set to the H level section, and the analog signals AINB to AIND that are collectively sample-held in the sample hold circuits 10a, 10b, and 10c are analog. The input selection circuit 11 sequentially selects them. Then, the analog signals AINB to AIND that are sequentially selected are sequentially supplied to the sample hold circuit 120 of the A / D converter 12, and are sequentially sampled and held based on the A / D conversion control signal ADCLK.

  Incidentally, the A / D converter 12 sequentially performs A / D conversion processing of the analog signals AINA to AIND in a pipeline manner. Therefore, after a predetermined time required for A / D conversion has elapsed since the analog signals AINA to AIND were supplied to the A / D converter 12, for example, in cycle 7, the digital signal DnA corresponding to the analog signal AINA, in cycle 8, A digital signal DnB corresponding to the analog signal AINB, a digital signal DnC corresponding to the analog signal AINC in the cycle 9, and a digital signal DnD corresponding to the analog signal AIND in the cycle 10 are output from the A / D converter 12.

  Here, in cycles 7 to 10, the digital output selection signals SELAO to SELDO are sequentially set to the H level section, and the digital signals DnA to DnD are sequentially selected in the digital output selection circuit 13 and temporarily held in the register 14. . As a result, in the cycle 10, all the digital signals DnA to DnD are held in the register 14, and are output from the register 14 to the outside of the A / D converter 100 based on the reference clock signal OCLK. is there.

=== Terrestrial digital broadcast receiver ===
As an example of a digital control system incorporating the A / D conversion apparatus 100 according to the present invention, a terrestrial digital broadcast receiving apparatus 200 for portable terminals is illustrated based on FIG. The terrestrial digital broadcast receiving apparatus 200 is an embodiment of the “receiving apparatus” according to the present invention.

  The terrestrial digital broadcast receiving apparatus 200 shown in FIG. 9 employs an Orthogonal Frequency Division Multiplexing (OFDM) system, a direct conversion system, and a diversity system.

  The OFDM scheme is one of multicarrier transmission schemes, in which a plurality of carriers orthogonal to each other are generated and arranged in a transmission band of one channel, and QPSK (Quadrature Modulation: Quadrature) is applied to each carrier. Phase shift keying) and 16QAM (Quadrature Amplitude Modulation). This OFDM system is excellent in transmission characteristics in a multipath environment, and its adoption is determined as a transmission system for terrestrial digital broadcasting.

  The direct conversion system is a system that processes a received high-frequency signal by directly converting the frequency into a baseband signal. Compared with a superheterodyne receiver that directly converts a received high-frequency signal to an intermediate frequency and processes it, a direct-conversion receiver does not require a circuit for processing a frequency conversion from a high-frequency signal to an intermediate frequency. Therefore, the circuit scale is small and the cost is low, and it is suitable for the multicarrier transmission system.

  The diversity method uses the fact that the reception state changes depending on the antenna position. For example, a signal processing system for each signal received by each of the plurality of antennas is provided in advance, and signal processing is performed according to the reception state. It is a method of switching systems. Alternatively, the diversity method may be a method in which only a plurality of antennas are provided and only the antennas are switched according to the reception state.

  Next, the configuration of the terrestrial digital broadcast receiving apparatus 200 will be described. The mixer circuits 204a, 204b, 204c, and 204d, the 90 ° phase shifters 205a and 205b, and the local oscillator 206 are an embodiment of the “frequency converter in the receiving device” according to the present invention. A / D conversion device 100 is an embodiment of an “A / D conversion unit in a receiving device” according to the present invention. Furthermore, OFDM demodulating section 208, deinterleaving processing section 209, and error correction processing section 210 are an embodiment of the “demodulation processing section in the receiving apparatus” according to the present invention.

  First, the high-frequency signals received by the antennas 201a and 201b are respectively supplied to the mixer circuits 204a, 204b, 204c, and the band-pass filters 202a and 202b and the low noise amplifiers 203a and 203b. 204d as one input. As the other input of the mixer circuits 204a and 204c, the local oscillation signal generated in the local oscillator 206 is supplied via the 90 ° phase shifters 205a and 205b, and the other input of the mixer circuits 204b and 204d is as follows. The local oscillation signal generated in the local oscillator 206 is directly supplied.

  In the mixer circuits 204b and 204d, an in-phase component I (hereinafter, I signal) of the baseband signal is obtained by mixing a local oscillation signal having a phase difference of 0 ° with an input high frequency signal. In the mixer circuits 204a and 204c, a quadrature component Q (hereinafter referred to as Q signal) of the baseband signal is obtained by mixing a local oscillation signal having a phase difference of 90 ° with an input high frequency signal. The I signal obtained by the mixer circuits 204b and 204d is supplied to a low pass filter (Low Pass Filter) 207b and 207d, and the Q signal obtained by the mixer circuits 204a and 204c is supplied to a low pass filter 207a and 207c. As a result, only frequency components that are ½ or less of the sampling frequency are extracted, and unnecessary signal components and noise other than the reception channel are removed.

  The A / D conversion apparatus 100 is an “A / D conversion apparatus” according to the present invention described above, and each of the signals AINA to AIND obtained from the low-pass filters 207a, 207b, 207c, and 207d is converted into a digital signal having a predetermined number of bits. The signals are converted into signals DnA to DnD. In this conversion, the sample and hold circuit 120 samples and holds the analog signal AINA to be processed first, and at the same time, the three sample and hold circuits 10a, 10b, and 10c perform the second. Thereafter, sample hold of the analog signals AINB to AIND to be processed is performed in a lump.

  The OFDM demodulator 208 subjects the digital signals DnA to DnD converted by the A / D converter 100 to OFDM demodulation processing according to the OFDM scheme. The OFDM demodulation processing includes, for example, processing for converting time axis data to frequency axis data by QPSK or 16QAM demodulation or fast Fourier transform.

  The deinterleave processing unit 209 performs a deinterleave process such as a frequency deinterleave process and a time deinterleave process on the signal subjected to the OFDM demodulation process. Note that the frequency deinterleaving process is a process for restoring frequency interleaving performed to compensate for signal loss at a specific frequency due to radio wave reflection or the like. The time deinterleaving process is a process for restoring the time interleaving performed for fading countermeasures and the like.

  The error correction processing unit 210 performs error correction processing by Viterbi decoding or Reed-Solomon code on the signal that has been subjected to deinterleaving processing.

  The signal subjected to the error correction processing is decompressed by the video / audio decoder 211 by the MPEG (Moving Picture Experts Group) decoding processing or the like, and the video / audio digital data is restored. The video / audio digital data is converted into video / audio analog data via a D / A converter (not shown), and then the video analog data is displayed on an LCD (Liquid Crystal Display) monitor 212 or the like. The audio analog data is output to the speaker 213 and the like.

=== Examples of effects ===
In a conventional A / D converter, when analog signals obtained from n (n is a natural number of 2 or more) channels are sequentially converted into digital signals, each analog signal is temporarily sampled and held. It must be sampled and held in the circuit.

  On the other hand, in the A / D conversion device 100 according to the present invention, an analog signal is obtained from n channels by focusing on one sample hold circuit 120 originally included in one A / D converter 12 itself. Sometimes, the sample and hold circuit 120 performs sample and hold of an analog signal to be processed first. At the same time, in the n-1 sample and hold circuits (10a, 10b, 10c, etc.) provided as peripheral circuits of the A / D converter 12, the sample and hold of the analog signal to be processed after the second is held. It is done in a lump.

  Therefore, according to the A / D conversion device 100 according to the present invention, the first analog signal to be processed obtained from the channel is not subjected to the sample hold circuit (10a, 10b, 10c, etc.), and is A / D converted. The sample and hold circuit 120 originally built in the device 12 quickly samples and holds, and as a result, the A / D conversion process is performed quickly. In other words, according to the A / D converter according to the present invention, the existing A / D converter 12 itself can be effectively utilized by using the sample-and-hold circuit 120 originally incorporated in the A / D converter 12. Without any improvement, it is possible to efficiently and quickly sample and hold analog signals respectively obtained from n channels.

  In addition, the A / D conversion apparatus 100 according to the present invention is simply configured as n peripheral circuits of the A / D converter 12 in order to perform A / D conversion processing on analog signals obtained from n channels, for example. After providing sample and hold circuits (10a, 10b, 10c, etc.), n sample and hold circuits (10a, 10b) are processed in the same way as analog signals to be processed first and second analog signals to be processed. 10c, etc.) will be compared with the case where the sample hold is performed collectively (comparative example).

  First, in the comparative example, the first analog signal to be processed is 1 in any one of n sample hold circuits (10a, 10b, 10c, etc.) as n peripheral circuits of the A / D converter 12. After the second sample hold, the A / D conversion process is performed after the second sample hold is performed in the sample hold circuit 120 originally included in the A / D converter 12. Similarly, the second analog signal to be processed is sampled and held twice in the sample-and-hold circuit (10a, 10b, 10c, etc.) and the sample-and-hold circuit 120 originally incorporated in the A / D converter 12. .

  That is, in the case of the comparative example, a total of 1 cycle in n sample hold circuits (10a, 10b, 10c, etc.) and n cycles for the number of channels in the sample hold circuit 120 originally incorporated in the A / D converter 12. (1 + n) cycles are required. Here, the A / D converter 12 takes in one analog signal in one cycle, and outputs one digital signal after a predetermined A / D conversion processing time has elapsed. Therefore, when an analog signal corresponding to the total number of channels is taken in by the A / D converter 12, a period in which the analog input signal or digital output signal of the A / D converter 12 is invalid is required when a cycle longer than the total number of channels is required Will occur.

  On the other hand, in the A / D conversion apparatus 100 according to the present invention, the first sample hold of the analog signal to be processed is performed only once in the sample hold circuit 120 originally incorporated in the A / D converter 12. The analog signal to be processed after the second is sampled and held in the sample-and-hold circuit 120 built in the A / D converter 12, and n−1 sample-and-hold circuits (10a, 10b, 10c etc.), sample hold is performed all at once.

  Therefore, according to the A / D converter 100 according to the present invention, when the A / D converter 12 takes in the analog signals for the total number of channels, n cycles for the total number of channels may be required. An invalid period does not occur in the analog input signal or digital output signal of the / D converter 12, and the A / D conversion process is efficiently performed. Compared to the case of the comparative example, the time required to sample and hold analog signals obtained from n channels can be shortened, and the A / D conversion processing after the sample and hold can be quickly performed.

  In the A / D conversion device 100 according to the present invention, the sampling frequency (frequency of the A / D conversion control signal) in the sample hold circuit 120 is changed to the sampling frequency (sample hold in the sample hold circuit (10a, 10b, 10c, etc.)). If the frequency is set higher than the frequency of the control signal SHCLK), the sample hold in the sample hold circuit 120 and the subsequent A / D conversion process until the sample hold in the sample hold circuit (10a, 10b, 10c, etc.) is completed. Can be completed in advance. Therefore, the sample and hold of the analog signal to be processed after the second in the sample and hold circuit 120 and the subsequent A / D conversion process can be performed efficiently.

  In the A / D conversion device 100 according to the present invention, preferably, the sampling frequency in the sample hold circuit 120 is set to n times the number of channels of the sampling frequency in the sample hold circuit (10a, 10b, 10c, etc.). For example, the sample and hold of the analog signal to be processed first in the sample and hold circuit 120 can be performed at an appropriate timing without being too fast and too late.

  Further, in the A / D converter 100 according to the present invention, the pipeline type A / D converter 12 is adopted among all existing A / D converters (for example, successive approximation type, flash type, etc.). Is preferable in terms of balance of power consumption, circuit scale, and speedup.

  Further, in the terrestrial digital broadcast receiving apparatus 200 incorporating the A / D conversion apparatus 100 according to the present invention, when converting each analog signal for a plurality of channels obtained from the received signal into a digital signal, the plurality of channels Minutes of analog signal sample and hold can be shortened. As a result, it can be said that the terrestrial digital broadcast receiving apparatus 200 can improve the performance of the terrestrial digital broadcast receiving apparatus 200 in view of the fact that analog signals in various frequency bands are handled.

  Although the present embodiment has been described above, the above-described examples are for facilitating the understanding of the present invention, and are not intended to limit the present invention. The present invention can be changed / improved without departing from the spirit thereof, and the present invention includes equivalents thereof.

It is a figure which shows the input / output signal specification of the A / D converter which concerns on one Embodiment of this invention. It is a figure which shows the structure of the A / D converter which concerns on one Embodiment of this invention. It is a figure which shows the structure of the sample hold circuit which concerns on one Embodiment of this invention. It is a figure which shows the structure of the pipeline type A / D converter which concerns on one Embodiment of this invention. It is a figure explaining operation | movement of the pipeline type A / D converter which concerns on one Embodiment of this invention. It is a figure explaining operation | movement of the pipeline type A / D converter which concerns on one Embodiment of this invention. It is a figure which shows the structure of the timing signal generation circuit which concerns on one Embodiment of this invention. It is a figure explaining operation | movement of the A / D converter which concerns on one Embodiment of this invention. It is a figure which shows the structure of the digital broadcast receiver which concerns on one Embodiment of this invention.

Explanation of symbols

100 A / D converters 10a, 10b, 10c Sample hold circuit 11 Analog input selection circuit 12 A / D converter 120 Sample hold circuits 121a, 121b, 121c, 121d ADC
122a, 122b, 122c, DAC
123a, 123b, 123c Adders 124a, 124b, 124c, 124d, 124e Amplifiers 125a, 125b, 125c, 125d, 125e, 125f, 125g, 125h, 125i, 125j D-type flip-flop 126 Digital output synthesis circuit 13 Digital output selection circuit 14 register 15 timing signal generation circuit 151 frequency dividing circuit 152 logic circuit 153 shift register 154 logic circuit 201a, 201b antenna 202a, 202b band pass filter 203a, 203b low noise amplifier 204a, 204b, 204c, 204d mixer circuit 205a, 205b 90 ° Phase shifter 206 Local oscillators 207a, 207b, 207c, 207d Low pass filter 208 OFDM demodulator 209 Deinterleave processor 210 Error Positive processing unit 211 video / audio decoder 212 LCD monitor 213 speaker

Claims (5)

In an A / D conversion device that samples and holds analog signals respectively obtained from n (n is a natural number of 2 or more) channels and converts them into digital signals,
One A / D converter containing one first sample and hold circuit;
The A / D conversion obtained from each of the n-1 channels in parallel with the first sample hold circuit sampling and holding the analog signal to be processed first by the A / D converter. N-1 second sample and hold circuits that collectively sample and hold the analog signals to be processed by the second to nth units ,
The A / D conversion of the analog signal to be processed first by the A / D converter and the analog signal collectively sampled and held by the second sample and hold circuit, obtained from one channel. An analog signal selection circuit that sequentially selects and supplies to the A / D converter according to the processing order in the device ,
The A / D converter samples and holds the first analog signal selected by the analog signal selection circuit in the first sample hold circuit, and then sequentially selects the second to nth analog signals in the analog signal selection circuit. Sequentially sample and hold the analog signals to be processed in the first sample and hold circuit ;
An A / D converter characterized by the above. Wherein the sampling frequency of the first sample-and-hold circuit, it is set higher than the sampling frequency in the second sample and hold circuit, A / D converter according to claim 1, characterized in. Wherein the sampling frequency of the first sample-and-hold circuit, it is set to n times the sampling frequency in the second sample and hold circuit, A / D converter according to claim 2, characterized in. The A / D converter is a pipeline type A / D converter that performs A / D conversion of analog signals sequentially selected by the analog signal selection circuit in a pipeline manner. 4. The A / D conversion device according to any one of 3 . A frequency conversion unit that performs frequency conversion on the received signal to obtain n (n is a natural number of 2 or more) frequency components from the received signal, and samples and holds an analog signal corresponding to each of the n frequency components. In a receiving apparatus having an A / D conversion unit that converts the digital signal into a digital signal and a demodulation processing unit that performs a predetermined demodulation process on the digital signal,
The A / D converter is
One A / D converter containing one first sample and hold circuit;
The A / D converter in parallel with the sample-hold in the first sample-and-hold circuit to an analog signal to be processed first, each from the n-1 of the channel 's obtained, the A / D converter N-1 second sample and hold circuits that collectively sample and hold the analog signals to be processed by the second to nth units ,
The A / D conversion of the analog signal to be processed first by the A / D converter and the analog signal collectively sampled and held by the second sample and hold circuit, obtained from one channel. An analog signal selection circuit that sequentially selects and supplies to the A / D converter according to the processing order in the device ,
The A / D converter samples and holds the first analog signal selected in the analog signal selection circuit in the first sample and hold circuit, and then sequentially selects the second to nth in the analog signal selection circuit. Sequentially sample and hold the analog signals to be processed in the first sample and hold circuit ;
A receiving device.

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