JP4843347B2 - Receiving system - Google Patents

Description

  The present invention relates to a receiving system having an AD converter, and more particularly to a receiving system in which a wide dynamic range is provided for AD conversion in a communication system using a digital modulation method for digital signal processing of an output of the AD converter.

  In recent digital mobile communication reception systems, in order to reduce the number of components, a direct conversion system that directly converts RF into a baseband is often employed.

  2 and 3 are diagrams showing a configuration example of the direct conversion method. The direct conversion method is roughly divided into two arrangements of channel selection filters, one of which is as shown in FIG. 2 in which the channel selection filter is constituted by an analog circuit and is converted into an AD converter. As shown in FIG. 3, the other is a case where a digital filter is used behind the AD converter. In order to cope with higher data rates, it is necessary to provide a roll-off characteristic with high accuracy as a channel selection filter. The configuration is suitable.

In FIG. 2, a quadrature-modulated signal is received by an antenna 12, passed through only a desired band by a surface acoustic wave filter (SAW) 13, amplified by a low noise amplifier 14, and a carrier frequency signal from a local oscillator 17 Is supplied to a quadrature demodulator (15a, 15b) of I (In-phase) and Q (Quadrature-phase) via a phase shifter 16. The quadrature demodulated received signals S _a and S _b are band-limited by the analog low-pass filters 18 a and 18 b, AD-converted by the AD converters 2 a and 2 b, and passed to the digital baseband processing unit.

In FIG. 3, the orthogonally demodulated received signals S _a and S _b pass through anti-aliasing filters (AAF) 1a and 1b, respectively, and then include interference waves by the wide dynamic range AD converters 2a and 2b. A / D conversion is performed and the band is limited by the digital low-pass filters 19a and 19b. The digitized reception data is transferred to the digital baseband processing unit.

  2 and 3, a variable gain amplifier (VGA) capable of switching the gain in accordance with the received signal level at the high-frequency signal stage in order to prevent the dynamic range required for AD conversion from becoming unnecessarily large. Is usually omitted here.

  When the channel selection filter is realized by a digital filter as shown in FIG. 3, the band limitation before the AD converter may be the minimum necessary mainly for the purpose of preventing aliasing. Since a wave can be input to an AD converter without being attenuated, a wide dynamic range characteristic is required for AD conversion.

  In order to reduce costs and improve performance, a reception system using a combination of a ΣΔ AD converter and digital signal processing, which is advantageous for digitization when the symbol rate is relatively low, has been proposed ( For example, refer nonpatent literature 1). In this ΣΔ type AD converter, oversampling is executed at a frequency several to several tens of times the symbol rate unique to the applied communication system.

Robert HM van Veldhoven, et.al., A 3.3-mW ΣΔ Modulator for UMTS in 0.18-microm CMOS With 70-dB Dynamic Range in 2-MHz Bandwidth, IEEE J. Solid State Circuits, VOL.37, No.12 , December 2002, pp1645-1652

  When the channel selection filter is composed of a digital filter, as described above, it is necessary to have a wide dynamic range for AD conversion. The sample rate of the AD converter should be a multiple (usually an integral multiple) of the symbol rate (for example, 3.84 MHz in the case of UMTS) unique to the applied communication system for the convenience of subsequent digital signal processing. In general, a sampling clock generated by using a PLL from a reference clock generated by a temperature-compensated crystal oscillator (hereinafter referred to as TCXO) is used.

  At this time, from a technical point of view, the TCXO oscillation frequency should be determined in consideration of the system-specific symbol rate, chip rate, and ease of PLL creation. Depending on the requirements of the system, it is desired that the oscillation frequency be different from the frequency seen from the technical point of view according to different requirements.

  Also, depending on the TCXO oscillation frequency, when generating a system-specific symbol rate multiplied clock in the PLL, the comparison reference frequency becomes lower, the loop bandwidth becomes narrower, and the phase noise generated by the PLL internal circuit itself may be reduced. It may be output to the clock without being sufficiently suppressed, and as a result, the jitter characteristics of the sampling clock of the AD converter may deteriorate.

On the other hand, in general, when the AD converter samples (samples) an input signal, jitter included in the sampling clock generates so-called noise (a signal component different from the original signal). In the n-bit AD converter, the S / N ratio when the jitter (RMS value) included in the sampling clock is σ _tj is

It becomes. Here, fin is the frequency of the input signal. That is, if the jitter characteristics of the sampling clock are bad, there is a problem that the limit dynamic range in AD conversion becomes narrow by itself.

  In view of the above points, the present invention has a wide dynamic range with at least little clock jitter even under conditions where a desired low jitter clock cannot be produced at a frequency multiplied by the symbol rate inherent to the system due to restrictions on the reference clock that can be used. It is an object of the present invention to provide a high-accuracy receiving system comprising an AD converter and a digital signal processor. In other words, it is an object of the present invention to provide a receiving system that can configure an AD conversion unit with a wide dynamic range with little clock jitter without being restricted by a frequency unique to the receiving system.

In order to solve the above problems and achieve the object of the present invention, the invention of claim 1 is a communication system using digital modulation, wherein an input signal is an arbitrary frequency different from an integer multiple of a symbol rate of the input signal. An A / D converter that samples at a sample rate, a digital signal processing unit that receives the output of the A / D converter and executes a process mainly for filtering at the sample rate, and the digital signal processing A sample rate converter that receives the output from the unit at the sample rate and converts it into a data string at a rate of a frequency multiplied by the symbol rate of the input signal, the sample rate converter comprising: For the output from the signal processing unit, calculate a value obtained by dividing N between two data (N is an integer of 2 or more) A value obtained by rounding off the fractional portion of the ratio between the rate of N times the sample rate and the rate of the symbol rate multiplied by the linear interpolator that creates a data string having a rate N times the sample rate A rate that is N times the sample rate such that the average rate is the rate of the multiplied frequency of the symbol rate. And a decimator for thinning out data from the data sequence and generating the data sequence at the rate of the symbol rate multiplied by the frequency . By using the sample rate converter in this manner, the sampling clock of the AD converter does not need to be a frequency multiplied by the symbol rate unique to the communication system, and the usable reference clock or the symbol symbol unique to the system can be used. Any frequency that is easy to achieve low jitter in the PLL can be applied as the sampling clock of the AD converter without being restricted by the rate, and as a result, high precision consisting of AD conversion with a wide dynamic range and digital signal processing The receiving system can be realized.

The invention according to claim 2 is the receiving system according to claim 1, wherein the digital signal processing unit arranged in front of the sample rate converter has an FIR having a root Nyquist roll-off characteristic. With a filter,
The output of the AD converter is sent to the sample rate converter via the FIR filter. As a result, it is possible to prevent a disturbing wave component included in the output signal of the AD converter from being turned back into the signal band by the sample rate conversion, and to realize a high-accuracy receiving system with small intersymbol interference.

Furthermore, the invention of claim 3 is the receiving system according to claim 1 or 2 , wherein the input signal used in a digital baseband processing unit at a subsequent stage is received by the output of the sample rate converter. Buffer means for outputting data synchronized with a clock having a frequency multiplied by a symbol rate is further provided, and the sample rate converter generates data for a rate of a frequency multiplied by a symbol rate of the input signal. It is what. As a result, it is possible to prevent the failure of the data delivery timing due to the phase shift.

  As described above, the receiving system of the present invention can operate the AD converter with a clock having an arbitrary frequency with low jitter, and therefore, there are restrictions on the usable reference clock and the symbol rate specific to the system to be applied. Regardless, it is possible to realize a high-accuracy receiving system including a wide dynamic range AD converter and a digital signal processing unit. In other words, the difficulty in realizing the required specifications related to the jitter characteristics of the PLL that generates the sampling clock of the AD converter can be greatly reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 4 is a diagram showing a schematic configuration of a direct conversion system receiving system to which the present invention is applied. The configuration shown in FIG. 4 is different from the configuration shown in FIG. 3 described above in that a sample rate converter (SRC) is provided between the digital low-pass filters 19a and 19b and the digital baseband processing section. 6a and 6b are provided.

  FIG. 1 is a diagram showing in more detail the operation after orthogonal demodulation of the receiving system using the direct conversion method according to the present invention shown in FIG.

First, the operation of the receiving system in the embodiment of the present invention will be described with reference to FIG. As shown in FIG. 1, in the receiving system according to the present invention, the orthogonally demodulated received signals S _a and S _b pass through anti-aliasing filters 1a and 1b, respectively, and then are converted by AD converters 2a and 2b having a wide dynamic range. A / D conversion is performed while the interference wave is included, and the band is limited by the digital low-pass filters 19a and 19b. When the digitized received data is transferred to the digital baseband processing unit, the sample rate of the AD converters 2a and 2b is not necessarily a digital base because it passes through the sample rate converters 6a and 6b. It is not necessary to multiply the clock rate of the band processing unit 11, that is, the symbol rate unique to the communication system. Therefore, it is possible to set the sampling clock of the AD converter to any frequency suitable for realizing a wide dynamic range, and at the same time, use an oscillator that meets the procurement cost and other system requirements. Is possible.

  The details of the present invention will be further described with reference to FIG. In the receiving system shown in FIG. 1, portions corresponding to the digital low-pass filters 19a and 19b immediately after the AD converter in FIG. 4 are FIR filters 3a and 3b having root Nyquist roll-off characteristics. Thereby, the interference wave component can be sufficiently attenuated and good symbol timing reproduction can be performed. Here, the operating frequency of the FIR filter is not a multiplication of the symbol rate inherent in the system, but is a clock rate of the sampling rate. However, this clock rate is usually sufficiently higher than the symbol rate. Since digital filters can achieve arbitrary filter characteristics by selecting appropriate coefficients, it is easy to realize root Nyquist roll-off characteristics corresponding to the system specific symbol rate. is there.

  The sample rate converter 6 shown in FIG. 1 is composed of linear interpolators 7a and 7b, decimators 8a and 8b, and a small-scale timing generation circuit 9, so that power consumption and area are not increased. Realized.

  Here, as an example, the operation principle will be described with reference to FIG. 1, taking as an example the case where this receiving system is applied to a UMTS (Universal Mobile Telecommunications System) receiver.

  The reference clock used for the UMTS receiver is often a 26 MHz TCXO widely used in GSM (Global System for Mobile communication) systems. Using this 26 MHz clock as a reference, for example, 52 MHz is generated by a PLL, and this is used as a sampling clock for the AD converter and an operation clock for the root Nyquist filter. Since this is twice the frequency of 26 MHz, the PLL loop band can be widened, so that a low jitter clock can be easily realized.

Next, for example, 8 times linear interpolation is performed on the root Nyquist filter outputs S _3a and S _3b , and then decimation is performed. In this case, since the calculation of the linear interpolation only needs to calculate a value obtained by dividing the two data into eight, eight times as many clocks (416 MHz) are not required. Assuming that the n-th root Nyquist filter output S _3a of the I channel is D _n (n = 0, 2, 3,...), The linear interpolation result S 4a is
_{D n (k) = D n} + k * (D n + 1 -D n) / 8 Equation 1
Where n is 0, 1, 2,... Representing the serial number of data in sampling clock units, and k is the serial number 0 to 7 of data interpolated between the data, as follows: Can be represented.
D _{0 (0)} , D _{0 (1)} , ..., D _{0 (7)} , D _{1 (0)} , ... D _{1 (7)} , D _{2 (0)} , ... D _{2 (7)} , ...
By doing so, a data string of a rate of 52 MHz * 8 = 416 MHz is obtained in a pseudo manner.

  The following description will be made only for the I channel, but it goes without saying that the same applies to the Q channel.

  Generally, N times linear interpolation is accompanied by a filter effect expressed by the following equation.

  Since the linear interpolation of 8 times has a filter characteristic as shown in FIG. 5, the spectrum of the signal component of the data string of the rate of 52 MHz * 8 = 416 MHz obtained in a pseudo manner is affected. However, in this case, the frequency of 52 MHz is sufficiently higher than 1.92 MHz, which is the Nyquist frequency (1/2 of the system-specific symbol rate) in UMTS, and the attenuation at the frequency of 1.92 MHz is about −0. It is only 0.02 dB, and its influence (by the spectrum in FIG. 5) is very small, and it is known that there is almost no deterioration in demodulation performance.

  Assuming that the digital baseband processing unit in the subsequent stage expects received data to be input at 15.36 MHz (4 times the symbol rate 3.84 MHz), data equivalent to the pseudo 416 MHz rate Consider extracting data from a sequence with a decimator to create a 15.36 MHz rate data sequence. 416 MHz is approximately 27.08 times 15.36 MHz, and is not an integral multiple, and cannot be realized by thinning out at equal intervals. Therefore, it is considered that the average rate is 15.36 MHz by combining the 27 sample interval and the 28 sample interval. The following formula shows the specific method.

That is, the data sequence for 12 samples at the 15.36 MHz rate can be obtained by repeatedly extracting 11 samples from the 416 MHz rate data sequence every 27 samples and extracting only the data of the 12th sample at 28 sample intervals. Recognize. Thus as the decimator output S _5a, for example, it is sufficient to the data string as shown in FIG.

  In FIG. 6, the sequence of numbers representing the serial number of data in sampling clock units is 0, 3, 6, 10, 13,..., And the difference is 3, 3, 4, 3, ... Since 52 MHz is about 3.4 times 15.36 MHz, the extracted data can be output at a rate of 15.36 MHz in a pseudo manner by combining three or four cycle intervals of the 52 MHz clock edge. Is possible. An example of such decimator output timing is shown in FIG. The timing at which the output data is calculated at this time is different from the original timing required for the extracted data, but as long as the average rate is exactly 15.36 MHz, No problem at all.

  It should be noted that when a part of the data string is extracted from the data string and the data rate is lowered, an unnecessary component (an out-of-band component, that is, in this case, a Nyquist frequency equal to or more than half of 15.36 MHz). 1), a low-pass filter is prepared in order to prevent performance degradation caused by folding back into the signal band (the Nyquist frequency described above). In the example shown in FIG. 1, the root Nyquist filter plays this role. In addition, the aliasing component generated by linear interpolation is sufficiently suppressed by the filter characteristics of the linear interpolation itself (Equation 1 above), so it is sufficient to not prepare a low-pass filter again. High demodulation accuracy can be obtained.

  As shown in FIG. 7, the data string obtained in this way is a pseudo 15.36 MHz rate data string whose calculation interval is not constant. The FIFO (10a, 10b) in FIG. 1 has a function for inputting such a signal and transferring the data to the subsequent digital baseband unit in an equal cycle without excess or deficiency. As shown in FIG. 7, this FIFO writing is performed by an interval sampling clock (in the example, 52 MHz clock), and reading from this FIFO is performed by the digital baseband processing unit clock (as illustrated in FIG. 7). In this case, 15.36 MHz).

  Since 15.36 MHz, which is a clock (or frequency-divided one) used in the digital baseband processing unit at the subsequent stage, is normally generated based on the same TCXO, the above-mentioned pseudo frequency is used as the average frequency. Since it is completely coincident with 15.36 MHz, it is possible to establish continuous data transfer by providing a certain number of stages in the FIFO and starting reading after writing to half of the number of stages Become.

  Instead of the FIFO, a RAM that can be controlled independently from the writing side and the reading side can be used, and a general RAM can also be used.

  As can be seen from the above, the receiving system according to the present invention can select the sample frequency of the AD converter without being restricted by the data rate specific to the applied system. A sampling clock for a low jitter AD converter can be easily generated by a PLL having a wide loop band by arbitrarily selecting a sample frequency. Therefore, a high-accuracy reception system (using an AD converter) having a wide dynamic range can be realized. Also, by adopting a combination of substantially high oversampling and non-equal-space decimation by linear interpolation as sample rate conversion means, sample rate conversion differs from sampling clock. A high-frequency operation clock is not required, thereby avoiding an increase in power consumption due to the high clock circuit.

  Here, the case where the present invention is applied to a direct conversion method in which a received high frequency signal is multiplied by a local signal of the same frequency and directly converted into a baseband signal has been described as an example. However, in the above-described configuration, the received high-frequency signal is multiplied by a local signal having a different frequency (1st local) and once dropped to an intermediate frequency, and then further multiplied by the local signal having the intermediate frequency (2nd local). It can also be applied to a superheterodyne system for converting to a signal, or a low IF system in which a relatively low frequency is adopted as the 2nd local and AD conversion is performed with an intermediate frequency and then converted to a baseband signal by digital multiplication. .

  As the sample rate converter, it is also possible to apply not the linear interpolation but the sample-and-hold interpolation that interpolates by inserting the same data as the actual data. However, in this case, since the filtering effect of the aliasing signal is reduced, there is a disadvantage that the noise component included in the data after the sample rate conversion is increased. Alternatively, zero interpolation that interpolates by inserting zero can be applied, but in this case, a low-pass filter is separately required. Further, instead of linear interpolation using two samples, interpolation calculated using two or more samples can also be used. In this case, the same effect can be obtained with the configuration of the above-described embodiment. However, there is a drawback that the configuration of interpolation is complicated.

  A configuration in which the sample rate converter is arranged in front of the root Nyquist filter is also conceivable. In this case, the above-mentioned problems can be solved and the operation clock of the root Nyquist filter can be lowered, but in order to prevent the interference wave from turning back into the band due to the sample rate conversion, Since a separate low-pass filter is required immediately before the sample rate converter, the filter characteristic becomes redundant, and conversely, there is a possibility of increasing power consumption.

  The present invention is suitable as a receiving system for digital mobile communication, which requires particularly high-precision demodulation performance.

According to the embodiment of the present invention, a root Nyquist filter is arranged behind an AD converter, a sample rate converter using linear interpolation, and a direct buffer applying a FIFO as data buffering means. It is a figure which shows the structure of the part after a quadrature demodulator of a conversion system receiving system. It is a figure which shows the structure of the direct conversion system receiving system in the case of comprising the reception filter for band limitation with an analog circuit, and placing it in front of the AD converter. It is a figure which shows the structure of the direct conversion system receiving system at the time of comprising the reception filter for a band limitation with a digital filter, and putting it behind an AD converter. A sample rate converter according to an embodiment of the present invention is applied to a band limiting reception filter configured by a digital filter, placed behind an AD converter, and further converted to a rate suitable for digital baseband processing. It is a figure which shows the structure of the direct conversion system receiving system at the time of being carried out. It is the schematic diagram showing the frequency characteristic by 8 time linear interpolation. It is a figure explaining the data sequence produced pseudo by the linear interpolation of 8 times. It is a timing chart figure which shows the example of the data output timing from a decimator.

Explanation of symbols

1a, 1b Anti-aliasing filter (AAF)
2a, 2b AD converter (ADC)
3a, 3b Root Nyquist filter 4 Temperature compensated crystal oscillator (TCXO)
5 Phase-locked loop (PLL)
6a, 6b Sample rate converter (SRC)
7a, 7b Linear interpolator 8a, 8b Decimator (selection control circuit)
9 Timing generation circuit 10a, 10b FIFO (first-in first-out) buffer 11 Digital baseband processing unit 12 Receiving antenna 13 Surface acoustic wave (SAW) filter 14 Low noise amplifier (LNA)
15a, 15b Quadrature demodulator 16 Phase shifter 17 Local oscillator (LO)
18a, 18b Analog low pass filter 19a, 19b Digital low pass filter

Claims (3)

A communication system using digital modulation,
An AD converter that samples an input signal at a sample rate of an arbitrary frequency different from an integer multiple of the symbol rate of the input signal ;
A digital signal processing unit that inputs the output of the AD converter and executes processing mainly for the purpose of filtering at the sample rate;
A sample rate converter that receives the output from the digital signal processing unit at the sample rate, and converts it into a data string having a frequency multiplied by a symbol rate of the input signal; and
The sample rate converter is
For the output from the digital signal processing unit, a value obtained by dividing N between two data (N is an integer equal to or greater than 2) is calculated, and a pseudo data string having a rate N times the sample rate is obtained. A linear interpolator to create,
An interval combining a sample interval of a value obtained by rounding down a fractional part of a ratio of a rate N times the sample rate and a rate of the multiplied frequency of the symbol rate and a sample interval obtained by rounding up the fractional value of the ratio. Then, data is thinned out from the data sequence at a rate N times the sample rate so that the average rate becomes the rate of the symbol rate multiplied by the frequency, and the rate of the symbol rate multiplied by the frequency is increased. A decimator for producing the data string;
Receiving system characterized in that it comprises a. The digital signal processing unit disposed in front of the sample rate converter includes an FIR filter having a root Nyquist roll-off characteristic,
The receiving system according to claim 1 , wherein the output of the AD converter is sent to the sample rate converter through the FIR filter . Buffer means for receiving the output of the sample rate converter and outputting data synchronized with a clock having a frequency multiplied by the symbol rate of the input signal used in the digital baseband processing unit in the subsequent stage,
The receiving system according to claim 1 or 2 , wherein the sample rate converter generates data for a rate of a frequency multiplied by a symbol rate of the input signal .

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