JP2845038B2 - Timing control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing controller, and more particularly to a timing controller suitable for controlling a refresh timing of a storage device using a DRAM.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional example. 2 is a memory array 50 in which data is written and read, and a write / read / refresh timing generation circuit that generates various timing signals for writing, reading, and refreshing data in the memory array 50. 11, a backup refresh timing generation circuit 21 for generating a backup refresh timing signal for refreshing data in the memory array 50 and retaining data during battery backup
And a timing selector 60 for selecting either the output of the write / read / refresh timing generation circuit 11 or the output of the backup refresh timing generation circuit 21 based on the battery backup signal 201 and outputting the selected output to the memory array 50. When a normal write or read and refresh operation is performed, a write timing signal or a read timing signal and a refresh timing signal from the write / read / refresh timing generation circuit 11 are supplied to the timing selector 6.
0 to the memory array 50. The memory array 50 performs a write operation, a read operation, and a refresh operation in synchronization with a write timing signal, a read timing signal, and a refresh timing signal from the timing selector 60. When shifting to battery backup, the battery backup signal 201 is input to the timing selector 60, and the backup refresh timing signal from the backup refresh timing generation circuit 21 is input to the memory array 50 via the timing selector 60. The memory array 50 performs a refresh operation in synchronization with a backup refresh timing signal from the timing selector 60.

[0003]

However, in the above-mentioned conventional example, the refresh timing is required at the transition between the normal operation and the battery backup because two refresh timing generation circuits are required for the normal operation and the battery backup. Arbitration control, such as waiting for one of the refresh requests, must be performed so as not to overlap, and the control becomes complicated and the device cannot be downsized.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to improve the disadvantages of the prior art, and in particular, to make a common refresh timing generation circuit for normal operation and battery backup, to reduce the size of the device and simplify control. An object of the present invention is to provide a timing control device capable of achieving the above.

[0005]

Therefore SUMMARY OF THE INVENTION In the present invention, data
Data write / read timing signal by
Signal and refresh timing signal
And a memory module to be refreshed for writing / reading and data of the data, the write / read timing generation circuit for outputting to the memory module generates data write / read timing signal, a memory module to generate a refresh timing signal The refresh timing generator circuit outputs the refresh timing signal to the refresh timing generator circuit .
Memory to generate a timing switching signal for selecting a switching signal
Output to the module and input the battery backup signal from the power supply control unit.
It generates timing switching signal for selecting the timing signals and employs a configuration that <br/> that includes a timing switching circuit for outputting to the memory module. This aims to achieve the above-mentioned object.

[0006]

During a normal write and read operation, the write / read timing generation circuit outputs a write or read timing signal to the memory module. The memory module performs a data write or read operation in synchronization with a write or read timing signal from the write / read timing generation circuit.

During a normal refresh operation, the refresh timing generation circuit outputs a refresh timing signal to the memory module. At the same time, the refresh timing generation circuit outputs a refresh signal to the timing switching circuit. Upon receiving the refresh signal from the refresh timing generation circuit, the timing switching circuit outputs a timing switching signal for selecting the refresh timing signal to the memory module. The memory module performs a data refresh operation in synchronization with a refresh timing signal from the refresh timing generation circuit.

At the time of battery backup, the timing switching circuit outputs a timing switching signal for selecting a refresh timing signal to the memory module upon receiving a battery backup signal from the power supply control device. The refresh timing generation circuit outputs a refresh timing signal to the memory module. The memory module performs a data refresh operation in synchronization with a refresh timing signal from the refresh timing generation circuit.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIG. The embodiment of FIG. 1 shows a memory module 40 for writing / reading data and refreshing data.
And a write / read timing generation circuit 10 for generating a write and read operation timing signal and outputting the same to the memory module 40, and a refresh timing generation circuit for generating a refresh timing signal during normal operation and battery backup and outputting the same to the memory module 40 The memory module 40 generates a timing switching signal 200 for selecting a refresh timing signal from the refresh timing generation circuit 20 based on the circuit 20, a refresh signal 300 from the refresh timing generation circuit 20, and a battery backup signal 100 from a power control device (not shown). Output switching circuit 30
And

Here, the memory module 40 is provided with a DRAM (Dynamic R) for writing / reading data.
and a timing signal 200 from the timing switching circuit 30. A data writing / reading timing signal from the writing / reading timing generation circuit 10 and a refresh timing signal from the refresh timing generation circuit 20 are provided by a memory array 50 composed of an S.A.M. And a timing selector 60 for switching between the two.

Next, the operation of this embodiment will be described.

(1) Normal write and read operations:

The write / read timing generation circuit 10 outputs a write or read timing signal to the timing selector 60.

The timing selector 60 outputs a write or read timing signal from the write / read timing generation circuit 10 to the memory array 50.

The memory array 50 performs a data write or read operation in synchronization with a write or read timing signal from the timing selector 60.

(2) During normal refresh operation:

The refresh timing generation circuit 20
The refresh timing signal is supplied to the timing selector 60.
Output to

At the same time, the refresh timing generation circuit 2
0 indicates that the refresh signal 300 is
Output to 0.

The timing switching circuit 30 is provided with a refresh signal 300 from the refresh timing generation circuit 20.
, A timing switching signal 200 for selecting a refresh timing signal is output to the timing selector 60.

The timing selector 60 outputs a refresh timing signal from the refresh timing generation circuit 20 to the memory array 50.

The memory array 50 performs a data refresh operation in synchronization with a refresh timing signal from the timing selector 60.

(3) At the time of battery backup:

The power control device outputs a battery backup signal 100 to the timing switching circuit 30.

When receiving the battery backup signal 100 from the power supply control device, the timing switching circuit 30 outputs a timing switching signal 200 for selecting a refresh timing signal to the timing selector 60.

The refresh timing generation circuit 20
The refresh timing signal is supplied to the timing selector 60.
Output to

The timing selector 60 outputs a refresh timing signal from the refresh timing generation circuit 20 to the memory array 50.

The memory array 50 performs a data refresh operation in synchronization with a refresh timing signal from the timing selector 60.

At the time of battery backup, since only data retention is required, the output from the timing switching circuit 30 is fixed to a timing switching signal 200 for selecting a refresh timing signal.

At this time, the objects to be backed up by the battery are the memory module 40, the refresh timing generation circuit 20, and the timing switching circuit 30, and the write / read timing generation circuit 10 is not the object of the battery backup.

[0030]

Since the present invention is constructed and functions as described above, it is possible to use a common refresh timing generation circuit during normal operation and during battery backup, thereby reducing the size and control of the apparatus. And an excellent timing control device, which can be simplified, can be provided.

[0031] In addition, during battery backup, data
Data only needs to be held.
These outputs are used to select the refresh timing signal.
Fixed to the switching signal. Therefore, the battery
Write / read data in memory module during backup
No power consumption, so low power consumption during battery backup
Power can be achieved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing one embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional example.

[Explanation of symbols]

 Reference Signs List 10 write / read timing generation circuit 20 refresh timing generation circuit 30 timing switching circuit 40 memory module 50 memory array 60 timing selector

Claims (1)

(57) [Claims] 1. A data writing / reading operation according to a timing switching signal.
Read timing signal and refresh timing signal
Switching Type, and a memory module to be refreshed for writing / reading and data of the data, the write / read timing generation circuit for outputting to the memory module generates the data write / read timing signal, the refresh timing a refresh timing generator for generating and outputting a signal to the memory module, the refresh timing signal and inputs the refresh signal from the refresh timing generator
The timing switch signal to be selected is generated and the memory mode is selected.
Module, and when a battery backup signal from the power supply controller is input, the refresh timing
Timing control system which includes a timing switching circuit for generating said timing switching signal for selecting a ring signal is output to the memory module.