JPH09311816A - Memory interface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the final cost of a memory interface as a whole by making it possible to deal with the change of a memory circuit without changing the design when the memory circuit is changed. SOLUTION: Plural kinds of storing means 10 in which the frequency of inputted reference signal and a data width are different from each other are constituted to be connectable. Then when the frequency of the reference signal of a connected storage means 10 is high, the data width is narrowed but when the frequency of the reference signal of a connected storage means 10 is low, the data width is widened to correspond to the many kinds of storage means 10 without changing a data rate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory interface, and in particular, it is suitable for use in a memory interface used for storing various data in a memory and reading the various stored data.

[0002]

2. Description of the Related Art In recent years, E
DO-DRAM (Extended Data Output-DRAM) and SD
High-speed memory units such as RAM have been developed. The EDO-DRAM has the following 1. Extended data output time. 2. Cycle time reduction. D is suitable for higher speed access.
RAM. The structure of the EDO-DRAM is almost the same as that of the conventional DRAM.

On the other hand, SDRAM (Synchronous-DRA)
M) is JEDEC (Joint Electron Device Engineerin)
g Council) is a memory unit whose specifications are standardized. The characteristics of the SDRAM are: Input / output circuit configuration synchronized with an external clock. 2. Input / output of pipeline structure. 3.2 Bank type cell array system. 4. Commandization of access. And the like. Due to these features, it is possible to speed up data transfer at the time of memory input / output.

As shown in FIG. 2, the SDRAM is composed of two systems of memory arrays M1 and M2, a clock buffer 81, a mode controller 82, an address controller 83, a data register 84 and a buffer memory 85.

The clock buffer 81 supplies reference clocks C to the memory arrays M1 and M2.
L1, CL2, CL3 and CL4 are selectively output. The mode controller 82, based on a control signal from a memory controller described later, each of the memory arrays M1,
Alternately set M2 read / write.

The address controller 83 specifies an address in the memory array based on address data supplied from an address conversion circuit (not shown). The data register 84 performs serial-parallel conversion.
The buffer memory 85 is for temporarily storing input / output data.

Memory arrays M1 and M in the memory
Reference numeral 2 is composed of memory cells (DRAM) 86A, 86B and sense amplifiers 87A, 87B provided independently of these memory cells 86A, 86B, and a predetermined amount of data held in these sense amplifiers 87A, 87B. By performing burst transfer in synchronization with the clock, the transfer speed between the memory and the outside of the memory and the operation speed of the bank inside the memory can be set independently, and high-speed read / write is possible as a whole. To do.

Conventionally, a schematic structure of a memory interface for controlling a DRAM has been as shown in FIG. In FIG. 3, 201 is an address decoder which decodes an input address signal and outputs the decoded result to an access controller 204 described later.

Reference numeral 202 denotes a DR from a reference signal such as a clock.
A refresh timer for outputting an AM refresh timing signal, 203 is the refresh timer 202
The refresh controller controls the access controller 204 based on the timing signal output from the refresh controller.

Reference numeral 204 is an access controller for outputting a control signal to the DRAM 207, and 205 is a DRA for switching between a row address and a column address in response to a selection signal from the access controller 204.
It is an address multiplexer for outputting to M207. 206 is a data bus for exchanging data between the DRAM 207 and an external device, and 207 is a DRAM.

Next, the operation of the memory interface will be described with reference to the state transition diagram shown in FIG. First, when there is no access request or refresh request from an external device (not shown), the memory interface is in the idle state indicated by SI.

When an access request is issued to the DRAM 207 from an external device, the access state SA shown in FIG. 4 is entered and the memory interface starts accessing the DRAM 207. When the access state SA is reached, the access controller 204 outputs a signal for setting a row address and a column address D.
The address multiplexer 205 outputs the data to the RAM 207, and in the order of the row address and the column address.
Causes the DRAM 207 to output an address signal.

The refresh timer 202 is the DRAM 2
A refresh request of 07 is periodically generated. When a refresh request is generated, the refresh state SR shown in FIG. 4 is entered. Then, in the refresh state SR, the memory interface causes the DRAM 207 to refresh.

In the idle state SI shown in FIG. 4, the access controller 204 presets the priorities of memory access and refresh, and transitions from the idle state SI to the access state SA or from the idle state SI. Arbitration of the transition to the refresh state SR is also performed.

[0015]

However, in the conventional memory interface as described above, the target memory circuit is only one type and is not compatible with other memory circuits.

Therefore, if the cost of the entire device is reduced by making the memory circuit inexpensive, there is a problem that the design of the memory interface is forced to be changed and the final cost is increased.

In view of the above problems, the present invention provides a memory interface capable of coping with a change in the memory circuit without changing the design and ultimately reducing the cost of the entire device. The purpose is to

[0018]

The memory interface of the present invention is a memory interface to which a plurality of types of storage means having different frequencies and data widths of an input reference signal can be connected, and the reference signal of the storage means is provided. When the frequency is high, the data width is narrowed, and when the frequency of the reference signal of the storage means is low, the data width is widened.

Another feature of the present invention is that
It is characterized by comprising a storage means identification means for identifying the type of the connected storage means.

Another feature of the present invention is that it comprises a reference signal selecting means for selecting and outputting one of the plurality of input reference signals. Is characterized in that one of the plurality of input reference signals is selected based on the identification result of the storage means identification means and is output to the storage means.

Further, other features of the present invention
Indicates that the data width is the first bit n and the frequency of the reference signal is
1 frequency f₁And the data width is
The frequency of the reference signal is the second frequency f with the bit m of 2_Twoso
A memory interface that can be connected to a second storage means
The first bit n and the first frequency f ₁
And the second bit m and the second frequency f
_TwoIt is characterized in that the result of multiplication with and is equal.

Another feature of the present invention is that storage means for identifying which of a plurality of types of storage means having different frequencies and data widths of the input reference signal is connected. It is characterized in that it is provided with an identification means.

Another feature of the present invention is that it comprises a reference signal selecting means for selecting and outputting one of the plurality of input reference signals, and the reference signal selecting means. Is characterized in that the reference signal is selected based on the identification result of the storage means identification means and is output to the storage means.

Another feature of the present invention is a memory interface to which a plurality of types of storage means having different frequencies and data widths of an input reference signal can be connected, wherein the data width is the first. Data width conversion for mutually converting the data having the data rate of the first data rate fHz at the bit n and the data having the data width of the third bit 2n and the second data rate f / 2 Hz Means, a storage means identifying means for identifying the type of storage means connected among the plurality of types of storage means, and controlling the connected storage means based on the identification result of the storage means identifying means. And a control means.

Another feature of the present invention is that it comprises a reference signal selecting means for selecting and outputting one of the plurality of input reference signals. Is characterized in that one of the plurality of input reference signals is selected based on the identification result of the storage means identification means and is output to the storage means.

Another feature of the present invention is that the data width is the first bit n and the frequency of the reference signal is the first data rate fHz, and the first storage means is the third data width. A bit 2n of the memory interface that can be connected to a second storage means in which the frequency of the reference signal is the second data rate f / 2 Hz, and the data width is the first bit n The data having the first data rate fHz and the data width of the third bit 2n
And a data width conversion means for mutually converting data whose reference signal frequency is the second data rate f / 2 Hz, a storage means identification means for identifying the type of the connected storage means, and the storage means. And a control means for controlling the connected storage means based on the identification result of the identification means.

Another feature of the present invention is that it comprises a reference signal selecting means for selecting and outputting one of the plurality of input reference signals, and the reference signal selecting means. Is characterized in that one of the plurality of input reference signals is selected based on the identification result of the storage means identification means and is output to the storage means.

Another feature of the present invention is a memory interface to which a plurality of types of storage means having different frequencies and data widths of input reference signals can be connected, and the data width is the first. First data width conversion means for converting data having a data rate of the first data rate fHz in the bit n to data having a second data rate of f / 2 Hz in the third bit 2n And data having a data width of the first bit n and a data rate of the first data rate fHz are converted into data having a data width of the third bit n / 2 and a data rate of the third data rate 2fHz. The second data width conversion means, the storage means identification means for identifying the type of the connected storage means, and the above-mentioned description based on the identification result of the storage means identification means. It is characterized in that a control means for controlling the means.

Another feature of the present invention is that it comprises a reference signal selecting means for selecting and outputting one of the input plurality of reference signals, and the reference signal selecting means. Outputs a reference signal to the storage means based on the identification result of the storage means identification means.

Another feature of the present invention is that the first storage means has a data width of a first bit n and a data rate of a first data rate fHz, and the data width is a third bit. A memory interface capable of connecting to a second storage means for data having a data rate of 2n and a second data rate of f / 2 Hz and having a first data width.
The data rate is the first data rate fHz at bit n of
Data having a data width of the third bit 2n and a data rate of the second data rate f / 2 Hz, and a data having a data width of the first bit n. Second data width conversion means for converting data having a first data rate fHz to data having a third data width of 3 bits n / 2 and a third data rate of 2 fHz, and the connection. Storage means identifying means for identifying the type of storage means being stored,
And a control unit that controls the storage unit based on the identification result of the storage unit identification unit.

Another feature of the present invention is that it comprises a reference signal selecting means for selecting and outputting one of the plurality of input reference signals, and the reference signal selecting means. Is characterized in that one of the plurality of input reference signals is selected based on the identification result of the storage means identification means and is output to the storage means.

[0032]

Since the present invention comprises the above technical means, it is possible to satisfactorily cope with the change of the type of the target memory circuit without changing the design.
It is possible to deal with various memory circuits without increasing the cost.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a memory interface of the present invention will be described with reference to FIG. In FIG. 1, reference numeral 1 is an address decoder, which decodes an input address signal and outputs it to an access controller 4 described later.

A refresh timer 2 outputs a timing signal for refreshing the memory from a reference signal such as a clock. A refresh controller 3 controls the operation of the command controller 6 based on the timing signal output from the refresh timer 2.

An access controller 4 is for outputting a control signal to a command controller described later. An address multiplexer 5 is for switching between a row address and a column address in response to a selection signal from the access controller 4 and outputting it to the storage means 10.

A command controller 6 is provided as a storage means identifying means for identifying the type of memory such as DRAM, EDO-DRAM or SDRAM provided as the storage means 10 in response to a control signal from an external device. That is, these memories are operated according to the identification result.

Reference numeral 7 is a mode controller 6, which outputs a mode signal to a command controller or a clock buffer 8 which will be described later in response to an input from an external device. Reference numeral 8 denotes a clock buffer, which is a plurality of clocks C having different frequencies
One of L1, CL2, CL3 and CL4 is selected and output to the storage means 10.

A data bus 9 is used for exchanging data between the memory and an external device. 10 is a memory, such as DRAM, SDRAM or EDO-D
Either of the RAMs is used.

Next, with reference to FIG. 5, the operation of the memory interface in which the SDRAM and the EDO-DRAM can be shared will be described. When the access request signal P1 from the external device is input to the access controller 4 through the address decoder 1, the idle state SI transits to the access standby state S1.

In the access standby state S1, the memory currently connected to the mode controller 7 is SDR.
A memory identification signal P2 for identifying whether it is AM or EDO-DRAM is input from an external device.

The mode controller 7 outputs the input memory identification signal P2 to the command controller 6 and the clock buffer 8. Command controller 6
Thus, when the memory is identified, the access standby state S1 transits to the first memory connection state S2 or the first memory connection state S2 '.

For example, the first memory connection state S2 is SD
It is predetermined that the transition is made when the RAM is connected and the second memory connection state S2 ′ is made when the EDO-DRAM is connected. When transitioning to the first memory connection state S2, the command controller 6
Output an access command to AM. The access command is, for example, as shown in Table 1 below.

[0043]

[Table 1]

First, the command controller 6 inputs a bank active command. At the same time, the access controller 4 inputs the row address P3 from the address multiplexer 5 to the connected SDRAM.

After that, the command controller 6 inputs a read / write command. At the same time as the input of the read / write command, the access controller 4 inputs the column address and inputs it from the address multiplexer 5 to the connected SDRAM.

On the other hand, the connected memory is EDO-D.
In the case of RAM, the access standby state S1 is transited to the second memory connection state S2 '. Second
When the memory connection state S2 'is changed, the command controller 6 outputs a signal for setting the row address to the storage means 10. At the same time, the access controller 4 causes the address multiplexer 5 to input the row address to the storage unit 10.

After that, the command controller 6 outputs a signal for setting the column address to the storage means 10. At the same time, the access controller 4 inputs the column address from the address multiplexer 5 to the storage means 10.

The transitions from the access standby state S1 to the first and second memory connection states S2 and S2 'may be performed in the opposite combination. For example, the first memory connection state S2 is ED.
When the O-DRAM is connected, the second memory connection state S2 ′ may be predetermined so as to transit when the SDRAM is connected.

The refresh timer 2 periodically generates a refresh request for the storage means 10. When a refresh request occurs, the idle state SI transits to the refresh standby state S3.

In the refresh standby state S3, the mode controller 7 is connected to the storage means 1 currently connected.
A memory identification signal P2 that identifies whether 0 is SDRAM or EDO-DRAM is input from an external device. The mode controller 7 outputs the input memory identification signal P2 to the command controller 6 and the clock buffer 8.

When the memory connected to the storage means 10 is identified, the refresh standby state S3 to the first memory connection state S4 or the second memory connection state S is displayed.
Transition to 4 '. It is predetermined that the first memory connection state S4 transits, for example, when the SDRAM is connected, and the second memory connection state S4 ′ transits when the EDO-DRAM is connected.

When transiting to the first memory connection state S4,
The command controller 6 inputs a refresh command to the SDRAM. In the case of SDRAM, when the command controller 6 inputs a refresh command, SDR
A refresh counter (not shown) inside the AM generates a refresh address so that the SDRAM is refreshed.

The connected memory is an EDO-D.
In the case of RAM, the refresh standby state S3 to the second
The memory connection state S4 'of FIG.
When transitioning to the second memory connection state S4 ', the command controller 6 outputs a signal for refreshing to the storage means 10 to refresh the EDO-DRAM connected as the storage means 10. ing.

Next, referring to FIGS. 6A and 6B,
SDRAM and EDO connected as storage means 10
The connection between the DRAM and the memory interface of this embodiment will be described. In FIG. 6, 101 is a memory interface according to the present embodiment, and 102 is an S.
DRAM, 103 is an EDO-DRAM, and 104 is a data bus.

A plurality of clocks having different frequencies, a memory identification signal, an access signal, etc. are input to the memory interface 101. An address signal and a command signal, for example, a 70 MHz clock signal are input from the memory interface 101 to the SDRAM 102.

Further, the memory interface 101
If the EDO-DRAM 103 is connected to
An address signal, a command signal, and a 35 MHz clock signal, for example, are input from the memory interface 101.

When the SDRAM 102 is connected to the memory interface 101, the SDRAM 102
Is connected to an external device by a data line for bits of the 8-bit data bus 104, for example.

On the other hand, when the EDO-DRAM 103 is connected to the memory interface 101, the ED
The O-DRAM 103 and the external device are connected by all the data lines of the 16-bit data bus 104, for example.

That is, when the EDO-DRAM 103 is connected to the memory interface 101,
The data input / output speed is halved as compared with the case where the SDRAM 102 is connected to the memory interface 101.

If the EDO-DRAM 103 is connected to the memory interface 101, SD
The data input / output amount for one clock is doubled as compared with the case where the RAM 102 is connected to the memory interface 101.

Furthermore, when the EDO-DRAM 103 is connected to the memory interface 101, 8-bit data is transferred to 2 by an unillustrated shift register.
Input / output is performed as individual 16-bit data.

By connecting as described above, the total data rate is SDRAM 102, EDO-
Which of the DRAM 103 is the memory interface 10
The same applies when connected to 1.

Next, another embodiment of the present invention will be described with reference to FIG. The same reference numbers as in FIG. 1 indicate the same functions. In FIG. 7, 1 is an address decoder,
The input address signal is decoded and output to the access controller 4 described later.

A refresh timer 2 outputs a timing signal for refreshing the memory from a reference signal such as a clock. A refresh controller 3 controls the command controller 6 based on the timing signal output from the refresh timer 3.

An access controller 4 is for outputting a control signal to a command controller 6 described later.

An address multiplexer 5 is for switching between a row address and a column address in response to a selection signal from the access controller 4 and outputting it to the storage means 10. A command controller 6 is a DRAM or EDO-DRA connected as the storage means 10 by a control signal from an external device.
These memories are operated according to the type such as M and SDRAM.

Reference numeral 7 denotes a mode controller, which sends a mode signal input from an external device to the command controller 6
Or to the clock buffer 8 described later. A clock buffer 8 receives a plurality of clocks having different frequencies, selects one of the plurality of clocks, and outputs it to the memory.

A data bus 9 is used for exchanging data between the memory and an external device. 10
Is a memory constituting a storage means, such as DRAM, SDR
Either AM or EDO-DRAM is used.

A data width conversion circuit 20 converts the data width and the data input / output rate between the data bus 9 and the memory 10 such as DRAM, EDO-DRAM or SDRAM. The data width conversion circuit 20 has an SDR
The AM and the data conversion circuit 20 are connected with a data width of 8 bits (first bit width), a data rate of 70 MHz and a first data rate, for example.

When the identification signal from the mode controller 7 identifies that the SDRAM is connected, the data width conversion circuit 20 outputs the data width and data rate without conversion. It should be noted that the EDO-DRAM and the data width conversion circuit 20 have, for example, a data width of 16 bits (second bit width) and a data rate of 35 MHz (second bit width).
Data rate).

On the other hand, when the identification signal from the mode controller 7 identifies that the EDO-DRAM is connected as the memory 10, the data width conversion circuit 20
Is an EDO-DRAM that converts two pieces of 8-bit data sent via the data bus 9 into one piece of 16-bit data.
Output to At this time, the data rate from the data bus 9 is 70 MHz, while the data rate to the EDO-DRAM is 35 MHz.

Further, the data width conversion circuit 20 uses the EDO-D
One 16-bit data from the RAM is output to the data bus 9 as two 8-bit data. At that time, EDO
The data rate from the DRAM is 35 MHz, whereas the data rate to the data bus 9 is 70 MHz.

Next, the connection between the SDRAM and EDO-DRAM and the memory interface of this embodiment will be described with reference to FIGS. 8A and 8B. In FIG. 8, 301 is a memory interface according to the present embodiment, 302 is SDRAM, and 303 is E.
DO-DRAM, 304 is a data bus.

The memory interface 301 has a plurality of clocks clk having different frequencies, a memory identification signal,
An access signal or the like is input. Further, an address signal from the memory interface 301 to the SDRAM 302,
A command signal, for example, a 70 MHz clock signal or the like is input.

ED in the memory interface 301
When the O-DRAM 303 is connected, an address signal, a command signal, and a clock signal of 35 MHz, for example, are input from the memory interface 301.

If the SDRAM 302 is connected to the memory interface 301, the SDRAM 3
02 and the memory interface 301 are connected with a data width of 8 bits, and when the EDO-DRAM 303 is connected to the memory interface 301, they are connected with a data width of 16 bits.

[0077]

As described above, according to the memory interface of the present invention, when the frequency of the input reference signal is high, the data width is narrowed, and when the frequency of the input reference signal is low, the data width is narrowed. Since the data width is widened, it is possible to connect a plurality of types of storage means having different reference signal frequencies and data widths. As a result, even if the type of the memory circuit to be connected is changed, it is possible to favorably cope with it without changing the data rate, so that it is possible to cope with various memory circuits without changing the design of the memory interface. As a result, the final cost of the entire device can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of a memory interface according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an SDRAM used in the first embodiment.

FIG. 3 is a block diagram showing an example of a conventional memory interface.

FIG. 4 is a state transition diagram showing an operation of a conventional memory interface.

FIG. 5 is a state transition diagram showing an operation of the memory interface according to the present embodiment.

FIG. 6 is a block diagram showing a connection between a memory interface and a memory according to the first embodiment.

FIG. 7 is a block diagram showing a configuration of a memory interface according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a connection between a memory interface and a memory according to a second embodiment of this invention.

[Explanation of symbols]

 1 Address Decoder 2 Refresh Timer 3 Refresh Controller 4 Access Controller 5 Address Multiplexer 6 Command Controller 7 Mode Controller 8 Clock Buffer 9 Data Bus 10 Storage Means

Claims (14)

[Claims] 1. A memory interface capable of connecting a plurality of types of storage means having different input reference signal frequencies and data widths, wherein the data width is narrowed when the reference signal frequency of the storage means is high. At the same time, the data interface is widened when the frequency of the reference signal of the storage means is low. 2. The memory interface according to claim 1, further comprising a storage unit identification unit for identifying the type of the connected storage unit. 3. A reference signal selecting means for selecting and outputting one of the plurality of input reference signals, wherein the reference signal selecting means determines a result of the storage means identifying means. 3. The memory interface according to claim 2, wherein one of the plurality of input reference signals is selected based on the selected reference signal and is output to the storage means. 4. A first storage means having a data width of a first bit n and a reference signal frequency of a first frequency f ₁ ; and a data width of a second bit m and a reference signal frequency of a second. A memory interface capable of connecting to a second storage means having a frequency f ₂ of, the multiplication result of the first bit n and the first frequency f _1, and the second bit m and the second frequency f ₁ . The memory interface is characterized in that the result of multiplication with the frequency f ₂ is equal. 5. A storage means identifying means for identifying which of a plurality of types of storage means having different frequencies and data widths of an input reference signal is connected is provided. Item 4. The memory interface according to item 4. 6. A reference signal selection means for selecting and outputting one of the plurality of input reference signals, wherein the reference signal selection means is a result of the storage means identification means. The memory interface according to claim 4, wherein the reference signal is selected based on the selected signal and output to the storage means. 7. A memory interface to which a plurality of types of storage means having different frequencies and data widths of an input reference signal can be connected, wherein the data width is the first bit n and the data rate is the first data. The data having the rate fHz, the data width having the third bit 2n, and the data rate having the second data rate f / 2
Data width conversion means for mutually converting data of Hz, storage means identification means for identifying the type of storage means connected among the plurality of types of storage means, and an identification result of the storage means identification means And a control means for controlling the connected storage means based on the above. 8. A reference signal selecting means for selecting and outputting one of the plurality of input reference signals, wherein the reference signal selecting means determines whether or not the identification result of the storage means identifying means is present. 8. The memory interface according to claim 7, wherein one of the plurality of input reference signals is selected based on the selected reference signal and is output to the storage means. 9. A first storage means having a data width of a first bit n and a reference signal frequency of a first data rate fHz; and a data width of a third bit 2n and a reference signal frequency of a second. A memory interface capable of connecting to a second storage means having a data rate of f / 2 Hz, wherein the data width is the first bit n and the frequency of the reference signal is the first data rate fHz; Data width conversion means for mutually converting data having a data width of the third bit 2n and a frequency of the reference signal being the second data rate f / 2 Hz, and a memory for identifying the type of the connected storage means. A memory interface comprising: means identifying means; and control means for controlling the connected storage means based on the identification result of the storage means identifying means. 10. A reference signal selection means for selecting and outputting one of the plurality of input reference signals, wherein the reference signal selection means is a result of the storage means identification means. 10. The memory interface according to claim 9, wherein one of the plurality of input reference signals is selected on the basis of the selected reference signal and is output to the storage means. 11. A memory interface capable of connecting a plurality of types of storage means having different frequencies and data widths of an input reference signal, wherein the data width is the first bit n and the data rate is the first data rate. The data whose frequency is fHz is the second data rate f / 2 Hz with the data width of the third bit 2n.
And a data having a data width of a first bit n and a data rate of a first data rate fHz, and a data having a third data width of n / 2. The third data rate is 2 fHz
Second data width conversion means for converting into data, storage means identifying means for identifying the type of the connected storage means, and controlling the storage means based on the identification result of the storage means identifying means. A memory interface comprising: a control unit. 12. A reference signal selecting means for selecting and outputting one of the plurality of input reference signals, wherein the reference signal selecting means determines a result of the storage means identifying means. 12. The memory interface according to claim 11, wherein the reference signal is output to the storage means based on the above. 13. A first storage means having a data width of a first bit n and a data rate of a first data rate fHz; and a data width of a third bit 2n and a second data rate.
A data interface having a data rate of f / 2 Hz and a second storage means for connecting the data having a data width of the first bit n and a data rate of the first data rate fHz. The width is the third bit 2n and the data rate is the second data rate f / 2 Hz
And a data having a data width of a first bit n and a data rate of a first data rate fHz, and a data having a third data width of n / 2. The third data rate is 2 fHz
Second data width conversion means for converting into data, storage means identification means for identifying the type of the connected storage means, and the storage means based on the identification result of the storage means identification means. A memory interface comprising: control means for controlling. 14. A reference signal selection means for selecting and outputting one of the plurality of input reference signals, wherein the reference signal selection means is a result of the identification by the storage means identification means. 14. The memory interface according to claim 13, wherein one of the plurality of input reference signals is selected based on the selected reference signal and is output to the storage unit.