JP2002109879A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time of continuous access to multiple memory cells connected to different bit lines. SOLUTION: This semiconductor memory has a DRAM core part 10 which has bit lines and also have multiple memory cells connected to each bit line and where data are written to or read out of memory cells selected according to addresses inputted by cycles, an address comparator 23 which compares addresses inputted in two successive cycles with each other and generates a flag showing whether or not memory cells selected according to both the addresses are connected to the same bit line, an address controller 21 which inputs and holds external addresses according to the flag, and a command controller 22 which inputs command according to the flags and outputs various control signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an improved data access method in a DRAM or a virtual SRAM.

[0002]

2. Description of the Related Art Generally, a DRAM is compared with an SRAM.
Cycle time at random access (random access
Since the cycle time is long, the data transfer efficiency is low under the condition of random access. That is, in the DRAM, the number of address bits is larger than that in the SRAM.
The address is divided into a row address and a column address, and these are input in a time-division manner. For this reason,
A DRAM has two cycle times, a row cycle time and a column cycle time. Due to its characteristics, the DRAM requires a long row cycle time.
Further, in the DRAM, a capacitor is used for a memory cell, and the capacitor dynamically holds data. For this reason, the DRAM requires a refresh operation. In the write operation, a charge time for writing to the capacitor is required, in a read operation, a charge / discharge time, and a precharge time for precharging the bit line to a predetermined potential after the end of the write / read operation are required. Since it is necessary to set a cycle time that can be sufficiently secured, the cycle time becomes longer.

In other words, if a random access operation such as an SRAM is performed by a DRAM, the cycle time becomes S
It is not as short as RAM.

FIG. 6A is a conceptual diagram showing an operation example of a DRAM when a plurality of memory cells sharing a bit line are continuously accessed. After the address A is supplied to select a corresponding memory cell and a write (write) or read (read) operation is performed, a bit line to which the memory cell is connected is precharged to a predetermined potential. A period required for a series of operations including the write / read operation and the precharge operation is a cycle time. Thereafter, the memory cells corresponding to the addresses B and C are sequentially selected, and a write or read operation is performed.
The bit line is precharged to a predetermined potential.

As described above, when a plurality of memory cells sharing a bit line are successively accessed, if a complete random access is to be realized, the word line potential rises in the row cycle and the memory cell is selected. Then, the data writing or reading operation is performed, then the word line potential decreases, and the precharging operation of the bit line must be started until the precharging operation ends. At the time of address switching between memory cells connected to the same bit line, if the next word line is activated before the bit line precharge operation is completed,
Erroneous writing occurs in another memory cell.

In a random access operation other than a random access operation in a plurality of memory cells sharing a bit line, that is, in a random access operation in a plurality of memory cells not sharing a bit line, even if the above-mentioned charge / discharge time and precharge time are not satisfied, Since the next cycle can be started, the cycle time can be shortened.

For example, as shown in the conceptual diagram of FIG. 6B, as long as access to a plurality of memory cells having bit lines separated from each other continues, even if the precharging operation of the bit lines is not completed, The word line at the next address can be activated.

However, in the conventional DRAM, FIG.
As shown in (a), the timing for activating a word line is set in consideration of a case where a plurality of memory cells sharing a bit line are continuously accessed.
There is a problem that the timing control as shown in FIG. 6B cannot be performed, and it is therefore difficult to speed up the read / write operation.

Although the basic configuration is a DRAM,
The same problem as described above also occurs in the case of a so-called virtual SRAM in which the refresh operation does not need to be considered from the outside.

[0010]

As described above, the conventional DR
In a semiconductor memory device such as an AM or a virtual SRAM, the timing for activating a word line is set by being restricted by a random access operation in a plurality of memory cells sharing a bit line, so that a high speed read / write operation is performed. Is difficult.

SUMMARY OF THE INVENTION The present invention has been made in consideration of the above circumstances, and has as its object to improve the operation speed of a random access operation in a plurality of memory cells that do not share a bit line. To provide a storage device.

[0012]

A semiconductor memory device according to the present invention has a bit line, a plurality of memory cells are connected to one bit line, and each memory cell is selected in accordance with an address inputted in each cycle. The memory circuit in which data is written to or read from the selected memory cell is compared with the addresses input in the previous cycle and the current cycle, and the memory cells selected according to both addresses are the same. A flag generation circuit for generating a flag indicating whether or not the memory cell is connected to the bit line.

Further, the semiconductor memory device of the present invention has a bit line, a plurality of memory cells are connected to one bit line, and a memory cell is selected in accordance with an address inputted in each cycle. A memory circuit for writing data to a memory cell or reading data from a selected memory cell, an address control circuit for holding an input address and supplying the address to the memory circuit, and controlling an operation of the memory circuit A command control circuit that outputs a control signal to the memory circuit for controlling at least data read and write operations of the memory circuit based on the command,
A flag that compares the address of the previous cycle and the address of the current cycle held in the address control circuit and generates a flag indicating whether both addresses are addresses corresponding to the memory cells connected to the same bit line. A generation circuit; and a logic circuit to which the flag and the synchronization signal are supplied and which outputs the synchronization signal to the address control circuit and the command control circuit as a synchronization signal for capturing an address and a command based on the flag. ing.

Further, the semiconductor memory device of the present invention has a bit line, a plurality of memory cells are connected to one bit line, and a memory cell is selected in accordance with an address inputted in each cycle. Holding a memory circuit in which data is written to a memory cell or data is read from a selected memory cell, and an input address;
An address control circuit to be supplied to the memory circuit and various commands for controlling the operation of the memory circuit are input, and a control signal for controlling at least data read and write operations of the memory circuit based on the command is transmitted to the memory control circuit. A command control circuit for outputting to the memory circuit;
A flag that compares the address of the previous cycle and the address of the current cycle held in the address control circuit and generates a flag indicating whether both addresses are addresses corresponding to the memory cells connected to the same bit line. A generation circuit, a delay circuit for delaying the flag generated by the flag generation circuit for one cycle and outputting the same, an output of the delay circuit and a synchronization signal being supplied, and the synchronization signal based on an output of the delay circuit. To the address control circuit and the command control circuit as a synchronizing signal for taking in an address and a command.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a DRAM according to the first embodiment of the present invention. In the figure, reference numeral 10 denotes an asynchronous DRAM core unit (memory circuit) 10 provided with a memory cell array, a row decoder, a column decoder, a sense amplifier and the like, and not including a timing signal generation circuit.

Reference numeral 20 denotes a synchronous interface (Synchronous DRAM interface) for supplying addresses and various control signals to the DRAM core unit 10 and transmitting and receiving input / output data between the DRAM core unit 10 and the outside of the DRAM.
ce) circuit.

In the DRAM core unit 10, in a read cycle, a memory cell in a memory cell array is selected in accordance with an input address, data is read from the selected memory cell, sensed and amplified by a sense amplifier, and Output as read data. In the write cycle, a memory cell in the memory cell array is selected in accordance with the input address, and data is written to the selected memory cell in accordance with externally input write data.

In the DRAM core unit 10, during the read cycle and the write cycle, as described with reference to FIG. 6B, before the precharge operation of the bit line is completed in the previous cycle, the next cycle. The operation is controlled so that the data read / write operation at the time is started.

In the synchronous interface circuit 20,
The address input from outside is the address controller 2
1 and the held address is the DRA
It is supplied to the M core unit 10 as an internal address. Commands input from the outside, for example, a write enable signal / WE and a refresh control signal / REF are held by the command controller 22, where a read signal / WE
DRAM decoded into RD, write signal / WT, etc.
It is supplied to the core unit 10.

The address of the previous cycle held by the address controller 21 is supplied to the address comparator 23 together with the current address. Address comparator 23
Compares the two addresses and generates a busy flag / Busy indicating whether or not the memory cells of the memory cell array in the DRAM core unit 10 selected according to the two addresses are the memory cells connected to the same bit line. I do. The busy flag / Busy is, for example, a signal which becomes "L" level when memory cells selected according to both addresses are connected to the same bit line, and becomes "H" level otherwise. is there. This busy flag / Bu
sy is supplied to a logic circuit including, for example, a CPU for supplying an address and a command to the DRAM.

Further, the busy flag / Busy is
It is supplied to an AND circuit 24 provided in the synchronous interface circuit 20. The clock signal CLK is supplied to the AND circuit 24. And this AND circuit 24
Is supplied to the address controller 21 and the command controller 22 described above. The address controller 21 and the command controller 22 include an AND circuit 24
When the synchronization signal output from the external device is input, an address and a command input from the outside are captured in synchronization with the input and held.

Further, a synchronizing signal which is established earlier than the clock signal CLK is input to the address comparator 23, and the address comparator 23 performs an address comparing operation in synchronization with the synchronizing signal.

FIG. 2 is a block diagram extracting and showing the configuration of the memory cell array portion in the DRAM core unit 10 in FIG. A plurality of memory cells MC are stored in a plurality of banks Bank.
0, Bank1,... In each bank, a plurality of word lines WL and bit lines BL are arranged so as to intersect with each other, and memory cells MC are arranged at intersections of each word line WL and bit line BL.

As shown in the circuit diagram of FIG. 3, each memory cell MC has one end of a source / drain current path connected to a corresponding bit line BL and a gate connected to a corresponding word line WL. It comprises a transistor Q and a capacitor C connected between the other end of the current path of the transistor Q and a node to which a predetermined potential is supplied.

Next, the operation of the DRAM having the above configuration will be described.
This will be described with reference to the timing chart of FIG.

FIG. 4 shows a case where a read cycle or a write cycle occurs several consecutive times, respectively.
The signal waveform in the main part in the middle is shown. Note that, in FIG. 4, the shaded portions on the lower left indicate that the respective logic levels are fixed at the “H” level or the “L” level. Further, tcy indicates one cycle period.

Here, it is assumed that the busy flag / Busy is at "H" level in advance. When the clock signal CLK rises to the “H” level in the first cycle, the output of the AND circuit 24 also rises to the “H” level in synchronization with the rise, the address A is held by the address controller 21 and the command controller 22 Command is retained. At this time, since the command is such that the refresh control signal / REF is at the "H" level and the write enable signal / WE is at the "H" level, this cycle is a read cycle.

Thereafter, the internal address A corresponding to the address A held by the address controller 21 is changed to the DRA.
While being supplied to the M core unit 10, decoding is performed based on the command held by the command controller 22, and an “L” level read signal / RD is supplied to the DRAM core unit 10. At this time, the write signal / WT is at "H" level. Thereafter, a memory cell corresponding to the internal address A is selected from the DRAM core unit 10, data is read from the selected memory cell, and output as read data QA via the synchronous interface circuit 20.

In the next cycle, the external address B is supplied. It is assumed that the address B corresponds to a memory cell connected to a bit line different from the bit line connected to the memory cell selected by the address A input in the previous cycle. The address B is input to the address comparator 23 together with the address A input in the previous cycle. In this case, since the addresses A and B correspond to the memory cells connected to different bit lines, the busy flag / Busy remains at "H" level and does not change. Thereafter, when the clock signal CLK rises, the output of the AND circuit 24 also rises to the “H” level, and the address controller 21 holds the address B and the command controller 22 holds the command. Also in this case, the command is such that the refresh control signal / REF is at the “H” level and the write enable signal /
Since WE is at "H" level, this cycle is also a read cycle.

Thereafter, the internal address B corresponding to the address B held in the address controller 21 is set to DRA.
While being supplied to the M core unit 10, decoding is performed based on the command held by the command controller 22, and an “L” level read signal / RD is supplied to the DRAM core unit 10. Further, thereafter, the DRAM core unit 1
From 0, a memory cell corresponding to the internal address B is selected, data is read from the selected memory cell, and the read data QB is read via the synchronous interface circuit 20.
Is output as

Here, as described above, in the DRAM core unit 10, at the time of a read cycle for reading data, before the end of the precharge operation of the bit line in the previous cycle, the operation in the next cycle is performed. Since the operation is controlled so that the data read / write operation is started, data can be read at a higher speed than in the related art.

In the next cycle, the external address C is supplied. It is assumed that the address C corresponds to a memory cell connected to the same bit line as the bit line to which the memory cell selected by the address B input in the previous cycle is connected. In this case, addresses B, C
Corresponds to the memory cell connected to the same bit line, so the busy flag / Busy output from the address comparator 13 for comparing both addresses falls to the "L" level. When the busy flag / Busy goes to "L" level, the output of the AND circuit 24 remains at "L" level even if the clock signal CLK rises to "H" level, and the address controller 21 and the command controller 22 send the address and command. Without taking in
Not retained (addresses and commands are not accepted).

In this case, the DRAM core unit 10 supplies control signals (/ RD,
/ WT, etc.) is not supplied, so that the operation of reading data from the memory cell corresponding to the internal address B input in the previous cycle is continued. That is, after the read operation on the memory cell corresponding to the internal address B, the operation is continued until the precharge operation of the bit line connected to the memory cell ends.

As described above, when addresses corresponding to memory cells having different bit lines are successively input, addresses and commands are fetched in continuous cycles,
Read data is output at the fastest speed.

On the other hand, when the addresses of the memory cells connected to the same bit line are successively inputted, a busy flag / Busy is generated after the next address is inputted, whereby the address and the command are not accepted. The state is communicated to the outside. Busy flag /
The external address (address C) and the command supplied in the cycle immediately after the Busy is generated are not held by the address controller 21 and the command controller 22.

Therefore, in a logic circuit outside the DRAM,
After the “L” level busy flag / Busy is generated, an address C and a command are issued again and supplied to the synchronous interface circuit 20. Then, after the reissued address C and command are supplied, the clock signal CLK rises.

By the way, after the address controller 21 outputs the internal address for a predetermined period, all the bits are fixed to the "H" level or the "L" level, so that the re-issued address C is supplied. The busy flag / Busy output from the address comparator 23 rises to “H” level by being compared with the output from the address controller 21 by the address comparator 23.

Therefore, thereafter, in the busy cycle, the address C and the command are fetched and held by the address controller 21 and the command controller 22,
The internal address C corresponding to the address C is the DRAM core unit 1
0, and decoding is performed based on the command held by the command controller 22, and “L”
The level read signal / RD is supplied to the DRAM core unit 10. Thereafter, a memory cell corresponding to the internal address C is selected from the DRAM core unit 10, data is read from the selected memory cell, and output as read data QC via the synchronous interface circuit 20.

On the other hand, in the case of a write cycle, a command supplied from the outside corresponds to a write operation (/ WE = “L” level), and instead of a read signal / RD, a “L” level write signal / The only difference is that WT is output from the command controller 22 and that write data D (DD or DE) is externally supplied to the DRAM core unit 10 and data is written to a selected memory cell corresponding to an internal address. , Etc. are the same as those in the read cycle, and the description thereof is omitted.

As described above, when data is read from a plurality of memory cells having different bit lines or data is continuously written to a plurality of memory cells having different bit lines, the data inputted in the previous cycle is input. Before the precharge operation of the bit line connected to the memory cell corresponding to the address is completed, data is read from or written to the memory cell corresponding to the address input in the next cycle. Since this is performed, the cycle time, that is, the period of the previous tcy can be shortened.

That is, the DRAM according to the above embodiment
Thus, the operation speed of the random access operation in a plurality of memory cells that do not share a bit line can be improved.

Next, a second embodiment of the present invention will be described.

FIG. 5 is a block diagram showing a configuration of a DRAM according to the second embodiment. In FIG. 5, FIG.
The same reference numerals are given to the portions corresponding to and the description thereof will be omitted.

In the DRAM of FIG. 1, the address comparator 23
The busy flag / Busy output from the AND circuit 2
4 and when the busy flag / Busy is at “H” level, the supply of the clock signal CLK to the address controller 21 and the command controller 22 is stopped.
Address controller 21 and command controller 2
2, the operation of taking in the address and command was stopped. Therefore, in the DRAM of FIG. 1, it is necessary to reissue the address and the command by the external logic circuit thereafter.

On the other hand, in the DRAM of FIG. 5, delay circuit 2 delays busy flag / Busy for one cycle period.
5, busy flag / B delayed by one cycle period
usy is supplied to the AND circuit 24.

With such a configuration, even if the busy flag / Busy is generated in the synchronous interface circuit 20, the reception of the input address and the command in that cycle is validated, and the address controller 21 and the command controller 22 perform the processing for one cycle. Retained
At the same time as being used in the next cycle, reception of addresses and commands is suspended.

According to the DRAM of the second embodiment, the same effects as those of the DRAM of the first embodiment can be obtained. Since it is not necessary to supply the same address and command, there is an effect that control of an external logic circuit becomes easy.

[0049]

As described above, according to the semiconductor memory device of the present invention, the cycle time is the longest when a plurality of memory cells connected to the same bit line are successively accessed. That is, the minimum cycle time can be set in accordance with the case where a plurality of memory cells connected to different bit lines are continuously accessed, and the performance of the memory can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM according to a first embodiment of the present invention.

FIG. 2 is a block diagram extracting and showing a configuration of a memory cell array part of a DRAM core part in FIG. 1;

FIG. 3 is a circuit diagram around a memory cell in FIG. 2;

FIG. 4 is a timing chart showing an example of the operation of the DRAM according to the first embodiment.

FIG. 5 is a block diagram showing a configuration of a DRAM according to a second embodiment.

FIG. 6 is a conceptual diagram showing an operation example of a DRAM when a plurality of memory cells sharing a bit line are continuously accessed.

[Explanation of symbols]

10: DRAM core unit, 20: Synchronous DRAM inter
face) circuit, 21 ... address controller, 22 ... command controller, 23 ... address comparator, 24 ... AND circuit, 25 ... delay circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yoshiyoshi Tokushige 1-term, Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa F-term in Toshiba Microelectronics Center Co., Ltd. 5B024 AA15 BA21 BA23 BA29

Claims (10)

[Claims] 1. A memory device comprising a bit line, a plurality of memory cells connected to one bit line, and data writing or selecting memory for a selected memory cell selected in accordance with an address inputted in each cycle. Compare the memory circuit from which data is read from the cell with the addresses input in the previous cycle and the current cycle, and determine whether the memory cell selected according to both addresses is a memory cell connected to the same bit line And a flag generation circuit for generating a flag indicating whether or not the semiconductor memory device is a semiconductor memory device. 2. The semiconductor memory device according to claim 1, further comprising an address control circuit for holding said input address and supplying said address to said memory circuit. 3. When a flag generated by the flag generation circuit indicates that a memory cell selected in accordance with the two addresses is a memory cell connected to the same bit line, the flag based on the flag is used. 3. The semiconductor memory according to claim 2, further comprising a control circuit for stopping the operation of holding the address of the current cycle in the address control circuit and holding the address input from the next cycle. apparatus. 4. A command for inputting various commands for controlling the operation of the memory circuit, and outputting a control signal for controlling at least data read and write operations of the memory circuit to the memory circuit based on the commands. 4. The semiconductor memory device according to claim 3, further comprising a control circuit. 5. The control circuit according to claim 1, wherein the flag generated by the flag generation circuit indicates that a memory cell selected according to the two addresses is a memory cell connected to the same bit line. Controlling the command control circuit to stop the output operation of the control signal based on the command of the current cycle based on the flag, and to output the control signal based on the command input from the next cycle to the memory circuit. 5. The semiconductor memory device according to claim 4, wherein said operation is performed. 6. When a flag generated by the flag generation circuit indicates that a memory cell selected in accordance with the two addresses is a memory cell connected to the same bit line, the flag is determined based on the flag. 3. The semiconductor memory device according to claim 2, further comprising a control circuit for controlling the address control circuit to hold an address of a current cycle and maintain the current cycle until the next cycle. 7. A command for inputting various commands for controlling the operation of the memory circuit, and outputting a control signal for controlling at least data read and write operations of the memory circuit to the memory circuit based on the commands. 7. The semiconductor memory device according to claim 6, further comprising a control circuit. 8. The control circuit according to claim 1, wherein the flag generated by the flag generation circuit indicates that a memory cell selected according to the two addresses is a memory cell connected to the same bit line. And controlling the command control circuit to hold the command of the current cycle until the next cycle based on the flag, and to output the control signal based on the held command. 8. The semiconductor memory device according to 7. 9. A memory cell having a bit line, a plurality of memory cells connected to one bit line, a memory cell selected according to an address inputted in each cycle, and writing of data to the selected memory cell. Or, a memory circuit from which data is read from a selected memory cell, an address control circuit that holds an input address and supplies the memory circuit, and various commands for controlling the operation of the memory circuit are input, A command control circuit for outputting to the memory circuit a control signal for controlling at least data read and write operations of the memory circuit based on the command; an address of a previous cycle held by the address control circuit; Address, and both addresses correspond to the memory cells connected to the same bit line. A flag generation circuit for generating a flag indicating whether the address is an address or not, and the flag and the synchronization signal are supplied. And a logic circuit that outputs a synchronization signal. 10. A memory cell having a bit line, a plurality of memory cells connected to one bit line, a memory cell selected according to an address inputted in each cycle, and writing of data to the selected memory cell. Or, a memory circuit from which data is read from a selected memory cell, an address control circuit that holds an input address and supplies the memory circuit, and various commands for controlling the operation of the memory circuit are input, A command control circuit for outputting to the memory circuit a control signal for controlling at least data read and write operations of the memory circuit based on the command; an address of a previous cycle held by the address control circuit; Address, and both addresses correspond to the memory cells connected to the same bit line. A flag generating circuit for generating a flag indicating whether or not the address is a delayed address, a delay circuit for delaying the flag generated by the flag generating circuit for a period of one cycle and outputting the same, and an output of the delay circuit and a synchronization signal. And a logic circuit for outputting the synchronization signal to the address control circuit and the command control circuit as a synchronization signal for fetching an address and a command based on an output of the delay circuit.