JP3219964B2 - Power down memory control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-down memory control unit comprising a memory module having a dynamic random access memory for performing a forced refresh at a constant period, and particularly to reducing power consumption of a random access memory that is not accessed. A power down memory control unit configured as described above.

[0002]

2. Description of the Related Art In a conventional power down control unit, for example, as described in Japanese Patent Publication No. 60-263396, power is completely supplied to a dynamic random access memory which is set to be unusable. In this case, the power consumption is reduced by stopping the operation.

[0003]

In the above-mentioned conventional power-down control unit, power is resupplied in order to enable the use of the dynamic random access memory once set as unusable. Time required for stabilization and dummy write to enable dynamic random access memory
Is time consuming and overhead occurs.

[0004] Further, there is a disadvantage that the data in the dynamic random access memory is erased by stopping the power supply.

[0005]

According to the power down control unit of the present invention, (a) each writes and reads data by a control timing signal, generates a divided clock from an external clock signal, and outputs the divided clock by a clock selection signal. A plurality of clock signals and one of the divided clock signals, which operate in synchronization with the selected clock signal, stop the operation when the divided clock is selected, and execute a forced refresh at a constant cycle; A plurality of memory modules each having the dynamic random access memory; (b) a control timing signal generation circuit for supplying the control timing signal to each of the memory modules; and (c) a clock selection circuit for each of the memory modules. And a clock selection signal circuit for supplying a signal.

[0006]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. Referring to FIG. 1 , in the embodiment of the present invention, a divided clock is generated from a control timing generation circuit 1, a clock selection signal circuit 17, and an external clock signal input from the outside, and a clock selection signal input from the outside is selected. The memory modules 18 to 21 each comprise a synchronous dynamic random access memory which selects one of the external clock signal and the divided clock signal by a signal and operates in synchronization with the clock signal.

[0008] Next, the operation with reference to FIGS. 1 and 2 will be described in detail.

The case where the memory module 20 is accessed and the memory modules 18 to 19 and 21 are not accessed will be described.

In this case, a control timing signal is generated from the control timing generation circuit 1 to the signal line 1C, and the signal line 1A
1B and 1D do not have any control timing.

The clock selection signal circuit 17 is controlled by a selection signal 1E from the control timing generation circuit 1, and outputs clock selection signals 17A, 17A,
7B, 17C, and 17D are '0', '0',
'1' and '0'.

Therefore, in all the synchronous dynamic random access memories in the memory module 20, the normal clock is selected and the normal operation is performed, but in the synchronous dynamic random access memories in the memory modules 18 to 19 and 21, the frequency division is performed. The clock is selected and all of these synchronous dynamic random access memories stop operating. Since the operation is stopped, power consumption is suppressed. Further, in the synchronous dynamic random access memory in which the operation is stopped, the forced refresh is executed at a constant cycle to secure data.

[0013] As shown in FIG. 2 is a synchronous dynamic random access memory, is supplied external clock signal from the clock supply line 45, a clock divider circuit 4
Divided by two. The selector 41 selects one of the external clock from the clock signal line 45 and the clock signal 46 from the clock dividing circuit 46 in accordance with the clock selection signal 44.
Select for internal use.

[0014] In the above embodiment, the memory module 20
Although only the case where only one module is accessed has been described, even when another module is accessed, only the module that is similarly accessed operates, the other modules stop operating, and power consumption is suppressed.

[0015]

As described above, the power down memory control unit of the present invention achieves suppression of power consumption by suppressing clock supply and frequency division of the dynamic random access memory of a memory module set to be unusable. There is an effect that can be. Furthermore, by continuing to supply power and performing forced refresh,
When the module is set to be usable again, the time required for stabilization of the power supply and the time required for dummy writing for enabling the dynamic random access memory are eliminated, and there is an effect that overhead does not occur. Further, there is an effect that data in the dynamic random access memory is maintained without being erased.

[Brief description of the drawings]

1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a synchronous dynamic random access memory used in an embodiment of the present invention.

[Explanation of symbols]

 1 Control timing generation circuit18, 19, 20, 21 memory module 11, 45 clock signal  17 Clock selection signal circuit41 Selector 40 Synchronous dynamic random access menu
Memory 42 Clock divider 1A, 1B, 1C, 1D Control timing signal 1E Select signal 17A, 17B, 17C, 17D Clock select signal43 Control timing generation circuit 47 Divided clock signal

Claims (1)

(57) [Claims] (A) writing and reading data by a control timing signal to generate a frequency-divided clock from an external clock signal; and selecting one of the external clock signal and the frequency-divided clock signal by a clock selection signal. A plurality of memory modules having a plurality of dynamic random access memories that select and operate in synchronization with the selected clock signal, stop operation when the divided clock is selected, and execute forced refresh at a fixed cycle; (B) a control timing signal generation circuit for supplying the control timing signal to each of the memory modules; and (c) a selection signal from the control timing signal generation circuit.
And a clock selection signal circuit for supplying the clock selection signal to each of the memory modules based on the above.