JPH08273355A - Control unit for power down memory - Google Patents

Abstract

PURPOSE: To preserve an unavailable data while reducing power consumption when a memory module comprising a dynamic random access memory is set unavailable and to eliminate the overhead at the time of resuming the data. CONSTITUTION: A control timing generation circuit 1 interrupts the generation of control timing signal for a memory module being set unavailable. A gate control circuit 2 gates the clock signal at gate circuits 7 through 10 based on a gate signal and inhibits the delivery of clock signal to a memory module being set unavailable. Upon inhibition of clock signal supply, the dynamic random access memories in modules 3 through 6 recognize the unavailability to stop the operation and executes the refresh operation forcibly at a constant period.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power-down memory control unit composed of a memory module having a dynamic random access memory for performing forced refresh in a constant cycle, and particularly reduces power consumption of a random access memory which is not accessed. And a power down memory control unit.

[0002]

2. Description of the Related Art In a conventional power-down control unit, for example, as described in Japanese Patent Publication No. 60-263396, power is completely supplied to a dynamic random access memory set to be unusable. The power consumption is reduced by stopping the power supply.

[0003]

In the conventional power-down control unit described above, in order to enable the dynamic random access memory once set to be unusable, the power is resupplied. Stabilization time and dummy write to enable dynamic random access memory
However, there is a drawback in that it takes time and overhead is generated.

Further, there is a disadvantage that the data in the dynamic random access memory is erased by stopping the power supply.

[0005]

According to a first power-down control unit of the present invention, (a) each writes and reads data by a control timing signal, operates in synchronization with a clock signal, and stops the clock signal. A plurality of memory modules having a plurality of dynamic random access memories that stop the operation by the above and execute a forced refresh at a constant cycle; and (b) a control timing signal generation circuit that supplies the control timing signal to each of the memory modules, (C) a plurality of gate circuits that gate the clock signal supplied to each of the memory modules for each memory module; and (d) a gate control circuit that supplies a gate control signal to control each of the gate circuits. , Are provided.

In the second power-down control unit of the present invention, (a) each writes or reads data according to a control timing signal, and when the voltage variable signal indicates a step-down, the voltage supplied to the internal memory cell is an external voltage. A memory module having a plurality of dynamic random access memories that lower the voltage, stop the operation, and execute a forced refresh at a constant cycle; and (b) a control timing signal generation circuit that supplies the control timing signal to each of the memory modules. , (C) a voltage variable circuit that supplies the voltage variable signal to each of the memory modules.

In the third power-down control unit of the present invention, (a) each writes / reads data according to a control timing signal, creates a divided clock from an external clock signal, and uses the clock selection signal to generate the divided clock and the external clock signal. A plurality of dynamic random numbers that select any one of the divided clock signals and operate in synchronization with the selected clock signal, and stop the operation when the divided clock is selected and execute forced refresh at a constant cycle. A plurality of memory modules having an access memory,
(B) a control timing signal generation circuit that supplies the control timing signal to each of the memory modules,
(C) A clock selection signal circuit that supplies the clock selection signal to each of the memory modules.

[0008]

The present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. Referring to FIG. 1, the first embodiment of the present invention includes a control timing generation circuit 1 and a gate control circuit 2.
And memory modules 3 to 6 composed of synchronous dynamic random access memories that operate in synchronization with a clock, and gate circuits 7 to 10.

Next, the operation will be described in detail.

A case where the memory module 3 is accessed but the memory modules 4 to 6 are not accessed will be described.

In this case, the control timing signal is generated from the control timing generating circuit 1 to the signal line 1A, and the signal line 1B is generated.
From 1 to 1D, no control timing occurs.

The control timing signal is, for example, a chip selection, a row address selection, a column address selection, a write enable, etc., and a logical product of the chip selection and the row address selection activates access to the dynamic random access memory. A read operation or a write operation is executed by the logical product of chip selection and column address selection. At this point, if the write enable is on, the write operation is executed, and if it is off, the read operation is executed. Finally, the operation is completed by the logical product of the three signals of chip selection, row address selection and write enable.

The gate control circuit 2 is controlled by the selection signal 1E from the control timing generation circuit 1, and outputs 2A, 2B, 2C and 2D from the gate control circuit 2 are "1", "0" and "0", respectively. , '0'.

The gate circuits 7 to 10 each have 2 A
To 2D and the clock signal 11 are ANDed, the clock signal is supplied only to the clock signal line 7A, and the clock signal is not supplied to the clock signal lines 8A to 10A.

That is, the clock signal is supplied only to the memory module 3 and not to the memory modules 4 to 6. Therefore, the clock signal is supplied to all the synchronous dynamic random access memories in the memory module 3 and the normal operation is performed, but the clock signal is not supplied to the synchronous dynamic random access memories in the memory modules 4 to 6. , All of these synchronous dynamic random access memories stop operating. Power consumption is suppressed due to the stop of the operation. Further, in the synchronous dynamic random access memory which has stopped the operation, forced refresh is executed at a constant cycle to secure data.

In the above-described first embodiment, the case where only the memory module 3 is accessed has been described. However, even when the other modules are accessed, only the accessed module operates in the same manner, The module stops operating and power consumption is reduced.

Next, the second embodiment will be described in detail.

FIG. 2 is a block diagram showing a second embodiment of the present invention. Referring to FIG. 2, the second embodiment of the present invention includes a control timing generation circuit 1 and a voltage variable circuit 12.
And a memory module 13 to 16 composed of a dynamic random access memory that lowers the voltage supplied to the internal memory cell below the external voltage when the voltage variable signal input from the outside indicates the step down.

Next, the operation will be described in detail with reference to FIGS. 2 and 4.

A case where the memory module 14 is accessed and the memory modules 13, 15 to 16 are not accessed will be described.

In this case, the control timing signal is generated from the control timing generation circuit 1 to the signal line 1B,
No control timing occurs in A, 1C to 1D.

Further, the voltage variable circuit 12 is controlled by the selection signal 1E from the control timing generation circuit 1, and the voltage variable signals 12A, 12B, 12 output from the voltage variable circuit 12 are controlled.
C and 12D are "1", "0", "1",
It becomes "1".

Therefore, in all the dynamic random access memories in the memory module 14, the normal voltage is supplied and the normal operation is performed.
In a dynamic random access memory within 3, 15 to 16, the voltage is stepped down and all these dynamic random access memories stop operating. Power consumption is suppressed due to the stop of the operation. In addition, in the dynamic random access memory which stopped the operation,
Forced refresh is executed at regular intervals to maintain data.

In the dynamic random access memory, as shown in FIG. 4, the external power supply is supplied from the power supply line 36 and stepped down by the voltage step-down circuit 32. Power supply line 3
6 from the external power source or the power source 37 from the voltage step-down circuit 32 according to the voltage variable signal 34.
Select 1 and use internally.

In the above-mentioned second embodiment, the case where only the memory module 14 is accessed has been described. However, even when other modules are accessed, only the module being accessed operates in the same manner, The module stops operating and power consumption is reduced.

It is needless to say that the dynamic random access memory in the second embodiment described above includes a synchronous dynamic random access memory.

Next, the third embodiment will be described in detail.

FIG. 3 is a block diagram showing a third embodiment of the present invention. Referring to FIG. 3, the third embodiment of the present invention generates a divided clock from a control timing generation circuit 1, a clock selection signal circuit 17, and an external clock signal input from the outside, and inputs the divided clock from the outside. A clock selection signal for selecting either the external clock signal or the divided clock signal and operating in synchronization with this clock signal. The memory modules 18 to 21 are composed of synchronous dynamic random access memories. ing.

Next, the operation will be described in detail with reference to FIGS. 3 and 5.

A case where the memory module 20 is accessed and the memory modules 18 to 19 and 21 are not accessed will be described.

In this case, a control timing signal is generated from the control timing generation circuit 1 to the signal line 1C, and the signal line 1A
From 1B to 1D, no control timing is generated.

Further, the clock selection signal circuit 17 is controlled by the selection signal 1E from the control timing generation circuit 1, and the clock selection signals 17A and 1A, 1A, which are outputs from the clock selection signal circuit 17
7B, 17C and 17D are respectively "0", "0",
It becomes "1" and "0".

Therefore, in all the synchronous dynamic random access memories in the memory module 20, the normal clock is selected and the normal operation is performed, but in the synchronous dynamic random access memories in the memory modules 18 to 19 and 21, the frequency division is performed. The clock is selected and all these synchronous dynamic random access memories stop operating. Power consumption is suppressed due to the stop of the operation. Further, in the synchronous dynamic random access memory which has stopped the operation, forced refresh is executed at a constant cycle to secure data.

In the synchronous dynamic random access memory, as shown in FIG. 5, an external clock signal is supplied from the clock supply line 45, and the clock frequency dividing circuit 4 is supplied.
Divided by 2. Either the external clock from the clock signal line 45 or the clock signal 46 from the clock divider circuit 46 is selected according to the clock selection signal 44.
Select with and use internally.

In the above-mentioned third embodiment, the case where only the memory module 20 is accessed has been described. However, even when other modules are accessed, only the module that is being accessed operates in the same manner, and other modules are accessed. The module stops operating and consumes less power.

[0037]

As described above, the power down memory control unit of the present invention consumes power by suppressing the clock supply of the dynamic random access memory of the memory module which is set to be unusable, reducing the voltage, and dividing the clock. The effect of being able to achieve the deterrence of In addition, by continuing to supply power and performing forced refresh, when the module is set to enable again, the time required for power supply to stabilize and dummy write to enable the dynamic random access memory are set. The effect is that the time required is removed and no overhead occurs. Further, there is an effect that the data in the dynamic random access memory is not erased and is preserved.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

FIG. 3 is a block diagram of a third embodiment of the present invention.

FIG. 4 is a block diagram of a dynamic random access memory used in the second embodiment of the present invention.

FIG. 5 is a block diagram of a synchronous dynamic random access memory used in a third embodiment of the present invention.

[Explanation of symbols]

1 Control Timing Generation Circuit 2 Gate Control Circuit 3, 4, 5, 6, 13, 14, 15, 16, 18, 1
9, 20, 21 Memory module 7, 8, 9, 10 Gate circuit 11, 7A, 8A, 9A, 10A, 45, 47 Clock signal 12 Voltage variable circuit 17 Clock selection signal circuit 30 Dynamic random access memory 31, 41 Selector 32 Voltage step-down circuit 40 Synchronous dynamic random access memory 42 Clock frequency divider circuit 1A, 1B, 1C, 1D Control timing signal 1E Selection signal 2A, 2B, 2C, 2D Gate control signal 12A, 12B, 12C, 12D, 34 Voltage variable signal 17A, 17B, 17C, 17D Clock selection signal 33, 43 Control timing generation circuit 36 External power supply 37 Step-down power supply 38 Internal power supply 47 Divided clock signal

Claims (3)

[Claims] 1. A plurality of dynamic memories, each of which writes and reads data by a control timing signal, operates in synchronization with a clock signal, stops the operation by stopping the clock signal, and executes a forced refresh at a constant cycle. A plurality of memory modules having random access memories; (b) a control timing signal generation circuit for supplying the control timing signal to each of the memory modules; and (c) a clock signal supplied to each of the memory modules. A plurality of gate circuits that gate each memory module, and (d) a gate control circuit that supplies a gate control signal that controls each of the gate circuits,
A power-down memory control unit comprising: 2. When (a) each writes or reads data according to a control timing signal and the voltage variable signal indicates a step-down, the voltage supplied to the internal memory cell is stepped down below the external voltage and the operation is stopped for a fixed period. A memory module having a plurality of dynamic random access memories for executing forced refresh in (b) a control timing signal generation circuit for supplying the control timing signal to each of the memory modules, and (c) each of the memory modules. And a voltage variable circuit for supplying the voltage variable signal to the power down memory control unit. 3. (a) Each writes and reads data by a control timing signal to create a divided clock from an external clock signal, and selects either the external clock signal or the divided clock signal by a clock selection signal. A plurality of memory modules having a plurality of dynamic random access memories that select and operate in synchronization with the selected clock signal, stop the operation when the divided clock is selected, and execute a forced refresh at a constant cycle; (B) A control timing signal generation circuit for supplying the control timing signal to each of the memory modules, and (c) a clock selection signal circuit for supplying the clock selection signal to each of the memory modules. A power-down memory control unit characterized by the above.