JP2000040360A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of reducing power consumption at the time RAS(row address strobe signal) is in an 'L' stand-by by controlling operations of buffer circuits for internal step-down voltage. SOLUTION: This memory is a 64M-bit DRAM and it is constituted of a memory array and its peripheral circuits or the like and in the internal step- down power source circuit to be incorporated in the internal power source voltage generating circuit of the peripheral circuit. An internal power source voltage down level sensor VDLS and plural internal step-down level buffer circuit VDLB are included. The internal step-down source circuit is constituted so as to prohibit operations of buffer circuits for internal step-down power source VDLB1 of one part of the circuit by controlling operations of other internal step-down level buffer circuit VDLB1 except a minimum internal step- down level buffer circuit assuring the 'L' stand-by state of the RAS among the buffer circuits for internal step-down power source VDLB by the output of the sensor VDLS while operating the internal power source voltage level sensor VDLS at the time the RAS is in the 'L' stand-by.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology of a semiconductor memory device, and more particularly, to a RAS "L" Stan in a state capable of always supporting read / write access during standby due to a low level of a row address strobe signal.
The present invention relates to a technique that is effective when applied to a semiconductor memory device such as a DRAM suitable for low power consumption during d-by.

[0002]

2. Description of the Related Art For example, as a technique studied by the present inventors, in a semiconductor memory device such as a DRAM which operates at high speed by using an internal step-down power supply for a circuit in a chip, the level of the internal step-down power supply at the time of high-speed operation In order to assure the above, a technique of arranging a large number of differential buffer circuits having large MOS constants in the peripheral circuit section can be considered.

[0003] As a technique related to such a semiconductor memory device such as a DRAM, for example,
The technology described in “Advanced Electronics I-9 Ultra LSI Memory” issued by Baifukan Co., Ltd. on May 5 is exemplified.

[0004]

In a semiconductor memory device such as a DRAM as described above, the enable of the buffer circuit of the internal step-down power supply is usually RAS synchronous, so that the RAS "L" Stand-by signal is not used. Even when most loads do not operate, the current at the time of RAS “L” Stand-by is large due to the current at the time of enabling the buffer circuit. That is, it is considered difficult to reduce the current consumption in order to guarantee the stable operation of the circuit.

An object of the present invention is to control the operation of a buffer circuit for an internal step-down power supply, thereby providing a RAS.
An object of the present invention is to provide a semiconductor memory device such as a DRAM which can reduce power consumption during "L" Stand-by.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device according to the present invention uses an internal step-down power supply for a circuit in a chip, and is applied to a semiconductor memory device having a plurality of buffer circuits for the internal step-down power supply for performing high-speed operation. And the RAS
At the time of "L" Stand-by, the internal step-down power supply level sensor which consumes low current is operated, and the output controls the enable signal of some buffer circuits for the internal step-down power supply.

In this configuration, each of the plurality of buffer circuits comprises a MOS transistor circuit for comparing the voltage level of the internal step-down power supply with the reference voltage level.
The OS transistor circuit has a large MOS constant and a negative feedback configuration, while the internal step-down power supply level sensor compares the voltage level of the internal step-down power supply with the reference voltage level.
The MOS transistor circuit has a small MOS constant and has no feedback.

Therefore, according to the semiconductor memory device, the operation of a part of the buffer circuit for the internal step-down power supply is inhibited, so that the current consumption in the buffer circuit can be reduced.
Power consumption during S “L” Stand-by can be reduced. As a result, the power consumption of the product can be reduced. In particular, it is suitable for DRAMs and the like, and is also applicable to other LSIs and the like using an internal step-down power supply.

This is because the power consumption can be reduced by operating the level sensor having a lower current consumption than the current when the buffer circuit is enabled, instead of the buffer operation.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic block diagram showing a semiconductor memory device according to one embodiment of the present invention, and FIG. 2 is a circuit diagram showing an internal step-down power supply circuit in the semiconductor memory device of this embodiment.

First, the configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 64-Mbit DRAM, and includes a memory cell array MCA including a plurality of memory cells, a row address buffer RAB for designating an address of the memory cell array MCA, and a column address buffer. CAB, row decoder RDE, column decoder CDE, row driver RD
R, a column driver CDR, a sense amplifier SA for reading / writing data, a main amplifier MA, an output buffer DOB, and an input buffer DIB.
And known configurations such as control signal buffers RB, CB, and WB, and an internal voltage generation circuit VG. These components are formed on a single semiconductor chip by a known semiconductor manufacturing technique.

An address signal Ai is externally input to this DRAM, and a row address signal and a column address signal are generated by a row address buffer RAB and a column address buffer CAB.
DE and row driver RDR, column decoder CDE
An arbitrary memory cell in memory cell array MCA is selected via column driver CDR. During the read operation, the sense amplifier SA and the input / output line I /
O, output data Do is output from the output buffer DOB via the main amplifier MA, and input data Di is input from the input buffer DIB during a write operation.

Further, as a control signal of the DRAM, a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal /
WE and the like are input via buffers RB, CB, and WB, respectively, and an internal control signal is generated based on these control signals, and the operation of the internal circuit is controlled by the internal control signal. In addition, the internal power supply system has a power supply voltage V
DD and the ground voltage VSS are input, and the internal voltage generation circuit V
G generates various internal voltage levels such as a substrate power supply, a step-up power supply, and a step-down power supply.
It is supplied to internal circuits such as CA and its peripheral circuits.

In particular, in the present embodiment, the circuit configuration of the internal step-down power supply circuit VDLG built in the internal voltage generating circuit VG is devised so that the internal step-down power supply which consumes low current during RAS "L" Stand-by. The level sensor is operated, and the enable signal of some buffer circuits for the internal step-down power supply can be controlled by this output. In this case, RAS “L” Stan
The minimum buffer circuit that guarantees the d-by state is operable.

That is, as shown in FIG. 2, for example, the internal step-down power supply circuit VDLG includes an internal step-down power supply level sensor VDLS and a plurality of internal step-down power supply buffer circuits VD.
LB. Buffer circuit V for internal step-down power supply
Since the DLB has a large constant and has negative feedback, the current consumption increases. On the other hand, since the internal step-down power supply level sensor VDLS has a small constant and no feedback, the current consumption can be reduced.

The internal step-down power supply level sensor VDLS includes PMOS transistors TP1 to TP3, N as shown in FIG.
MOS transistors TN1 to TN5, inverter IV
1, delay circuit DLY1 and NOR gate NO
A row address strobe signal RAS is input to the delay circuit DLY1, and an enable signal is input to the gates of the NMOS transistors TN3 and TN5. The delay circuit DLY1 operates in synchronization with the row address strobe signal RAS.

In this configuration, the reference level and the NMOS transistor T are connected to the gate of the NMOS transistor TN1.
An internal step-down power supply is applied to the gate of N2. When the internal step-down power supply is higher than the reference level, a low level control signal is output. When the internal step-down power supply is lower than the reference level, a high level control signal is output to the internal step-down power supply buffer circuit VDLB.

The internal step-down power supply buffer circuit VDLB
As shown in FIG.
A control signal from the internal step-down power supply level sensor VDLS is input to the gates of the NMOS transistors TN8 and TN9. The control signal is synchronized with the row address strobe signal RAS similarly to the internal step-down power supply level sensor VDLS. It is configured to operate.

In this configuration, the reference level and the NMOS transistor T are connected to the gate of the NMOS transistor TN6.
An internal step-down power supply is applied to the gate of N7, and the internal step-down power supply operates when the internal step-down power supply is equal to or higher than the reference level and equal to or lower than the reference level.
B to ensure the level of the internal step-down power supply at the time of high-speed operation, as well as the RAS “L” Stand-b
The operation at the time of y is also controlled.

Next, a method of controlling the operation of the plurality of internal step-down power supply buffer circuits VDLB for the operation of the present embodiment will be described.

For example, an internal step-down power supply level sensor VD
LS compares the reference level applied to the gate of the NMOS transistor TN1 with the internal step-down power supply applied to the gate of the NMOS transistor TN2. When the internal step-down power supply is equal to or higher than the reference level, the NMOS transistor TN2 is turned on. , The NMOS transistor TN1 is turned off, and the NMOS transistor TN4 is turned on.

The low-level signal due to the ON state of the NMOS transistor TN4 is inverted through the inverter IV1 to be at the high level, and the other is the NOR gate NOR1 to which the row address strobe signal RAS is input via the delay circuit DLY1. , And outputs a low-level control signal.

Some of the internal step-down power supply buffer circuits VDLB1 among the plurality of internal step-down power supply buffer circuits VDLB receive a low-level control signal as an input.
Based on this control signal, the NMOS transistors TN8,
TN9 is gate-controlled, and the NMOS transistor TN
8, TN9 are turned off, and some internal step-down power supply buffer circuits VDLB1 are disabled.

An internal step-down power supply level sensor VDLS
Except for the internal step-down power supply buffer circuit VDLB1 which receives the control signal from
The DLB2 is always enabled by a control signal of another system without passing through the internal step-down power supply level sensor VDLS.

As a result, the RAS "L" Stand-b in a state where it can always respond to read / write access.
At the time of y, only the minimum internal step-down power supply buffer circuit VDLB2 that guarantees this state is operated, and other internal step-down power supply buffer circuits VDLB1 other than this can be prohibited from operating.

For example, in a 64-Mbit DRAM, when the internal step-down power supply for a power supply voltage of 3.3 V is 2.2 V, the internal step-down power supply is compared with a reference voltage of 2 V, and the RAS "L" Stand is lower than the reference voltage. At -by, the operation of three internal step-down power supply buffer circuits VDLB1 of the four internal step-down power supply buffer circuits VDLB is prohibited, and only one internal step-down power supply buffer circuit VDLB2 is operated. .

Therefore, according to the semiconductor memory device of the present embodiment, except for the minimum internal step-down power supply buffer circuit VDLB2 except for the minimum internal step-down power supply buffer circuit VDLB2 which guarantees the RAS "L" Stand-by state, The operation is controlled, and a part of the internal step-down power supply buffer circuit VDLB is controlled.
By disabling the operation of the internal step-down power supply buffer circuit VDLB, the internal step-down power supply level sensor VDLS, which consumes a lower current than the current when the internal step-down power supply buffer circuit VDLB is enabled, is operated instead of the internal step-down power supply buffer circuit VDLB. The current consumption of the internal step-down power supply buffer circuit VDLB can be reduced, and the power consumption during RAS “L” Stand-by can be reduced.

It should be noted that such a plurality of internal step-down power supply buffer circuits VDLB and internal step-down power supply level sensors VDL
The configuration including S controls the oscillator based on the output signal of the level sensor, for example, and not only has a different purpose of use but also uses an oscillator when compared with a boost power supply circuit that generates a boost power supply through a charge pump circuit. The difference is that the buffer circuit VDLB2 always operates with a minimum internal step-down power supply buffer circuit.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above embodiment, 6
Although the case where the present invention is applied to a 4M bit DRAM has been described, the present invention is not limited to this, and the present invention is also applicable to a DRAM having a larger capacity such as 256M bit. Furthermore, not limited to DRAM, synchronous DRA
The present invention can be widely applied to other semiconductor memory devices using an internal step-down power supply, such as M and Rambus specification DRAMs.

[0035]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) The provision of the internal step-down power supply level sensor for comparing the voltage level of the internal step-down power supply with the reference voltage level enables the internal step-down power supply level sensor to operate during RAS “L” Stand-by. Since only the minimum buffer circuit can be operated based on the output and the operation of the other buffer circuits can be prohibited, the current consumption in the buffer circuit can be reduced and the RAS "L" Stand-
It is possible to reduce the power consumption at the time of by.

(2) Since the internal step-down power supply level sensor uses a MOS transistor circuit having a smaller MOS constant than the buffer circuit and having no feedback, the current consumption is lower than the current when the buffer circuit is enabled. Since a certain internal step-down power supply level sensor can be operated instead of the buffer operation, low power consumption can be achieved.

(3) According to the above (1) and (2), in a semiconductor memory device such as a DRAM using an internal step-down power supply, stable operation of the circuit at the time of high-speed operation is guaranteed, and low power consumption due to low current consumption is achieved. Can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing an internal step-down power supply circuit in the semiconductor memory device according to one embodiment of the present invention;

[Explanation of symbols]

MCA memory cell array RAB row address buffer CAB column address buffer RDE row decoder CDE column decoder RDR row driver CDR column driver SA sense amplifier MA main amplifier DOB output buffer DIB input buffer RB, CB, WB buffer VG internal voltage generation circuit VDLG internal step-down power supply Circuit VLLS Internal step-down power supply level sensor VDLB, VDLB1, VDLB2 Internal step-down power supply buffer circuit TP1 to TP6 PMOS transistors TN1 to TN9 NMOS transistor IV1 Inverter DLY1 Delay circuit NOR1 NOR gate

Claims (4)

[Claims] 1. A semiconductor memory device including an internal step-down power supply and a plurality of buffer circuits for the internal step-down power supply for guaranteeing the voltage level of the internal step-down power supply, wherein the voltage level of the internal step-down power supply and a reference Compare with the voltage level,
An internal step-down power supply level sensor for controlling the operation of the plurality of buffer circuits based on the comparison result, and operating the internal step-down power supply level sensor during standby at a low level of a row address strobe signal; A semiconductor memory device which controls operations of the plurality of buffer circuits based on an output of a level sensor. 2. The semiconductor memory device according to claim 1, wherein each of said plurality of buffer circuits compares a voltage level of said internal step-down power supply with said reference voltage level.
The MOS transistor circuit has a large MOS constant and a negative feedback configuration.
The internal step-down power supply level sensor includes a MOS transistor circuit that compares a voltage level of the internal step-down power supply with the reference voltage level, and has a small MOS constant and no feedback. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein an operation of another buffer circuit of the plurality of buffer circuits except for a buffer circuit that guarantees a standby state based on a low level of the row address strobe signal is performed. A semiconductor memory device which is prohibited. 4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a DRAM.