JPH08212134A - Semiconductor integrated circuit and power consumption reducing method for the same - Google Patents

Abstract

PURPOSE: To provide the semiconductor integrated circuit and power consumption reducing method for the same with which power consumption reduction and high-speed address comparison can be performed. CONSTITUTION: This circuit is provided with a row decoder 1 for inputting one part of a requested address and activating a prescribed word line 3 corresponding to this input, tag cell array 5 connected through the word line 3 to this row decoder 1 so as to output a prescribed tag address with activation, comparator 19 for comparing the tag address outputted from this tag cell array 5 with a block frame address, dummy cell array 13 formed simultaneously with the tag cell array 5 so as to output data by activating the prescribed word line 3, and comparator activating signal generator 17 for generating the activating signal of the comparator 19 at the timing of output. Corresponding to the activating signal, the comparator 19 judges whether comparing the tag address with the block frame address or not.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of high-speed address comparison with low power consumption.

[0002]

2. Description of the Related Art A semiconductor integrated circuit, particularly a cache memory, is required to have a high speed as the processing capability of a CPU is dramatically improved. FIG. 3 shows a computer system including a general cache memory, and the role of the general cache memory will be described. This computer system includes a CPU 21, a cache memory 23, and a main memory 25, which are connected to an address bus 33 and a data bus 35, respectively, and perform various input / output. When the CPU 21 requests the desired data, it is first confirmed whether or not this data is stored in the cache memory 23. For this confirmation, the tag cache 27 in which the tag address (the address of the main memory where the data was stored) is stored is accessed, and the comparison with the requested address is performed by the comparison unit 29. The data cache 31 is accessed only when the comparisons match. If they do not match, the cache is updated and the main memory 25 is accessed.

However, in the conventional cache memory, when the tag address and the block frame address are compared, even if two addresses are consecutively matched, the comparison operation is performed due to the deviation of the input timing ( Hit check). This example is shown in FIG.
An explanation will be given using (a). Block frame address,
When both the tag address and the tag address are at the low potential (L), the hit signals match each other, and hence the high potential (H) is set (state I in the figure). Here, for example, when the block frame address and the tag address state transition timings are shifted and the block frame address state transits first, the hit signals do not match even when the two addresses continuously match. The low potential (L) indicating the above state is shown (state II in the figure). Next, when the state of the tag address transits with a delay, the hit signal again shows a high potential (H) indicating a coincident state (state in the figure).
III). That is, the hit check is performed twice. Therefore, there is a problem that power consumption is consumed by unnecessary operation of the comparison unit 29 due to this hit check.

Therefore, the conventional cache memory is shown in FIG.
The above problem is avoided by the configuration as shown in FIG. The contents will be described below. The row decoder 1 inputs part of the address (index frame address) requested by a CPU (not shown), and searches the tag cell array 5 in which a predetermined tag address is stored. For this search, the row decoder 1 activates the corresponding word line 3, and a predetermined tag address is passed through the sense amplifier 15 to the comparator 1
Output to 9. The comparator 19 also receives another part (block frame address) of the address requested by the CPU and compares this block frame address with the output predetermined tag address. If they match, the data cache memory (not shown) is accessed. If they do not match, the cache is updated and the main memory is accessed.

In this conventional cache memory, a comparator activation signal generating circuit 37 is provided in order to prevent the comparator 19 from operating (activating), and the comparator activation signal generating circuit 37 outputs. The activation signal determines whether or not the comparison operation is performed. This content is shown in Figure 5.
This will be described with reference to FIG. As shown in FIG. 5B, when both the block frame address and the tag address are at the low potential (L), the hit signals match each other, and hence the high potential (H) is set (state I in the figure). ). here,
For example, when the timing of the state transition of the block frame address and the tag address is deviated and the state of the block frame address transits first, the comparator activation signal is set to avoid activation of the comparator 19. Set to low potential (L). As a result, the comparator is not activated and the hit signal does not change (state III in the figure).
). Next, since the state of the tag address transits with a delay, in the end, during the period when the deactivation signal is at the low potential, (the margin of the address to which the state transits first (state I in the figure
I)) + (Block frame address and tag address state transition timing is out of sync (state III in the figure)) + (margin of address to be changed later (state IV in the figure)) Become. As mentioned above,
During the period when the tag address and block frame address change, the power consumption is reduced by deactivating the comparator.

[0006]

In the conventional cache memory, the power consumption is reduced by deactivating the comparator during the period when the address is changing. There is a problem in determining the width of state IV) in the figure. That is, if the timing of activating the comparator is too early (state IV in the figure is too short), power consumption cannot be saved, and if the timing of activation is too late (state IV in the figure is long. Too much)
The output of the hit check becomes slow, which hinders the speedup. This timing has a power supply voltage dependency, a process dependency, a temperature dependency, etc., and these are intricately related, so it is very difficult to determine an appropriate timing margin. In particular, since fine cells are used in the cells, variations in tag address read time due to variations in process cannot be ignored. Therefore, it is necessary to secure a large margin in advance at the design stage, which is an obstacle to the speedup.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to generate a signal for activating an address comparator with a necessary and sufficient timing margin to reduce power consumption. It is an object of the present invention to provide a semiconductor integrated circuit capable of performing high-speed address comparison and a method for reducing power consumption of the semiconductor integrated circuit.

[0008]

To achieve the above object, in the first configuration of the semiconductor integrated circuit according to the present invention, the tag address stored in the tag cell array is compared with the block frame address, and these addresses are It has a comparator that outputs a hit signal when they match and a dummy cell that is formed at the same time as the tag cell array, and generates a signal as to whether or not the comparator is activated using the read data of the dummy cell. It is characterized by

The second aspect of the semiconductor integrated circuit according to the present invention
In the above configuration, a part of the requested address is input, and a row decoder that activates a predetermined word line by this input is connected to the row decoder by the word line, and a predetermined tag address is output by the activation. A tag cell array, a comparator for comparing a tag address output from the tag cell array with a block frame address, a dummy cell array formed simultaneously with the tag cell array and outputting data by activating a predetermined word line, A comparator activation signal generator for generating an activation signal of the comparator according to the timing of the output, and the comparator compares the tag address and the block frame address with the activation signal. It is characterized by determining whether or not.

To further achieve the above object, the method of reducing the power consumption of a semiconductor integrated circuit according to the present invention is characterized in that a tag address stored in a tag cell array is compared with a block frame address, and these addresses match. In a method of reducing the power consumption of a semiconductor integrated circuit by using a comparator that sometimes outputs a hit signal and interrupting the comparison performed by the comparator with an activation signal, a dummy cell formed simultaneously with the tag cell array is used. That is, the activation signal is generated according to the read data of the dummy cell, and the comparison of the comparator is interrupted by using the generated activation signal.

[0011]

In the present invention, when reading the tag address,
At the same time, the data of the dummy cell is read out. Since this dummy cell is formed at the same time as the formation of the tag cell array, it takes almost the same time as reading the tag address, and the power supply voltage dependency of that time and the dependency on process variations are also the same. Therefore, if the comparator activation signal is generated using the data read from the dummy cell, the timing margin can be saved even if there is a variation in the power supply voltage or a variation in the process. As a result, it is not necessary to take an excessive timing margin at the time of design, and it is possible to suppress a decrease in comparison speed caused by activating / deactivating the comparator.

[0012]

Embodiments of a semiconductor integrated circuit according to the present invention will be described with reference to the drawings. First, description will be made with reference to FIG.

This semiconductor integrated circuit has a CPU (not shown).
Input a part of the address (index frame address) requested by the row decoder 1 and activates a predetermined word line by this input, and the row decoder 1 and the word line 3 are connected to each other. A tag cell array 5 that outputs a tag address and a comparator 19 that compares the tag address output by the tag cell array 5 with a block frame address are provided. here,
The semiconductor integrated circuit according to the present invention further includes a dummy cell 13 connected to the same word line as the tag cell array 5. Therefore, when a predetermined word line is activated by the row decoder 1, the data stored in the dummy cell 13 can be output at the same time.

Since the dummy cell 13 is formed in the same process as the tag cell array 5, it has the same power supply voltage dependency, process dependency, and temperature dependency as the tag cell array 5. Further, in this embodiment, it is assumed that the data to be read is fixed so as to output a high potential (H) as shown in FIG.

Next, the operation of this semiconductor integrated circuit will be described. The row decoder 1 inputs a part of the address (index frame address) requested by a CPU (not shown) from the index input line 7, and searches the tag cell array 5 in which a predetermined tag address is stored. For this search, the corresponding word line 3 is activated by the row decoder 1, a predetermined tag address is read, and the sense amplifier 1
It outputs to the comparator 19 via 5.

The CPU inputs the tag address output from the tag cell array 5 and another part (block frame address) of the address requested by the CPU, and compares them. If they match as a result of the comparison, the data cache memory (not shown) is accessed. If they do not match, the cache is updated and the main memory is accessed.

On the other hand, when the tag cell array 5 searches for a tag address, the data in the dummy cell 13 is also read at the same time and input to the comparator activation signal generator 17. The comparator activation signal generator 17 generates a comparator activation signal by using the output timing of the dummy cell 13, and the comparator 1
Output to 9. The comparator 19 determines whether to perform the comparison operation based on the comparator activation signal. As a result, even if there is a difference in the input timing of the block frame address and the tag address, the comparator 19 does not operate, so that power consumption can be reduced.

As described above, when the comparator activation signal is generated from the data read from the dummy cell, the timing margin can be saved even if there are fluctuations in the power supply voltage or fluctuations in the process. As a result, it is not necessary to take an excessive timing margin at the time of design, and it is possible to suppress a decrease in comparison speed caused by activating / deactivating the comparator. This enables low power consumption and high-speed comparison.

Although the dummy cells are connected by the same word line in the above-described embodiment, in another embodiment, a word line which is always activated when each word line is activated is provided, and the word The dummy cell may be activated by a line and the output of the dummy cell may be used in the comparator activation circuit.

[0020]

As described above, according to the present invention,
Since the comparator activation signal is generated using the data of the dummy cell, it is possible to provide a semiconductor integrated circuit which has low power consumption and can perform high-speed comparison.

[Brief description of drawings]

FIG. 1 is a diagram showing a plan view of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a diagram showing an example of a dummy cell.

FIG. 3 is a block diagram used for explaining the operation of a general computer system.

FIG. 4 is a diagram showing a conventional semiconductor integrated circuit.

FIG. 5 is a diagram for explaining a timing chart of a conventional technique.

[Explanation of symbols]

 1 Row Decoder 3 Word Line 5 Tag Cell Array 7 Index Input Line 9 Tag Address Input Line 11 Block Address Input Line 13 Dummy Cell Array 15 Sense Amplifier 17 Comparator Activation Signal Generator 19 Comparator 21 CPU 23 Cache Memory 25 Main Memory 27 Tag Cache 29 Comparison unit 31 Data cache 33 Address bus 35 Data bus 37 Comparator activation signal generation circuit

Claims (3)

[Claims] 1. A comparator for comparing a tag address stored in a tag cell array with a block frame address and outputting a hit signal when these addresses match, and a dummy cell formed simultaneously with the tag cell array. A semiconductor integrated circuit having a signal for generating whether to activate the comparator using read data of the dummy cell. 2. A row decoder for inputting a part of a requested address and activating a predetermined word line by this input, and a row decoder connected to the row decoder by a word line, and activating a predetermined tag address by the activation. A tag cell array for outputting, a comparator for comparing a tag address output by the tag cell array with a block frame address, a dummy cell array formed simultaneously with the tag cell array and outputting data by activating a predetermined word line, A comparator activation signal generator that generates an activation signal for the comparator according to the output timing, the comparator comparing the tag address and the block frame address with the activation signal. A semiconductor integrated circuit characterized by determining whether or not. 3. A tag address stored in a tag cell array is compared with a block frame address, and a comparator that outputs a hit signal when these addresses match is used, and the comparison performed by this comparator is an activation signal. In the method for reducing the power consumption of a semiconductor integrated circuit by interrupting the semiconductor integrated circuit, a dummy cell formed at the same time as the tag cell array is provided, the activation signal is generated by the read data of the dummy cell, and the generated activation signal is generated. A method for reducing power consumption of a semiconductor integrated circuit, characterized in that the comparison of the comparator is interrupted by using an activation signal.