KR960001109B1 - Semiconductor memory device having dispersed row clock - Google Patents

Abstract

The semiconductor memory element having at least more than two memory blocks, at least more than two word line drivers, and at least more than two low decoders, comprises at least more than two master low clock generating circuits for providing a master low clock having the high voltage to the corresponding word line driver by being coupled with the more than two word line drivers, respectively and selectively driven by a low address for a block selection.

Description

Semiconductor memory device with distributed master clock generator

1 is a block diagram of a word line control circuit including a conventional master low clock generation circuit.

Figure 2a is a detailed view of a conventional master clock generator circuit.

2b is a signal waveform diagram of a conventional master clock generator.

3 is an overall structure diagram of a semiconductor memory device to which a conventional master clock generator is applied.

4 is a block diagram of a word line control circuit having distributedly arranged master low clock generation circuits in accordance with an embodiment of the present invention.

FIG. 5A is a detailed circuit diagram of the master row clock generation circuit shown in FIG.

FIG. 5B is an operation waveform diagram of the master row clock generation circuit shown in FIG. 5B.

6 is an overall structural diagram of a semiconductor memory device including the master row clock generation circuits distributed in accordance with an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

11,41: master low clock generation circuit 12,42: word line driver

13,43: Loo decoder 14,44: memory block

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dynamic Random Access Memory) device, which is a semiconductor memory device, and more particularly to a master block clock generator (Master Row Clock Generator) that outputs a high voltage to be supplied to a word line. The present invention relates to a semiconductor memory device having distributedly arranged master low-clock generation circuits capable of reducing the generation of noise by distributing the discretely arranged and selectively driving, thereby causing the master low-clock to be generated only in the selected memory block.

In general, in the DRAM device, after reading the cell data, the voltage level of the selected word line is set to Vcc + V _T (Vcc) in order to store the full-high data again in the cell. , V _T : the threshold voltage of the cell's pass transistor).

The conventional technique used in the above-mentioned master low-clock generation circuit as a whole is to increase the load by driving all the memory blocks as one, even though the DRAM element is divided into a plurality of memory blocks as the speed and high integration As a result, the semiconductor memory device consumes a very large current, generates a large noise, and also causes a problem of lowering an operation speed.

Therefore, in the present invention, a master row clock generation circuit is implemented in each memory block so as to be suitable for use in a DRAM device which is becoming faster and more integrated, so that a word line driven by one master row block generation circuit is limited to one memory block. In addition to improving drive capability, the solution is to reduce current consumption and prevent noise.

Hereinafter, with reference to the accompanying drawings will be described in detail the prior art and the present invention.

FIG. 1 is a block diagram showing a word line control circuit having one master row clock generation circuit 11. As shown, one master row clock generation circuit 11 includes several word line drivers. (12 to 1), not controlled by an address that selects a memory block, and all master low clock generation signals in the entire chip only by a low address strobe (RAS) pulse signal. (11) is operated to bootstrapping the master row clock ψX + above the level of the power supply voltage Vcc.

FIG. 2A is a detailed view of the conventional master low clock generation circuit 11, and the master low clock generation circuit 11 is generated by a low precharge control signal XPRE having a voltage level bootstrap in a standby state. Output signal ψX + maintains the level of the full-base voltage (-Vcc), and when the active state is active, the low precharge control signal XPRE is shifted to the level of the power supply voltage Vcc. At the same time, the low enable signal XE and the discharge-charge control signal XP controlled by the RAS pulse signal are enabled at a high level so that the output node N21 of the NAND gate G1 has a low level. Accordingly, the node N22 transitions from the low level of the standby state to the high level so that the voltage level of the master low clock ψX + is increased by the large size of the MOS transistor MC21 having a capacitor structure. Boots up to a level higher than Vcc + △ V Operate to be wrapped.

FIG. 2B is a waveform diagram showing an operation state of signals related to the master low clock generation circuit 11 shown in FIG. 2A, and as shown in FIG. 2B, FIG. 2B controlled by the RAS pulse signal (c) of FIG. It is understood that the bootstrapping section of the master row clock ψX + of FIG. 2b (d) is determined according to the operating time of the row enable signal XE and the discharge control signal XP of FIG.

FIG. 3 is a blur diagram showing the overall structure of the conventional master low clock generation circuit 11, in which the output signal? X + of the global master low clock generation circuit 11 is transmitted to each memory block 14; Entering the input of the existing word line driver 12, any word line driver 12 designated by four combinations of the row address AX01 receives four driver signals XA, XB, XC, and XD. To occur. The four driver signals XA, XB, XC, and XD generated by the word line driver 12 to which the master low-clock (ψX +) is transmitted pass through the low-decoder 13 to store the memory block 14 in the memory block 14. This will enable the selected word line.

In the case of a DRAM including one of the conventional master low clock generation circuits described with reference to FIGS. 1 to 3 above, as described above, since one master low clock generation circuit must drive several word line drivers, the degree of integration is high. In order to make a high speed and high speed semiconductor device, it is necessary to increase the size of the master low clock generation circuit or increase the number of the master low clock generation circuits. In this case, the peak current increases and the current consumption as well as the noise problem. Can grow.

Therefore, the present invention divides the master low clock generation circuit into each memory block and uses the low address to select the memory block as well as the signal controlled by the RAS pulse signal as a signal for controlling the master low clock generation circuit. When one memory block is selected, only the corresponding master low clock is strapped above the power supply voltage (Vcc) level, and the other master low clock is precharged and the power supply voltage (Vcc) level is maintained as it is. The purpose is to reduce the peak current and improve the noise problem.

Hereinafter, the master low clock generation circuit of the present invention will be described with reference to FIGS. 4 to 6.

4 is a block diagram showing a word line control circuit having dividedly arranged master low clock generation circuits 41 according to the present invention. If there are n memory blocks, FIG. In this case, the circuit is enabled by the boost signal BS outputted by the RAS pulse signal corresponding to each memory block and an address for selecting the memory block.

The master low clock ((X) + i / n) of the master low clock generating circuit 41 is transmitted to the word line after passing through the word line driver 42 and the low decoder 43 as described in FIG. Lose.

FIG. 5A is a detailed view showing an embodiment of the master low clock generation circuit 41 used in the present invention. The configuration and operation of the circuit are the same as those of the conventional master low clock generation circuit 11 described in FIG. However, instead of the XP signal controlled by the RAS signal, the booster signal BS that selects a memory block is connected to the input terminal of the NAND gate G2, and only a selected one of the n master low clocks is higher than the power supply voltage Vcc. Bootstrapping

FIG. 5B is a waveform diagram showing an operation state of signals related to the master low clock generation circuit 41 of the present invention shown in FIG. 5A, and the solid line is a signal waveform of the selected master low clock generation circuit in FIG. The master low clock ψX + i / n of d) is determined by the bootstrapping section by the low enable signal XE and the booster signal BS of FIGS. 5b and 5b. The dotted line is a waveform of the master low clock (? X + i / n) of the other unselected memory blocks, and always has a power supply voltage Vcc level.

FIG. 6 is a block diagram showing the overall structure of a semiconductor memory device having dividedly arranged master low clock generation circuits 41 according to the present invention, wherein the master low clock generating circuit 41 of each memory block exists. The output enters the input of the wordline driver 42 present in that memory block 44 and is passed to the row decoder 43 to enable the selected wordline.

The rest of the operation is the same as already described with reference to FIGS. 4 to 5b.

As shown in FIG. 4 to FIG. 6, the DRAM device having the divided master low clock generation circuit of the present invention enables the master low clock only in a selected memory block to reduce the peak current during operation. Therefore, the high-speed operation can be executed while being less affected by noise, resulting in a DRAM device having good characteristics.

Claims (1)

At least two memory blocks having a plurality of word lines, and at least two word lines respectively installed to correspond to the at least two memory blocks to generate a word line driving signal for driving word lines belonging to the memory block; The at least memory block to selectively enable a plurality of word lines in the memory block by applying an output of the word line driver to any word line in the memory block specified by a driver and a word line selection row address; A semiconductor memory device having at least two or more row decoders respectively provided between the at least two or more word line drivers, the semiconductor memory elements being distributedly arranged so as to be connected to the at least two or more word line drivers, respectively, and having a row address for block selection. By A semiconductor memory device having at least two master low clock generation circuits selectively driven to supply a master low clock having a high voltage level to a corresponding word line driver, respectively.