JPS58105618A - Latch device - Google Patents

Abstract

PURPOSE:To use the succeeding data generating period of other data transfer by making a latch circuit latch a signal having the same logical level as a precharged level. CONSTITUTION:A logical circuit 3 through a static latch circuit 2, a precharging circuit 4 and a logical circuit 6 controlling a buffer circuit 5 are connected to bus lines 11-14. When a signal having the same logical level 1 as a precharged level is written in latches 111-114 in the latch circuit 2, a latch signal phi'L synchronous with a precharged pulse phiPRE at that time and asynchronous in other cases is supplied from a latch signal supplying terminal 51. At that time, an inverted signal against the latch signal phi'L is supplied from a terminal 52 to the gates of data holding transistors 151-154. Consequently the succeeding data generating period can be used for other data transfer, using the data lines efficiently.

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a latch device suitable as a latch circuit for a digital integrated circuit.

Technical background of the invention and its problems In integrated circuits with complex circuit configurations, such as microprocessors, it is common practice to transfer data in a time-division manner via a common signal line. The common signal line mentioned above is called a data path. When receiving and receiving data from this data path, a dynamic latch circuit or a static latch circuit is used.In addition, a 3-state buffer is used to output data to the data path. However, a method is often used in which only one of the next higher level or lower level is output, and the other level is compensated for by precharging the pass line. ○ The following is a conventional example: The path line precharging method using the N-channel MO8-FE will be described. 8
Figure 1 shows an example of a conventional path/line drive circuit. ~1
4 is a pass line (data line) 12 is a static latch circuit, J is a logic circuit provided on the output side of this latch circuit 2, 4 is a precharge circuit, 5 is a pass line 1
．． 14 is a buffer circuit that determines data, and 6 is a logic circuit that controls this buffer circuit J. The latch circuit 2 has latches 1° to 11° corresponding to pass lines 1° to 14, respectively. Transistor 12I is for taking in data on pass line 11 in response to ratte signal φL. Inverter 13. .

14 is the part that becomes the main body of the ratte, and transistor 1
5. are inverters 13., which are at the same signal level. input and inverter 14. Connect the outputs of to form a static hold circuit. Transistor 15. Gate control is performed by an inverted pulse φL of the latch signal φL. Other lattes 112-11. Regarding the above latch 1
Since it is the same as , the corresponding shreds are given the same reference numerals and only the subscripts are different, and the explanation will be omitted. The precharge circuit 4 is connected to the power supply Vee and the path lines 11 to 1, and is connected to the following transistors 21° to 21+k and a precharge signal φ.
The 0 buffer circuit 5, which is controlled by Zoro, connects the ground line and the path 24711 to 1. The intermediate transistors 311 to 31 are controlled by the output of the logic circuit 6.

FIG. 2 shows an example of timing waveforms for the circuit shown in FIG. φ,
is a system clock signal, and the period from the rising edge of this clock φ1 to the next rising edge is one state, and data is exchanged via the path line in units of this one state. The precharge clock φpig, which has the same period as the clock φ, is connected to the pass line 1.
1 to 14 are precharged to H (high) level. After completion of the 0 precharge, the logic circuit 6 drives the buffer circuit 5t and outputs data to the pass line. At this time, the pass line outputs only L (low) level data. When the 0 data is at the H level, the buffer circuit 5 enters a high impedance state and the pass line maintains the precharge level. Data on this pass line is captured by latches 11°-1 to 4. The latch timing is pulse φL
The configuration shown in FIG. 1 is an example in which there are four pass lines, that is, the data is 4 bits, but each timing can be considered in exactly the same way in the case of 8 bits, 16 bits, etc.

In the case of the above conventional example, latte 11. When you want to write all 4 bits @1# to ~114, in that state, set the outputs of all buffer circuits that drive the pass lines to high impedance, and set the precharge level of pass lines II~14 to latch pulse φL. The data of all 0 and all 1 # that is written into the latch circuit is often input to a specific logic circuit when it is in a fixed state. For example, when you want to decrement data, you can add "1111" in binary code to that data.0 If the above data is subtraction timer data, it will be decremented periodically. Writing 11# to a bit requires time equivalent to one step, ft.

OBJECTS OF THE INVENTION The present invention has been made in view of the above circumstances, and its purpose is to make the use of pass lines more effective by changing the latch timing of the latch circuit.

SUMMARY OF THE INVENTION In order to achieve the above object, the timing of precharging the data line and the data latch going low to the latch circuit are made to match. By doing this, the following data is captured after all bits are "1". The data establishment period can be used for data transfer, and can also be used as the data of the data preacher i;/l''all the pits''l#.

Embodiment of the Invention An embodiment f of the present invention will be described below with reference to the drawings. FIG. 3 is a circuit configuration diagram showing the same embodiment;
Since this is an example in which the corresponding parts correspond to those shown in the figure, the corresponding parts are given the same reference numerals and the explanation will be omitted, and the characteristic points will be explained. When sending a signal of the same logic level as the precharge level to ~114, that is, when sending a signal 'm1''' to ~114,
~""When latching to 1#1, synchronize with precharge pulse φFRI, and at other times -PRE
A two-way signal φL' (see FIG. 4) which is not synchronized with the latch signal supply end 51 is supplied from the latch signal supply terminal 51, and at this time, the data hold transistor 15. An inverted signal ε' of the latch signal -L' is applied to the gates of terminals 5 to 154.
2. In the diagram 93, when you want to write "1" to all the outputs 11□ to 114, the latch signal φL' is output in synchronization with the precharge signal φP■, and in other cases, other logic circuits If data is to be received from or taken from, the latch pulse φL' may be outputted during a period other than the precharge period, as in the conventional case. In this way, all 11"
The next data establishment period (period A in FIG. 4) in which data is captured can be used for data transfer. On the other hand, conventionally, all “1
” data, this period could not be used for other data transfers, and the timing of the next state had to be waited for. Therefore, according to Figure 183, the pass line was used with an efficiency of L As a result, the speed of the entire system will be increased.

As described in detail, according to the present invention, the latch circuit is made to output the signal 'kj of the same logic level as the precharge level, so that the next data establishment period can be used for other data transfer, and the precharge In addition to the period, each data
It is also necessary to provide states for obtaining signals of the same logic level on the lines, which can further enable the use of the data lines.

[Brief explanation of drawings]

Fig. 1 is a circuit configuration diagram of a conventional device, Fig. 2 is a timing chart showing the operation of the same configuration, No. 35!5 is a circuit configuration diagram of an embodiment of the present invention, and Fig. 4 is an operation of the same configuration. CJj which is a timing chart shown ~14...Data line, 2...Latch circuit, 4...Precharge circuit, 5
...Buffer circuit, sl...Latch signal supply end.

Claims (1)

[Claims] A latch device consisting of a plurality of data lines and a latch circuit connected to each of these data lines, wherein the data lines are precharged with the same precharge signal, and the latch circuit latches data with the same latch signal. , means for outputting the latch signal within the precharge period when causing the latch circuit to latch a signal of the same logic level as the precharge level; otherwise outputting the latch signal outside the precharge period; A latch device comprising: