JPH04350742A - Picture data write method and picture memory device - Google Patents

Abstract

PURPOSE:To shorten the write time of all picture data. CONSTITUTION:n RAMs 1 to n, an m-bit data bus D, an nm-bit shift register S to which serial picture data SD is supplied, data bus selectors C1 to Cn which are arranged for RAMs 1 to n and selectively connect the data bus D or the parallel output terminal of m continuous bits of the shift register S to data terminals of RAMs 1 to n in accordance with a select control signal C, and a chip select circuit CS which simultaneously selects and activates plural RAMs out of RAMs 1 to n to set plural RAMs to the write state at the time of selecting the parallel output terminal of the shift register S by the select control signal C are provided.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image data writing method and an image memory device.

0002

2. Description of the Related Art In order to speed up assembly, inspection, etc. using an image processing device, it is necessary to perform image input processing and image processing on input images at high speed.

FIG. 7 is a block diagram of an image processing device to which a conventional image memory device 20 is applied.

For example, objects to be inspected or assembled are placed on a transport device, the objects are intermittently fed at a pitch between the objects, and the imaging device 10 is disposed above the transport device. When an object is imaged by the imaging device 10, the imaging device 10
A video signal and a synchronization signal are output from. After this video signal is supplied to the binarization circuit 12 and binarized, the S/
The signal is supplied to the P converter 14 and converted into, for example, 8-bit parallel data. Further, the synchronization signal is supplied to the transfer control circuit 16, and a write address, an S/P conversion timing signal, and a bus request signal BR1 are generated. This write address is incremented every time parallel data is output from the S/P converter 14. These parallel data and write address are supplied to the image memory device 20 via the bus B1, the bus selector 18, and the bus B0, and the data is written to the address of the image memory device 20.

A system processor 22 and an image processing circuit 24 are connected to the bus selector 18 via a bus B2 and a bus B3, respectively. One of them is selected and connected to bus B0. The image processing circuit 24 performs specific image processing on the image written in the image memory device 20 at high speed due to its hardware configuration. On the other hand, the system processor 22
It is equipped with an MPU, a program memory, a work memory, and an I/O port, and performs overall image processing and other processing other than the specific image processing using a software configuration.

The bus arbiter 26 includes an S/P converter 14
, the system processor 22 and the image processing circuit 24 respectively supply bus request signals BR1, BR2 and BR3. Upon receiving the bus request signal BR1, BR2, or BR3, the bus arbiter 26 supplies an acknowledge signal AK1, AK2, or AK3 to the S/P converter 14, system processor 22, or image processing circuit 24. Further, the imaging device 10 is supplied with an imaging command from the system processor 22, and in response, the imaging device 10
sends an acknowledge signal AK0 to the system processor 22 from
is supplied.

The image memory device 20 includes a chip select circuit 30, RAMs 31-34, 41-44, and a bus B0. This bus B0 includes a data bus and an address bus, and the upper three bits A of the address bus
13 to A15 are supplied to the bus beater 26, decoded, and one of the RAMs 31 to 34 and RAMs 41 to 44 is selected. Then, data from the S/P converter 14 is written to designated addresses A0 to A12 of the selected RAM, or the contents of these addresses are read and processed by the system processor 22 or the image processing circuit 24.

[0008]

[Problem to be solved by the invention] However, S/P
Every time, for example, 1 byte of data from the converter 14 is written to the RAM, bus B0 is selected, the address is updated, and the RA
Since it is necessary to select M and put it into the write state and write the data to the RAM, there is a problem that it takes a long time to write all the image data.

SUMMARY OF THE INVENTION In view of these problems, an object of the present invention is to provide an image data writing method and an image memory device that can shorten the total image data writing time.

0010

Means for Solving the Problems and Their Effects FIG. 1 is a block diagram showing the principle structure of an image memory device according to the present invention.

[0011] This image memory device includes RAMs 1 to n;
An m-bit data bus D, an nm-bit shift register S to which serial image data SD is supplied, and each set of R
It is arranged for AM1-n, and selectively connects either one of the consecutive m-bit parallel output terminals of the data bus D and the shift register S to the data terminals of RAM1-n according to the selection control signal C. Data bus selector C1-C
n, and a chip select circuit CS that simultaneously selects and activates a plurality of sets of RAMs and puts the plurality of RAMs into a write state when the selection control signal C selects the parallel output terminal of the shift register S. ing.

In the above configuration, the shift register S has n
When m-bit serial image data SD is held, 1
The contents of the nm bits of the shift register S are written to n sets of RAMs 1 to n at one or more times. Therefore, 1
The time required to write all image data is shorter than when writing to RAM for each address. In the image data writing method according to the present invention, image data is written into the image memory device in this manner. The image memory device to which this method is applied is
At least RAM1 to n and an m-bit data bus D
and a nm-bit shift register S to which serial image data SD is supplied.

Note that if the storage capacity of the image memory device is relatively large, by writing the contents of nm bits of the shift register S to the RAM in multiple steps, it is possible to prevent the current consumption from increasing at once. It is possible to reduce the amount of noise and prevent the occurrence of large noise.

Further, the image memory device may include a shift register S.
If the image data is binary data, there is no need to use an S/P converter to convert the binary data to parallel data, which also contributes to shortening the image data writing time. .

Next, an image memory device according to one embodiment of the present invention will be described with reference to the reference numerals of corresponding components in FIG.

This image memory device includes first to k groups of RAMs, each group consisting of n groups, for example, first group RAMs 31 to 34,
2nd group RAM41-44, 3rd group RAM51-54,
m-bit data bus D0 and serial image data SD
are supplied with nm bits each, for example, a first shift register S30, a second shift register S40, a third shift register S50, and each RAM3.
arranged for 1-34, 41-44, 51-54,
Depending on the selection control signals C3 to C5, one of the data bus D0 and the consecutive m-bit parallel output terminals of the shift registers S30, S40, and S50 is connected to the RAMs 31 to 34,
A data bus selector selectively connected to data terminals 41 to 44 and 51 to 54, for example, data bus selector C
31 to C34, C41 to C44, C51 to C54 and the selection control signal Ci (i=3 to 5) are in the shift register Si0.
When selecting the parallel output terminal of , a plurality of RAMs belonging to the i-2th group are simultaneously selected and activated;
It also includes a chip select circuit 30 that puts the plurality of RAMs into a write state.

In the above configuration, the shift register S30
, S40, and S50, and after nm-bit data is held in shift register Si0 (i=3 to 5), the contents of nm-bit of shift register Si0 are changed once or multiple times. RAMi1~i
4 is written.

According to this configuration, when the contents of the shift register are written to the RAM in a plurality of times, the serial image data SD is supplied to the other shift registers at the same time as the image data is written from the shift register to the RAM. Therefore, the above-mentioned effect of shortening the total image data writing time can be enhanced.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 2 is a block diagram of an image memory device according to an embodiment of the present invention. FIG. 3 is a block diagram of an image processing device to which the image memory device of FIG. 2 is applied. In FIG. 3, the same components as those in FIG. 7 are given the same reference numerals, and their explanations will be omitted.

In this image processing device, as shown in FIG.
Serial image data SD, which is the output of the binarization circuit 12, is directly supplied to the image memory device 20A. The transfer control circuit 16A also generates a write address and supplies it to the bus selector 18 via the address bus A1, and also generates first to third group selection control signals C3 to C5 and shift pulses S3 to S5, which will be described later. and supplies this to the image memory device 20A.

As shown in FIG. 2, the image memory device 20A includes a first group of RAMs 31 to 34 and a second group of RAMs 41 to 34.
44, and a third group of RAMs 51 to 54. Each of the RAMs 31 to 54 has the same configuration and consists of one or more chips.

Data bus selectors C31 to C54 are arranged for each RAM31 to 54, and the output terminals of the data bus selectors C31 to C54 are connected to the RAMs 31 to 5, respectively.
It is connected to the data terminal of 4. Also, the first group RA
A shift register S30 is arranged along the RAMs M31 to M34, and a shift register S30 is arranged along the RAMs 41 to 44 of the second group.
40 are arranged, and a shift register S50 is arranged along the third group of RAMs 51-54. Shift register Si0 (i=3 to 5) is divided into four m-bit shift registers Sij (j=1 to 4), and shift register S
The m-bit parallel output terminal of ij is the data bus selector C.
It is connected to one input terminal of ij. A data bus D0 is connected to the other input terminal of the data bus selector Cij. The i-2nd group selection control signal Ci is supplied to the selection control terminal of the data bus selector Cij. The data bus selector Cij connects either the data bus D0 of the bus B0 or the shift register Sij to the data terminal of the RAMij according to the i-2nd group selection control signal Ci.

Shift registers S30, S40 and S50
Serial image data SD is input to the serial data input terminal of
are supplied, and shift registers S30, S40 and S50
Shift pulses S3, S4, and S5 are supplied to the clock terminals of , respectively.

[0025] Lower 1 of address bus A0 of bus B0
2 bits A0 to A11 are commonly supplied to the address input terminals of RAM31 to 54, and upper 4 bits A12 to A1
5 is supplied to the chip select circuit 30. This chip select circuit 30 receives first to third group selection control signals C3 to
C5 is also supplied. The chip select circuit 30 generates chip select signals CS31 to C based on these input signals.
S54 is generated and supplied to the chip select input terminals of the RAMs 31-54.

FIG. 4 shows a partial configuration of the chip select circuit 30.
Shown below. Upper 4 bits A12 to A1 of address bus A0
5 is supplied to the decoder 301 and decoded, and among the outputs of the decoder 301, select signals Q31 to Q34 corresponding to the RAMs 31 to 34 are supplied to the OR gate 302, and the output of the OR gate 302 is input to one input terminal of the AND gate 303. supplied to Select signal Q31 is also supplied to one input terminal of AND gate 305. The other input terminal of the AND gate 303 is supplied with the first group selection control signal C3, and the other input terminal of the AND gate 305 is supplied with the first group selection control signal C3 via the inverter 304. The outputs of AND gates 303 and 305 are supplied to OR gate 306, and a chip select signal CS31 for selecting RAM 31 is taken out from OR gate 306.

When the first group selection control signal C3 and the select signal Q31 become high level, the chip select signal C3 becomes high level.
S31 becomes a high level, and chip select signals CS32 to CS34 also become a high level, and the RAM 31
-34 are selected at the same time. When the first group selection control signal C3 is at a low level, only the chip select signal CS31 is at a high level when the select signal Q31 is at a high level, and similarly, when the select signal Q3j (j = 2 to 4) is at a high level, At this time, only the chip select signal CS3j becomes high level. The same applies to the selection of RAMs 41 to 54.

Next, the operation of the image memory device configured as described above will be explained with reference to FIG.

In the initial part shown in FIG. 5, FIG.
As shown in D) and (F), the first to third group selection control signals C
3 to C5 are all at low level, and RAM31 to 5
A data bus D0 is connected to the data terminal No.4. Further, the bus request signal BR1 is at a low level as shown in FIG. 5(G). On the other hand, the bus request signals BR2 and BR3 change as shown in FIGS. 5(H) and (I), for example. Bus selection priority is bus B1, B2,
B3, and the bus beater 26 is in the order shown in FIGS. 5(J) to (
As shown in L), first, bus B2 is selected.

In this state, the system processor 22 processes the image data written in the RAMs 31-54. In parallel with this image processing, a shift pulse S3 is supplied to the clock terminal of the shift register S30,
The shift register S30 enters the operating state as shown in FIG. 5(A), and the serial image data S is stored in the shift register S30.
D is retained and shifted. At this time, shift pulse S
4 and S5 are stopped.

When the shift operation is repeated 4m times, the shift pulse S3 stops, the bus request signal BR1 becomes high level as shown in FIG. 5(G), and the bus B1 is selected as shown in FIG. 5(J). As shown in FIG. 5(B), the first group selection control signal C3 becomes high level, and the shift register S
30 parallel output terminals are connected to data terminals of RAMs 31-34, and the entire contents of shift register S30 are written to RAMs 31-34. In parallel with this write operation, a shift pulse S4 is supplied to the shift register S40, and the same processing as described above is performed.

When the bus request signal BR2 becomes low level as shown in FIG. 5(H), the bus B3 is selected as shown in FIG. 5(L), and the image processing circuit Image processing by 24 is performed.

In the same manner as above, next shift register S4
The contents of 0 are written to RAM41-44, then the contents of shift register S50 are written to RAM51-54, then the contents of shift register S30 are written to RAM31-34, and the same process is performed. be exposed.

In this embodiment, the input image data is transferred to the shift register S4i (i=1 to 4) of the image memory device 20A, and the image data is written to RAMi1 to i4 in batches in bit length units of the shift register S4i. Therefore, the total image data writing time is shortened, and that time can be used for image processing, and the total processing time of the image processing apparatus is shortened.

Furthermore, since the image memory device 20 includes shift registers S30, S40, and S50, there is no need to use the S/P converter 14 shown in FIG. 7, which also contributes to shortening the image input time. ing.

Next, the case where one pixel data is multivalued will be explained. FIG. 6 is a block diagram of another image processing device to which the image memory device 20A of FIG. 2 is applied. In this image processing device, the video signal output from the imaging device 10 is
After being supplied to the D converter 28 and digitized, it is supplied to the P/S converter 29 and converted into serial image data SD, which is then supplied to the image memory device 20A. Other points are the same as in FIG.

[0037]

As explained above, in the image data writing method and image memory device according to the present invention, when serial image data is held in all bits of the shift register, 1
Since the entire contents of the shift register are written to the RAM once or multiple times, the time required to write all image data is reduced compared to when writing to the RAM for each address. This greatly contributes to speeding up inspection and assembly processing.

Furthermore, since the image memory device is equipped with a shift register, when the image data is binary data,
There is no need to convert binary data into parallel data using an S/P converter, and the aforementioned effect of shortening the image data writing time is enhanced.

According to the first aspect of the present invention, when writing the contents of the shift register to the RAM in multiple batches, at the same time as writing the image data from the shift register to the RAM, serial images are written to other shift registers. Since the data can be supplied, the above-mentioned effect of shortening the total image data writing time is enhanced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention.

FIG. 2 is a block diagram of an image memory device according to an embodiment of the present invention.

FIG. 3 is a block diagram of an image processing device to which the image memory device of FIG. 2 is applied.

FIG. 4 is a partial configuration diagram of the chip select circuit of FIG. 2;

FIG. 5 is a time chart showing the operation of the circuits in FIGS. 2 and 3;

FIG. 6 is a block diagram of another image processing device to which the image memory device of FIG. 2 is applied.

FIG. 7 is a block diagram of an image processing device to which a conventional image memory device 20 is applied.

[Explanation of symbols]

30 Chip select circuit 31-54 RAM S30, S40, S50 Shift register C31-C
54 Data bus selector SD Serial image data C3 to C5 selection control signal

Claims (3)

[Claims] 1. An image memory comprising n sets of RAMs (1 to n), an m-bit data bus (D), and an nm-bit shift register (S) to which serial image data (SD) is supplied. An image memory device characterized in that, after holding nm-bit data in the shift register, the nm-bit contents of the shift register are written into n sets of the RAMs one or more times. 2. n sets of RAMs (1 to n), an m-bit data bus (D), an nm-bit shift register (S) to which serial image data (SD) is supplied, and a corresponding one of each set. Data that is arranged for the RAM and selectively connects either the data bus or the consecutive m-bit parallel output terminals of the shift register to the data terminal of the RAM according to a selection control signal (C). Bus selector (C1~
Cn), and when the selection control signal selects the parallel output terminals of the shift register, a plurality of sets of the RAM
a chip select circuit (CS
), and after the nm-bit data is held in the shift register, the nm-bit contents of the shift register are written to n sets of the RAMs once or multiple times. Image memory device. 3. First to k group RAM, each group consisting of n groups.
(31-34, 41-44, 51-54), m-bit data bus (D0), and serial image data (SD)
are supplied to the first to k shift registers (S30, S40, S50) each having nm bits, and are arranged for each set of the RAM, according to selection control signals (C3 to C5).
a data bus selector (C31 to C3) that selectively connects either the data bus or the continuous m-bit parallel output terminals of the shift register to the data terminal of the RAM;
4, C41 to C44, C51 to C54), and when the selection control signal selects the parallel output terminal of the i-th shift register (i=1-k), the plurality of sets of RAMs belonging to the i-th group are selected. select at the same time to activate the RAM,
It has a chip select circuit (30) that puts the plurality of sets of the RAM into a write state, and the serial image data is sequentially supplied to the first to k shift registers, and the i-th shift register (i=1 to k ), n of the i-th shift register is held once or multiple times.
An image memory device characterized in that the contents of m bits are written into the i-th group RAM.