JPH0579800U - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] When memory is accessed, t _ON ,
A semiconductor memory device capable of switching t _OFF is obtained. [Structure] The SOT generation circuit that determines the SC access is t
Provide a terminal X that can input the _ON / t _OFF switching signal X.

Description

[Detailed description of the device]

[0001]

[Industrial applications]

 The present invention relates to a semiconductor memory device, and particularly to its access.

[0002]

[Prior Art]

 FIG. 4 is a block diagram showing the overall configuration of a conventional video random access memory (hereinafter abbreviated as VRAM). In the figure, 1 is a memory array arranged in rows and columns, 2 is an address terminal for receiving an address signal, the address signal received by the address terminal 2 is converted into an internal signal 3 by an address buffer 10, and this signal 3 is received. The digit row decoder 8 selects a row in the memory cell array 1, and the column decoder 9 selects a column. 8 is a row decoder, 9 is a column decoder, 10 is an address buffer, 11 is a clock generator, 12 and 13 are RAM I / Os, and 14 is a random access memory 1 having a number of cells equal to the number of memory cells in the column direction. The serial register, the memory cell array 1 and the serial register 14 can transfer information on an arbitrary row, and the transfer means 15 is used for the transfer. Reference numeral 16 is a serial register, and 17 is a clock terminal for receiving a shift operation signal. The shift operation signal is received and converted into an internal signal by the SC buffer 19, which is sent to the internal signal serial selector 16 and the 1 in the serial register 14 is sent. By selecting cells and shifting them one by one, a series of shift operations enable memory read and write. At the time of this reading and writing, it is performed at the terminal 18, and corresponding to it is the serial I / O 20 and the data signal 21 at the time of serial operation. The signal received from the clock terminal 7 causes the clock generator 11 to generate an internal clock, and sends to the transfer means 15 an instruction as to whether or not to transfer. FIG. 5 shows an SOT generation circuit. Data is output from the read data latch 22 of FIG. 7 to the output latch 23 by the SOT signal of this SOT generation circuit.

Next, the operation will be described. FIG. 6 shows the operation timing of the SOT generation circuit of FIG. First, SC1 rises after a delay of Delay 24 hours from the rise of the serial clock SC. This causes one shot of SOT. Delay 25 determines the pulse width of this SOT. The NAND26 has a function of applying Delay24 from SC clock to generation of SC1 and not applying Delay24 from reset of SC clock to reset of SC1. By one shot of this SOT, data is sent from the read data latch 22 of FIG. 7 to the output latch 23 and output to the outside. In this way, the access time from the serial clock SC is determined by Delay 24 in FIG. The system side of FIG. 8 takes in the data thus output to the system at a timing such as A or B.

[0004]

[Problems to be solved by the device]

 Since the conventional semiconductor memory device is configured as described above, the access time must be defined as one, and the data hold time t for the system of FIG. _OFF Access time t for system B_ONThere is a problem in that the delay of the SOT generation circuit must use two types of devices with different times in order to meet the demand for both systems A and B. It was

The present invention has been made to solve the above problems, and to obtain a semiconductor memory device capable of supporting a system in which the requirements of t _ON and t _OFF are completely opposite to each other with one type of device. With the goal.

[0006]

[Means for Solving the Problems]

The invention semiconductor memory device according to the is used to input different t _ON by the system, t _ON with respect to requests t _OFF, the switching signal for controlling from outside the t _OFF.

[0007]

[Action]

In the semiconductor memory device according to the present invention, t _ON and t _OFF are controlled by a setting signal from the outside, and switching between fast and slow access is performed.

[0008]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a block diagram showing the overall configuration of a semiconductor memory device according to a first embodiment of the present invention. 1 is the same as FIG. 4 showing the conventional configuration except that the SC buffer 19 is provided with a terminal X, the description thereof will be omitted. FIG. 2 is a circuit diagram of an SOT generating circuit according to the first embodiment of the present invention. In the figure, X is a terminal for inputting t _ON and t _OFF switching signals and signals, 101 is a NAND circuit for determining whether or not to apply Delay 124 in response to the switching signal X, and the switching signal X is directly applied to the bonding pad. Connect, that is, newly provide t _ON and t _OFF switching pins. SC, SC1, and Delay25 in FIG. 2 are the same as the conventional one in FIG. 5, respectively. Further, the transition from the read data latch to the output data latch by SOT is the same as the conventional one.

Next, the operation will be described. FIG. 3 is a timing diagram of the SOT generation circuit of FIG. Now, the L level is input to the terminal X from the newly provided pin. Receiving this L level signal, NAND101 outputs H level and is input to NAND126. Therefore, the NAND 126 becomes an inverter for the SC clock. In this case, when the SC clock is input, the SCI is generated regardless of the Delay 124. FIG. 3 shows switching between the X, SC, SC1 and SOT signals and the output data Sout. In FIG. 3, the broken line portions of SC1, SOT, Sout correspond to the case where the switching signal X of t _ON , t _OFF is at L level, and the generation of SOT with respect to the SC clock becomes faster, that is, Delay 124 is ignored. It As a result, the switching of the output data Sout becomes faster.

Next, the H level is input to the terminal X as the switching signal X. Receiving this H level signal, NAND101 becomes an inverter for the other input and waits for the other input. Now, when the SC clock is input, the output passing through Delay124 is input to NAND101, while the output of NAND101 Is inverted and input to NAND126, which causes SC1 to rise. In FIG. 3, the case where the solid line part of X, SC1, SOT, Sout is the above, that is, the case where the switching signal X of t _ON , t _OFF is at the H level, and the generation of SOT with respect to the SC clock is delayed. That is, it takes Delay124 to generate SOT from the SC clock. Eventually, switching of output data is delayed.

Example 2. In the first embodiment, the t _ON / t _OFF switching signal X is connected to the bonding pad, and t _ON / t _OFF is controlled by the external pin newly provided. It is also possible to use mode setting by a key or the like, or a signal sent by sensing a voltage.

Example 3. In the first embodiment, the case of the VRAM has been described, but SE inversion access, address access (static column), and OE inversion access may be used.

[0013]

[Effect of the device]

As described above, according to the present invention, the access to the semiconductor memory device can be controlled from the outside, so that the same chip can meet different system requirements of t _ON and t _OFF .

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an SOT generation circuit according to a first embodiment of the present invention.

FIG. 3 is a timing diagram of SOT generation according to the first embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional semiconductor memory device.

FIG. 5 is a circuit diagram of a conventional SOT generation circuit.

FIG. 6 is a timing diagram of SOT generation used in the related art and the embodiment of the present invention.

FIG. 7 is a SOT transmission circuit diagram of serial read data used in the related art and the embodiment of the present invention.

FIG. 8: SC access and 2 of the conventional and the embodiment of the present invention
FIG. 7 is a diagram showing types of system latches.

[Explanation of symbols]

1 memory array 14 serial register 17 serial clock 18 serial input / output pin 22 read data latch 23 output data latch X t _ON , t _OFF switching signal

Claims (2)

[Scope of utility model registration request] 1. A memory array configured in a matrix direction,
An address terminal for receiving an address signal, a means for selecting an arbitrary cell in the memory cell array by a signal input from the address terminal, a data input terminal for inputting write data to a selected cell, and a read operation from the cell In a semiconductor memory device having an output terminal of, a terminal information, a writing / reading means for connecting to a selected cell, and a clock terminal, t _ON and t _OFF can be controlled from the outside. Semiconductor memory device. 2. A random access memory, a second memory having a number of cells equal to the number of memory cells in the column direction in the memory array, and the first memory and the second memory transferring information about arbitrary rows. Means, an external clock terminal for receiving this transfer signal, and 1 in the second memory.
In a semiconductor memory device having a clock terminal for selecting cells and shifting them one by one and receiving a series of shift operation signals, and a terminal for reading data write data, t _ON and t _OFF can be controlled from the outside. A semiconductor memory device characterized by the above.