JPH04153978A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To update one part of background data to foreground data by performing logic calculation between serial input data and the output data from a register for serial output and inputting the output data to a register for serial input. CONSTITUTION:A selection word line 2 for access of a RAM part 1 is activated, and one line of data is batch-transferred to a register 4 for serial output from a RAM part 1, and a ROP code corresponding to the kind of required logic calculation is written in a register 9 for ROP code. The logic calculation of data serially inputted from a serial input terminal 5 and the output data from the register 4 for serial output is performed according to the ROP code to be outputted from the register 9 for ROP code, and the calculation result is written in a serial input register 3. After that, a selection word line 2 to be transferred by the RAM part 1 is activated, and the batch transfer of one line of data is performed from the register 3 for serial input to the RAM part 1. Thus, one part of the background data is updated to the foreground data.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device equipped with a serial input/output register.

2. Description of the Related Art A conventional semiconductor memory device (hereinafter referred to as a memory) will be described below with reference to the drawings.

FIG. 2 is a block diagram showing the internal configuration of a conventional memory. In Figure 2, l is the random access memory (RAM') section of the memory, and 2 is the selection word line selected when transferring one row of data between logic 1 and the serial input/output register. be.

3 is a serial input register, and 4 is a serial output register.

Next, data access in this memory will be explained. Random access to the RAIII unit 1 involves inputting and outputting data from random input/output terminals.

For serial input access, data serially input from the serial input terminal 5 is stored in the serial input register 3, and then the selected word @2 to be transferred in the RAM section 1 is activated, and one row of data is stored for serial input. register 3
The data is transferred all at once to the RAM section 1. When performing serial output access, first activate the selection word @2 of the row to be output with logic 1, transfer one row of data from logic 1 to the serial output register 4, and then transfer the data to the serial output terminal 6. Serially output data from a.

Problems to be Solved by the Invention In such a conventional memory, when serial input access is performed, one line of data (hereinafter referred to as background data) written in the RAM section 1 is all serial input data ( (hereinafter referred to as foreground data), it is not possible to update only part of a row or to write the results of logical operations on background data and foreground data to the logic section 1.

The present invention is intended to solve the above-mentioned problem, and aims to provide a semiconductor memory device in which a part of a row of background data can be changed with foreground data, and can be processed and written into the discussion section. be.

Means for Solving the Problems A semiconductor memory device of the present invention is provided with a logic operation circuit that performs a logic operation on serial input data input from the outside and output data from a serial output register, and outputs from the logic operation circuit. It is configured so that data is input to a serial input register.

Effects According to the above configuration, by preparing control data for each column data to determine the type of logical operation, it is possible to update part of the background data to foreground data, or perform #I calculation between background data and #quantity data. Processing result'f! Example: An example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the internal structure of a memory of a semiconductor memory device according to an embodiment of the present invention. In the first building 1.
l is memory random access memo! j (RAM)
81S, 2 is the selected word line selected when transferring one line of data between the RAM section and the serial input/output register, 3 is the serial input register, 4 is the serial 6
It is the same as the conventional example shown in FIG. 2. 8
is a logic operation circuit connected to the serial input adder,
A logical operation is performed between the serial input data inputted from the outside and the output data from the serial output register 4, and the data of 7 is inputted to the serial input register. Reference numeral 9 denotes a logic operation circuit 80, which is a ROP code register for preparing control data (hereinafter referred to as ROP code) for determining the type of logic operation for each column data.

The type of logical operation for each column data is selected according to the ROP code of the corresponding column.

Data access in this memory will be explained. RAMii! Random access to 1 inputs and outputs data from the random input/output terminal. For serial input access that does not use logic operations similar to the conventional example, data serially input from the serial input terminal 5 is stored in the real input register 3, and then the selected word line 2 to be transferred in the RAM section 1 is activated. , one row of data is transferred in batch from the serial input register 3 to the logic section l. When performing serial output access, activate the selected word line 2 of the row to be output in the RAM section 1, transfer one row of data from logic 1 to the serial output register at once, and then transfer the data from the serial output terminal 6. output serially.

Next, serial input access using logical operations will be explained. First, the selected word of the row to be accessed in RAM section 1 @
2 and register 9 for data tW code for one line.
Write it in.

As a method of writing the ROP code to the ROP code register 9, there are two methods: serially taking in the ROP code data from the serial input terminal 52), and
There is a method in which the ROP code data for 21 lines is written in the ROP code register 9 and then fetched into the ROP code register 9 at once by data transfer.

Then, the data serially input from the serial input terminal 5 and the output data from the serial output register 4 and '
i. Perform a logical operation according to the ROP code output from the ROP code register 9, and write the result of the operation to the serial input register 3. After 7, activate the selected word line 2 to be transferred in the RAM section l, and write the 1st row. The data for the serial input register 3 is transferred all at once to the logic l.

An example of a logical operation is shown in Figure 3.The logical operation in Figure 3 performs the same logical operation on the entire register) and i("'
In Figure 3, REG I 5TER is the serial input register, 5source is the external input serial data,
1, 1, and 1 nation indicate the data of the serial output register, and S and D stand for 5source and Des&1naLion, respectively. Also, Xo(
(exclusive or), Xnor (exclusive or
The types of logical operations such as 5' Benoit) and the figures of the operation results are shown.

- Effects of the Invention As described above, according to the present invention, a logic operation circuit is provided that performs a logic operation on serial input data input from the outside and output data from a serial output register, and the output from the logic operation circuit is By configuring the data input to enter the serial input register, a screen that updates part of the background data to foreground data,
The logical computation processing results of background data and foreground data can be written into the RAM section.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the internal configuration of a semiconductor storage device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the internal configuration of a conventional semiconductor storage device, and FIG. 3 is a diagram showing an example of logical operations. It is. 1... Random access memory section of memory, 2...
Selected word line, 3...Serial input register, 4.
...Serial output register, 8...Logic operation circuit,
9...Register for ROP code and code. Yoshihiro Morimoto Diagram Figure 3 REQtsTE* 7) - carving 4 negative la moxibustion ear control elephant (mats) C-D

Claims (1)

[Claims] 1) A random access memory to which a serial input register and a serial output register are added, comprising a logical operation circuit that performs a logical operation on serial input data input from the outside and output data from the serial output register, and A semiconductor memory device configured so that output data from a logical operation circuit is input to a serial input register.