JPH0895853A - Sequential fast access system using plural banks of slow operation memory - Google Patents

Abstract

PURPOSE: To provide a product which is inexpensive and can be mass-produced. CONSTITUTION: The device which needs to perform memory access to plural address areas sequentially plural times in a certain time uses plural banks of the low-speed operation memory M1 and supplies addresses to the memory banks MB1, MB2... sequentially at a high speed, latches the addresses corresponding to the memory banks MB1, MB2... in respective latch circuits RC1, RC2... nearby the low-speed operation memory M1 and secure an address supply holding time required for this low-speed operation memory M1, and takes output data out of the respective memory banks MB1, MB2... in order at a high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an apparatus for accessing a plurality of memory addresses a plurality of times within a fixed time.
The present invention relates to a high-speed access method that realizes an operation equivalent to a plurality of accesses when an expensive high-speed operation memory is used by securing an address holding time required for an inexpensive low-speed operation memory.

[0002]

2. Description of the Related Art FIG. 5 is an explanatory diagram of an example of a conventional system, and FIG. 6 is an explanatory diagram of its access operation. This conventional method is
As shown in FIG. 1, the high-speed memory access operation circuit C uses the high-speed operation memory Mh. As shown in FIG. 6, the high-speed memory access operation circuit C includes a plurality of memory addresses, for example, six memory addresses, 1 , 2, 3, 4,
5 and 6 are sequentially given, and the data is taken out from the high speed operation memory Mh.

[0003]

However, in the above-mentioned conventional method, since the high-speed operation memory Mh is expensive, it is not suitable for mass-produced products, and it is difficult to obtain it as compared with the low-speed operation memory. There are challenges.

[0004]

SUMMARY OF THE INVENTION The present invention solves the problem of the prior art, which is a rise in product cost when a high-speed operation memory is used, and makes it easy to obtain a plurality of memories that are overwhelmingly inexpensive. It is an object of the present invention to provide a sequential high-speed access method using a plurality of banks of low-speed operation memories, which can realize a memory access operation equivalent to that when an expensive high-speed operation memory is used by using banks.
That is, according to the method of the present invention, in a device that requires memory access to a plurality of address areas a number of times in succession within a fixed time, each memory bank MB1, MB2, ... To the latch circuits LC1, LC2 ... In the vicinity of the low speed operation memory M1, the addresses corresponding to the memory banks MB1, MB2 ... The memory M1 is secured with a necessary address supply holding time, and each memory bank MB1, MB2 ...
It is characterized in that the output data is sequentially extracted at high speed.

[0005]

[Operation] With the above-mentioned configuration, the corresponding addresses are sequentially supplied at high speed to the memory banks MB1, MB2 ... Of the low-speed operation memory Ml, and the memory banks MB1, MB2. The addresses are supplied to and latched by the respective latch circuits LC1, LC2 ... Corresponding to.
The addresses latched by the memory banks MB1, MB2, ... Are supplied to the memory banks MB1, MB2 ,.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the method of the present invention will be described below with reference to the drawings. FIG. 1 is a structural explanatory view of a first embodiment of the system of the present invention,
FIG. 2 is an explanatory diagram of the access operation. First, the configuration of the first embodiment will be described. In FIG. 1, C is a high-speed memory access operation circuit, and Ml is a low-speed operation memory, which is used in a plurality of banks, for example, two banks. In the vicinity of the two banks of low-speed operation memory M1, each memory bank MB1,
Latch circuit R corresponding to MB2 for latching an address
C1 and RC2 are provided. These latch circuits RC1 and RC
2 serves to secure the address supply holding time required for the low-speed operation memory Ml. C1 and C2 are memory side and latch side input / output control circuits corresponding to the access time of the low-speed operation memory Ml, respectively. The memory side input / output control circuit C1 supplies the addresses from the high speed memory access operation circuit C to the respective memory banks MB1 and MB2 in sequence and the data from the respective memory banks MB1 and MB2 in order to the high speed memory access operation circuit. It plays the role of inputting to C at high speed.

Next, the operation of the first embodiment will be described. From the high-speed memory access operation circuit C, memory addresses 1 to 6 are sequentially input to the memory banks MB1 and MB2 of the low-speed operation memory Ml via the memory side input / output control circuit CL as in the high-speed operation memory access. On the other hand, from the high-speed memory access operation circuit C, the memory addresses 1 to 6 are sequentially passed through the latch side input / output control circuit C2 and the respective latch circuits RC.
1 and RC2 are input and latched. That is, the addresses input to the memory banks MB1 and MB2 are held by the latch elements of the latch circuits RC1 and RC2, and the addresses are continuously supplied for the holding time _Tr required for the low-speed operation memory Ml. Addresses 1, 3, given to each memory bank MB1, MB2 of the low-speed operation memory Ml
The data 5 and the data 2, 4 and 6 can be read or written. At the time of data reading, the data reading control signal from the high-speed memory access operation circuit C sequentially controls the data in the memory banks MB1 and MB2 to be in an output state, and controls so that the data from the memory banks MB1 and MB2 do not collide with each other. While being processed, it is taken into the high-speed memory access operation circuit C. Further, at the time of writing data, the data writing control signal from the high-speed memory access operation circuit C sequentially controls the data writing to each memory bank MB1 and MB2, and in synchronization with this, high-speed writing to each memory bank MB1 and MB2. The data is supplied to and written from the high speed memory access operation circuit C.

FIG. 3 is an explanatory diagram of the configuration of the second embodiment, and FIG. 4 is an explanatory diagram of its access operation. The second embodiment has the same structure and operation as the first embodiment except that two banks of low-speed operation memory Ml are used and three corresponding latch circuits RC1 to RC3 are used. In the case of the first embodiment, the address holding time _Tr of each memory bank MB1 and MB2 is a time for two addresses, but in the case of the second embodiment, the address holding time of each memory bank MB1 to MB3. The case where T _r is the time for three addresses is illustrated.

Memory in the case of the conventional example using the high-speed operation memory Mh (FIG. 5) and in the case of the first embodiment (FIG. 1) in which the same access as that of the conventional example is made possible by using the low-speed operation memory Ml. Table 1 shows a comparative example of costs.

[Table 1] As is clear from this comparative example, in the case of the present invention, the cost can be significantly reduced as compared with the conventional case. It is needless to say that if a high-speed operation memory is used and a configuration like this method is used, higher-speed access becomes possible.

[0010]

As described above, according to the present invention, a plurality of low-speed operation memories are used to enable high-speed access equivalent to that of the conventional method. It is possible to provide an inexpensive product that can be mass-produced.

[Brief description of drawings]

FIG. 1 is a structural explanatory view of a first embodiment of the system of the present invention.

FIG. 2 is a diagram for explaining the access operation.

FIG. 3 is a structural explanatory view of a second embodiment.

FIG. 4 is a diagram for explaining the access operation.

FIG. 5 is a diagram illustrating the configuration of an example of a conventional method.

FIG. 6 is a diagram for explaining the access operation.

[Explanation of symbols]

 C High-speed memory access operation circuit Ml Low-speed operation memory MB1 memory bank MB2 memory bank MB3 memory bank RC1 latch circuit RC2 latch circuit RC3 latch circuit C1 memory side input / output control circuit C2 latch side input / output control circuit

Claims (1)

[Claims] 1. A device which requires memory access to a plurality of address areas a number of times sequentially within a fixed time,
Addresses are sequentially supplied to each memory bank at high speed using multiple banks of low-speed operation memory, and the address corresponding to each memory bank is latched by each latch circuit in the vicinity of the low-speed operation memory. Sequential high-speed access method using multiple banks of low-speed operation memory, which secures the necessary address supply and hold time for output data from each memory bank at high speed.