JPH041440B2 - - Google Patents
Info
- Publication number
- JPH041440B2 JPH041440B2 JP62154532A JP15453287A JPH041440B2 JP H041440 B2 JPH041440 B2 JP H041440B2 JP 62154532 A JP62154532 A JP 62154532A JP 15453287 A JP15453287 A JP 15453287A JP H041440 B2 JPH041440 B2 JP H041440B2
- Authority
- JP
- Japan
- Prior art keywords
- inverter circuit
- output
- level
- circuit
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 description 4
- 230000006378 damage Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000011156 evaluation Methods 0.000 description 4
- 238000012360 testing method Methods 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/19—Monitoring patterns of pulse trains
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/096—Synchronous circuits, i.e. using clock signals
- H03K19/0963—Synchronous circuits, i.e. using clock signals using transistors of complementary type
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- Logic Circuits (AREA)
- Power Sources (AREA)
- Shift Register Type Memory (AREA)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62154532A JPS641200A (en) | 1987-06-23 | 1987-06-23 | Semiconductor integrated circuit |
US07/208,441 US4920282A (en) | 1987-06-23 | 1988-06-20 | Dynamic latch circuit for preventing short-circuit current from flowing during absence of clock pulses when under test |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62154532A JPS641200A (en) | 1987-06-23 | 1987-06-23 | Semiconductor integrated circuit |
Publications (3)
Publication Number | Publication Date |
---|---|
JPH011200A JPH011200A (ja) | 1989-01-05 |
JPS641200A JPS641200A (en) | 1989-01-05 |
JPH041440B2 true JPH041440B2 (US20030199744A1-20031023-C00003.png) | 1992-01-13 |
Family
ID=15586317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62154532A Granted JPS641200A (en) | 1987-06-23 | 1987-06-23 | Semiconductor integrated circuit |
Country Status (2)
Country | Link |
---|---|
US (1) | US4920282A (US20030199744A1-20031023-C00003.png) |
JP (1) | JPS641200A (US20030199744A1-20031023-C00003.png) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5208489A (en) * | 1986-09-03 | 1993-05-04 | Texas Instruments Incorporated | Multiple compound domino logic circuit |
JP2583521B2 (ja) * | 1987-08-28 | 1997-02-19 | 株式会社東芝 | 半導体集積回路 |
EP0417130A4 (en) * | 1988-05-06 | 1992-02-26 | Magellan Corporation (Australia) Pty. Ltd. | Low-power clocking circuits |
JPH02132917A (ja) * | 1988-11-14 | 1990-05-22 | Toshiba Corp | バスドライバー集積回路 |
US4988896A (en) * | 1989-07-31 | 1991-01-29 | International Business Machines Corporation | High speed CMOS latch without pass-gates |
US5081377A (en) * | 1990-09-21 | 1992-01-14 | At&T Bell Laboratories | Latch circuit with reduced metastability |
US7388400B2 (en) * | 1993-01-07 | 2008-06-17 | Elpida Memory, Inc. | Semiconductor integrated circuits with power reduction mechanism |
US6384623B1 (en) * | 1993-01-07 | 2002-05-07 | Hitachi, Ltd. | Semiconductor integrated circuits with power reduction mechanism |
DE4321315C1 (de) * | 1993-06-26 | 1995-01-05 | Itt Ind Gmbh Deutsche | Takterzeugungsschaltung für taktgesteuerte Logikschaltungen |
US5572150A (en) * | 1995-04-10 | 1996-11-05 | International Business Machines Corporation | Low power pre-discharged ratio logic |
KR100303073B1 (ko) * | 1995-05-11 | 2001-11-02 | 칼 하인쯔 호르닝어 | 동적 레지스터를 사용한 cmos 회로용 클럭 신호 발생 장치 |
US5949261A (en) | 1996-12-17 | 1999-09-07 | Cypress Semiconductor Corp. | Method and circuit for reducing power and/or current consumption |
US6230245B1 (en) | 1997-02-11 | 2001-05-08 | Micron Technology, Inc. | Method and apparatus for generating a variable sequence of memory device command signals |
US6175894B1 (en) * | 1997-03-05 | 2001-01-16 | Micron Technology, Inc. | Memory device command buffer apparatus and method and memory devices and computer systems using same |
US5996043A (en) | 1997-06-13 | 1999-11-30 | Micron Technology, Inc. | Two step memory device command buffer apparatus and method and memory devices and computer systems using same |
US6484244B1 (en) | 1997-06-17 | 2002-11-19 | Micron Technology, Inc. | Method and system for storing and processing multiple memory commands |
US6178488B1 (en) | 1998-08-27 | 2001-01-23 | Micron Technology, Inc. | Method and apparatus for processing pipelined memory commands |
EP1145024B1 (en) * | 1998-11-13 | 2003-05-14 | Broadcom Corporation | Dynamic register with iddq testing capability |
US6385276B1 (en) | 2001-06-12 | 2002-05-07 | Rf Micro Devices, Inc. | Dual-modulus prescaler |
US6779010B2 (en) | 2001-06-12 | 2004-08-17 | Rf Micro Devices, Inc. | Accumulator with programmable full-scale range |
US7003049B2 (en) * | 2001-06-12 | 2006-02-21 | Rf Micro Devices, Inc. | Fractional-N digital modulation with analog IQ interface |
US6448831B1 (en) | 2001-06-12 | 2002-09-10 | Rf Micro Devices, Inc. | True single-phase flip-flop |
US6693468B2 (en) | 2001-06-12 | 2004-02-17 | Rf Micro Devices, Inc. | Fractional-N synthesizer with improved noise performance |
US6954872B2 (en) * | 2001-09-28 | 2005-10-11 | Intel Corporation | Registering events while clocking multiple domains |
US6917662B2 (en) | 2003-09-11 | 2005-07-12 | International Business Machines Corporation | Programmable low-power high-frequency divider |
US7483013B2 (en) * | 2005-05-20 | 2009-01-27 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor circuit, display device, and electronic appliance therewith |
KR100635500B1 (ko) * | 2005-05-24 | 2006-10-17 | 삼성에스디아이 주식회사 | 시프트 레지스터 및 이를 포함하는 유기 전계발광 표시장치 |
US7358787B2 (en) * | 2006-02-28 | 2008-04-15 | International Business Machines Corporation | Dual operational mode CML latch |
TW200929869A (en) * | 2007-12-20 | 2009-07-01 | Realtek Semiconductor Corp | Flip-flop |
US9612609B2 (en) * | 2014-11-18 | 2017-04-04 | Atmel Corporation | Single wire system clock signal generation |
TWI660585B (zh) * | 2018-07-31 | 2019-05-21 | 瑞昱半導體股份有限公司 | 鎖存器電路 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3749936A (en) * | 1971-08-19 | 1973-07-31 | Texas Instruments Inc | Fault protected output buffer |
US3906258A (en) * | 1974-03-04 | 1975-09-16 | Rca Corp | Failure detecting and inhibiting circuit |
US4467285A (en) * | 1981-12-21 | 1984-08-21 | Gte Automatic Electric Labs Inc. | Pulse monitor circuit |
US4598214A (en) * | 1983-10-31 | 1986-07-01 | Texas Instruments Incorporated | Low power shift register latch |
US4633097A (en) * | 1983-11-17 | 1986-12-30 | Motorola, Inc. | Clock monitor circuit and method |
JPS60198618A (ja) * | 1984-03-21 | 1985-10-08 | Oki Electric Ind Co Ltd | ダイナミツク論理回路 |
-
1987
- 1987-06-23 JP JP62154532A patent/JPS641200A/ja active Granted
-
1988
- 1988-06-20 US US07/208,441 patent/US4920282A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPS641200A (en) | 1989-01-05 |
US4920282A (en) | 1990-04-24 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |