JPH04122029A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce junction capacity and base resistance and improve high frequency property such as cut-off frequency, etc., by thinning the total thickness of a first insulating film, a first conductive film, and a second insulating film to the level of a specific value. CONSTITUTION:The first thin insulating film 4 right below a first polysilicon film 5 is etched sideways by isotropic wet etching so as to form 'eaves'. By the quantity of side etching, the width D of a base lead-out part is determined. Next, a second polysilicon film 8 is formed all over the surface to fill the eaves back. By thermal oxidation, the second polysilicon film 8 excluding the part of eaves is converted into a thermal oxide film 9. Next, by the CVD method, a glass layer 10, which contains P-type impurities with a specified thickness is formed all over the surface, and is heat-treated. Next, the glass layer 10 containing impurities is etched anisotropically, and is left in the shape of a sidewall. Next, a third polysilicon film 11 with a specified thickness is formed all over the surface, and the ions of N-type impurities are implanted by ion implantation method or thermal diffusion method, and an emitter is formed, and the element part is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor integrated circuit including a bipolar transistor.

[Conventional technology]

In order to realize a high-speed bipolar transistor with reduced base resistance and base junction capacitance, a transistor has been proposed in which a graft base is formed in a self-aligned manner using a polysilicon film for base extraction as a diffusion source.

This will be explained with reference to FIGS. 2(a) to 2(g).

First, as shown in FIG. 2(a), an N-type epitaxial layer 2 is formed on a P-type silicon substrate 1 having a high concentration N-type buried layer (not shown), and a field oxide film for element isolation is formed. 3 to form a collector region made of the N-type epitaxial layer 2.

Next, a thin first insulating film 4 and a first polysilicon film 5 doped with P-type impurities are formed. In order to lower the base extraction resistance, the thickness of the first polysilicon M5 is 25 mm.
00~4000λ, boron 3~5X1015cm-
``P-type impurity was doped by ion implantation.

Next, Si3N4 film 7aN Si02 film 7b1Si,
A second insulating film 7 made of a Na film 7c is sequentially deposited. In order to form an "eaves" later, the thickness of the first insulating film 4 was set to 1,500 to 3,000 layers. The thickness of the second insulating film 6 was set to 2,500 to 4,000 in consideration of dielectric strength.

Next, as shown in FIG. 2(b), after etching the region of the second insulating film 7 where the base is to be formed to form an opening, the first polysilicon film 5 is etched using the second insulating film 7 as a mask. etching.

Next, as shown in FIG. 2C, a third insulating film 14 is deposited on the entire surface and etched back by RIE to leave side walls made of the third insulating film 14.

Next, as shown in FIG. 2(d), the second insulation 11R7
and the third insulating film 14 as a mask, the thin first insulating film J[! 4 is wet-etched and side-etched to form an "eaves" made of the first polysilicon film 5.
form.

Next, a second polysilicon film 8 with a thickness of 1,500 to 3,000 thick is deposited over the entire surface, and then etched with KOH or hydrazine to fill in the "eaves".

Next, as shown in FIG. 2(e), the impurities in the first polysilicon film 5 are diffused onto the surface of the N-type epitaxial layer 2 through the second polysilicon film 8 to form a graft base 12.
A third oxide film 15 is formed.

Next, as shown in FIG. 2(f), a base 13 is formed by ion implantation, and a fourth 5i3N4IIIE3 is formed on the entire surface.
is formed and etched back by RIE method to form a fourth Si
3N, form a side wall consisting of a film 16, and form a third oxide film 15.
An opening is formed in the area where the emitter is to be formed.

Next, as shown in FIG. 2(g), a third polysilicon film 11 is deposited on the entire surface, and impurities are introduced through the third polysilicon film 11 by ion implantation to form an emitter (not shown). The element section is then completed.

For reference, a cross-sectional view of a case with a wide opening is shown in FIG.

[Problem to be solved by the invention]

The first problem is that when selectively etching the second polysilicon film, differences in etching rate due to differences in impurity concentration and surface orientation of single crystal silicon are utilized.

Therefore, variations in the etching rate due to the impurity concentration introduced into the second polysilicon film and the state of the alkaline etching solution cause variations in the distance between the graft base and emitter, which should be formed with high precision in a self-aligned manner. Ta.

In addition, since it is necessary to use a (100) plane semiconductor substrate with a small etching rate, it is necessary to use MOS on the same substrate.
There are restrictions on forming elements of the mold.

Furthermore, when hydrazine is used as an etching solution, strict control over flammability and carcinogenicity is required.

The second problem is that in conventional transistors, the first insulating film,
When the emitter opening becomes approximately the same size or smaller submicron size compared to the "total film thickness" of the first polysilicon and the second insulating film, impurities from the third polysilicon The disadvantage is that the current does not reach the semiconductor substrate surface sufficiently, and the necessary current amplification factor cannot be obtained.

As a countermeasure for this, it is effective to reduce the total film thickness mentioned above, but if the first insulating film is made thinner (then when the first polysilicon film is etched, the first insulating film will also be etched a little). The entrance of the ``eaves'' is narrower than the back and widens at the end, making it difficult to embed the second polysilicon.
"su" will be included.

Furthermore, this method also has its limitations, since the resistance to protruding the base increases when the first polysilicon is made thinner.

The "total film thickness" is nearly 0.9 μm, the aperture size is reduced by about 0.3 μm on one side due to the side walls, and the graft base spreads by about 0.5 μm on each side, so considering the aspect ratio, the emitter aperture size is The limit was 1.2 μm, and the actual emitter size was about 0.6 μm and the base size was about 2.2 μm.

[Means to solve the problem]

The method for manufacturing a semiconductor device of the present invention includes forming a first thin insulating film on a first conductivity type epitaxial layer formed on a first conductivity type buried layer, a first polysilicon film of a second conductivity type, and a high melting point polysilicon film. A first opening is formed by sequentially forming a conductive film and a second insulating film including a metal silicide film, and selectively removing the second insulating film and the conductive film by anisotropic etching. and using the second insulating film as a mask to
The eaves are formed by side-etching the thin insulating film to form an eaves directly under the conductive film, forming a second polysilicon film on the entire surface to a thickness that will bury the eaves, and thermal oxidation and etching. a step of removing the second polysilicon film on the outside of the second polysilicon film, a step of forming a glass layer containing impurities of the second conductivity type on the entire surface, and a heat treatment to remove the impurities contained in the first polysilicon film. An impurity is introduced into the surface of the epitaxial layer of the first conductivity type through the second polysilicon film to form a graft base of the second conductivity type, and at the same time, a second impurity contained in the glass layer is introduced into the surface of the epitaxial layer of the first conductivity type.
a step of introducing a conductivity type impurity into the surface of the first conductivity type epitaxial layer to form an intrinsic base; a step of leaving the glass layer only on the side surface of the first opening by etching back; The method includes the step of forming an emitter by introducing impurities of the first conductivity type onto the deposited polysilicon film.

〔Example〕

An embodiment of the present invention will be described with reference to FIG. 1(a).

First, as shown in FIG. 1(a), a heavily doped N-type buried layer (not shown) is formed on a P-type silicon substrate 1 to a thickness of 0 over the entire surface.
．． Grow a 5-1.0 μm N-type epitaxial layer.

Next, a field oxide film 3 for element isolation reaching the P-type silicon substrate 1 is formed.

Next, thermal oxidation is applied to the entire surface with a thickness of 200 to 600 people.
A thin insulating film 4 is formed.

Furthermore, a conductive film having a thickness of 1,000 to 2,000 layers is formed, which is made of a first P-type polysilicon film 5 and a high melting point metal silicide film 6.

The first polysilicon film 5 needs to contain a necessary amount of impurity as a source of impurity diffusion into the graft base portion. If the impurity concentration is too high, when the second polysilicon film is thermally oxidized later, the impurity will diffuse into the intended intrinsic base region, so care must be taken. However, the base resistance is determined by the layer resistance of the upper layer of high melting point metal silicide.

Therefore, for example, boron doping into polysilicon is carried out by ion implantation using 1×1013 to 5×10” atoms.
Let it be s/cm2.

Further, a conductive film made of an N-type polysilicon film and a high melting point silicide film is formed for drawing out the collector (not shown).

Next, a second insulating film 7 made of a silicon nitride film having a thickness of 1000 to 2000 μm is formed over the entire surface.

Next, as shown in FIG. 1(b), the second insulating film 7, metal silicide film 6, and first polysilicon film 5 are selectively removed in sequence by anisotropic etching.

Next, as shown in FIG. 1C, the first thin insulating film 4 immediately below the first polysilicon M4 is side-etched by isotropic wet etching to form an "eaves".

The width of the base extraction portion is determined by the amount of side etching. If the aspect ratio of this eaves portion is D/H≧4, it will be difficult to fill in the second polysilicon film 8 later, so when H=500 people, D=1500 people.

Next, as shown in FIG. 1(d), a second polysilicon film 8 is deposited over the entire surface to refill the "eaves". The thickness of the second polysilicon film 8 is preferably 1/2D-D;
= 300 people when there are 500 people.

Next, as shown in FIG. 1(e), the second polysilicon film 8 other than the portion of the eaves 3 is converted into a thermal oxide film 9 by thermal oxidation.

If the thickness of the second polysilicon film 8 is 300, then the thickness is 900.
It can be converted into an oxide film 9 by steam oxidation at 15°C for 15 minutes.

At this time, the impurity concentration contained in the first polysilicon film 5 must be kept at a concentration that does not adversely affect the intended intrinsic base region under these oxidation conditions.

Next, as shown in FIG. 1(f), the thermal oxide film 9 is removed by etching.

Next, as shown in FIG. 1(g), a glass layer 10 containing P-type impurities of 1,000 to 3,000 thick is formed on the entire surface by CVD and heat-treated. At this time, the P-type impurity contained in the first polysilicon film 5 is diffused to form the graft base 12, and the P-type impurity in the impurity-containing glass layer 10 is diffused to form the base 13.

If an impurity different from the base is ion-implanted with high energy before or after introducing the base impurity, the ft.
transistors can be obtained.

Next, as shown in FIG. 1(h), the impurity-containing glass layer 10 is anisotropically etched to leave a sidewall shape.

Next, as shown in Figure 1(i), a thickness of 1000 mm is applied to the entire surface
A third polysilicon film 11 of ~3000 layers is formed, and N
An emitter (not shown) is formed with type impurities by ion implantation or thermal diffusion, and the element portion is completed.

In this embodiment, an NPN transistor among bipolar transistors has been described, but similar effects can be obtained with a PNP transistor.

By providing an impurity doping step for the first polysilicon film, a base forming step, and an emitter forming step for each conductivity type, a complementary circuit can be easily constructed.

〔Effect of the invention〕

The graft base can be formed with high accuracy in a narrow width of 1500λ or less in a self-aligned manner on the outside of the first opening.

Since the semiconductor substrate surface is not exposed to plasma such as RIE, there is no risk of deterioration of transistor characteristics such as an increase in base recombination current.

Since unnecessary portions of the second polysilicon film are removed by oxidation, there is no need to use harmful chemicals such as hydrazine, which facilitates production.

Similarly, when removing unnecessary portions of the second polysilicon film, the base conductivity type and concentration do not matter because the difference in impurity concentration and the difference in crystal plane orientation are not utilized.

The semiconductor substrate crystal planes are (100), (111), (511)
) can be applied to both.

Since the total thickness of the first insulating film, first conductive film, and second insulating film can be reduced to about 1/3 compared to the conventional example, impurity doping into submicron-sized emitters becomes easy.

In this example, the total thickness of the first insulating film, first conductive film, and second conductive film can be reduced to about 0.3 μm,
The size of the opening by the side wall is reduced by approximately 0.15 μm on one side, and the spread of the graft base from one opening is reduced to approximately 0.15 μm on each side.

Therefore, even considering the aspect ratio, the emitter aperture size is reduced to approximately 0.3 μm and the base size is approximately 0.9 μm.

Compared to the conventional example, the emitter area can be reduced to 1/4 and the base area to 1/6.

As a result, submicron bases and emitters can be easily formed, reducing junction capacitance and base resistance.
It is possible to improve high frequency characteristics such as cutoff frequency.

[Brief explanation of drawings]

FIGS. 1(a) to (i) are cross-sectional views showing an embodiment of the present invention in order of process, and FIGS. 2(a) to (g) are sectional views showing a method of manufacturing a semiconductor device including a bipolar transistor according to the prior art in order of process. FIG. 3 is a cross-sectional view showing a conventional semiconductor device with a wide opening. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... N-type epitaxial layer, 3... Field oxide film, 4... First thin insulating film, 5... First P-type polysilicon film, 6...
High melting point metal silicide film, 7... second insulating film, 7a
...Si3N, + film, 7b-8i02 film, 7 c =
S i 3N4 film, 810. a second polysilicon film,
9... Converted thermal oxide film, 10... Impurity-containing glass layer, 11... Third polysilicon film, 2... Graft base, 3... Base, 4... Third insulating film, 5... third oxide film, 16... fourth Si3N4 film.

Claims (1)

[Claims] A first thin insulating film is formed on the epitaxial layer of the first conductivity type formed on the buried layer of the first conductivity type, a conductive film consisting of a first polysilicon film of the second conductivity type and a refractory metal silicide film; a step of sequentially forming a second insulating film, a step of selectively removing the second insulating film and the conductive film by anisotropic etching to form a first opening, and a step of forming a second insulating film. A step of side-etching the first thin insulating film as a mask to form an eaves directly under the conductive film, a step of forming a second polysilicon film on the entire surface to a thickness sufficient to refill the eaves, and a step of thermal oxidation. A step of removing the second polysilicon film on the outside of the eaves by etching, a step of forming a glass layer containing impurities of the second conductivity type on the entire surface, and a heat treatment to remove the first polysilicon film. Introducing impurities contained in the silicon film into the surface of the first conductivity type epitaxial layer through the second polysilicon film to form a graft base of the second conductivity type, and at the same time introducing impurities of the second conductivity type contained in the glass layer. a step of introducing into the surface of the first conductivity type epitaxial layer to form an intrinsic base, a step of leaving the glass layer only on the side surface of the first opening by etching back, and a step of forming a third polysilicon film on the entire surface. and forming an emitter by introducing impurities of a first conductivity type onto the deposited material.